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vci_mem_cache_v3.h @ 2

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1	/* -- c++ --
2	* File : vci_mem_cache_v3.h
3	* Date : 26/10/2008
4	* Copyright : UPMC / LIP6
5	* Authors : Alain Greiner / Eric Guthmuller
6	*
7	* SOCLIB_LGPL_HEADER_BEGIN
8	*
9	* This file is part of SoCLib, GNU LGPLv2.1.
10	*
11	* SoCLib is free software; you can redistribute it and/or modify it
12	* under the terms of the GNU Lesser General Public License as published
13	* by the Free Software Foundation; version 2.1 of the License.
14	*
15	* SoCLib is distributed in the hope that it will be useful, but
16	* WITHOUT ANY WARRANTY; without even the implied warranty of
17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18	* Lesser General Public License for more details.
19	*
20	* You should have received a copy of the GNU Lesser General Public
21	* License along with SoCLib; if not, write to the Free Software
22	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23	* 02110-1301 USA
24	*
25	* SOCLIB_LGPL_HEADER_END
26	*
27	* Maintainers: alain eric.guthmuller@polytechnique.edu
28	*/
29	/*
30	*
31	* Modifications done by Christophe Choichillon on the 7/04/2009:
32	* - Adding new states in the CLEANUP FSM : CLEANUP_UPT_LOCK and CLEANUP_UPT_WRITE
33	* - Adding a new VCI target port for the CLEANUP network
34	* - Adding new state in the ALLOC_UPT_FSM : ALLOC_UPT_CLEANUP
35	*
36	* Modifications to do :
37	* - Adding new variables used by the CLEANUP FSM
38	*
39	*/
40
41	#ifndef SOCLIB_CABA_MEM_CACHE_V3_H
42	#define SOCLIB_CABA_MEM_CACHE_V3_H
43
44	#include <inttypes.h>
45	#include <systemc>
46	#include <list>
47	#include <cassert>
48	#include "arithmetics.h"
49	#include "alloc_elems.h"
50	#include "caba_base_module.h"
51	#include "vci_target.h"
52	#include "vci_initiator.h"
53	#include "generic_fifo.h"
54	#include "mapping_table.h"
55	#include "int_tab.h"
56	#include "mem_cache_directory_v3.h"
57	#include "xram_transaction_v3.h"
58	#include "update_tab_v3.h"
59	#include "atomic_tab_v3.h"
60
61	#define TRANSACTION_TAB_LINES 4 // Number of lines in the transaction tab
62	#define UPDATE_TAB_LINES 4 // Number of lines in the update tab
63	#define BROADCAST_ADDR 0x0000000003 // Address to send the broadcast invalidate
64
65	namespace soclib { namespace caba {
66	using namespace sc_core;
67
68	template<typename vci_param>
69	class VciMemCacheV3
70	: public soclib::caba::BaseModule
71	{
72	typedef sc_dt::sc_uint<40> addr_t;
73	typedef typename vci_param::fast_addr_t vci_addr_t;
74	typedef uint32_t data_t;
75	typedef uint32_t tag_t;
76	typedef uint32_t size_t;
77	typedef uint32_t be_t;
78	typedef uint32_t copy_t;
79
80	/* States of the TGT_CMD fsm */
81	enum tgt_cmd_fsm_state_e{
82	TGT_CMD_IDLE,
83	TGT_CMD_READ,
84	TGT_CMD_READ_EOP,
85	TGT_CMD_WRITE,
86	TGT_CMD_ATOMIC,
87	};
88
89	/* States of the TGT_RSP fsm */
90	enum tgt_rsp_fsm_state_e{
91	TGT_RSP_READ_IDLE,
92	TGT_RSP_WRITE_IDLE,
93	TGT_RSP_LLSC_IDLE,
94	TGT_RSP_XRAM_IDLE,
95	TGT_RSP_INIT_IDLE,
96	TGT_RSP_CLEANUP_IDLE,
97	TGT_RSP_READ,
98	TGT_RSP_WRITE,
99	TGT_RSP_LLSC,
100	TGT_RSP_XRAM,
101	TGT_RSP_INIT,
102	TGT_RSP_CLEANUP,
103	};
104
105	/* States of the INIT_CMD fsm */
106	enum init_cmd_fsm_state_e{
107	INIT_CMD_INVAL_IDLE,
108	INIT_CMD_INVAL_NLINE,
109	INIT_CMD_XRAM_BRDCAST,
110	INIT_CMD_UPDT_IDLE,
111	INIT_CMD_WRITE_BRDCAST,
112	INIT_CMD_UPDT_NLINE,
113	INIT_CMD_UPDT_INDEX,
114	INIT_CMD_UPDT_DATA,
115	INIT_CMD_SC_UPDT_IDLE,
116	INIT_CMD_SC_BRDCAST,
117	INIT_CMD_SC_UPDT_NLINE,
118	INIT_CMD_SC_UPDT_INDEX,
119	INIT_CMD_SC_UPDT_DATA,
120	};
121
122	/* States of the INIT_RSP fsm */
123	enum init_rsp_fsm_state_e{
124	INIT_RSP_IDLE,
125	INIT_RSP_UPT_LOCK,
126	INIT_RSP_UPT_CLEAR,
127	INIT_RSP_END,
128	};
129
130	/* States of the READ fsm */
131	enum read_fsm_state_e{
132	READ_IDLE,
133	READ_DIR_LOCK,
134	READ_DIR_HIT,
135	READ_HEAP_LOCK,
136	READ_HEAP_WRITE,
137	READ_HEAP_ERASE,
138	READ_HEAP_LAST,
139	READ_RSP,
140	READ_TRT_LOCK,
141	READ_TRT_SET,
142	READ_XRAM_REQ,
143	};
144
145	/* States of the WRITE fsm */
146	enum write_fsm_state_e{
147	WRITE_IDLE,
148	WRITE_NEXT,
149	WRITE_DIR_LOCK,
150	WRITE_DIR_HIT_READ,
151	WRITE_DIR_HIT,
152	WRITE_DIR_HIT_RSP,
153	WRITE_UPT_LOCK,
154	WRITE_HEAP_LOCK,
155	WRITE_UPT_REQ,
156	WRITE_UPDATE,
157	WRITE_UPT_DEC,
158	WRITE_RSP,
159	WRITE_TRT_LOCK,
160	WRITE_TRT_DATA,
161	WRITE_TRT_SET,
162	WRITE_WAIT,
163	WRITE_XRAM_REQ,
164	WRITE_TRT_WRITE_LOCK,
165	WRITE_INVAL_LOCK,
166	WRITE_DIR_INVAL,
167	WRITE_INVAL,
168	WRITE_XRAM_SEND,
169	WRITE_HEAP_ERASE,
170	WRITE_HEAP_LAST,
171	};
172
173	/* States of the IXR_RSP fsm */
174	enum ixr_rsp_fsm_state_e{
175	IXR_RSP_IDLE,
176	IXR_RSP_ACK,
177	IXR_RSP_TRT_ERASE,
178	IXR_RSP_TRT_READ,
179	};
180
181	/* States of the XRAM_RSP fsm */
182	enum xram_rsp_fsm_state_e{
183	XRAM_RSP_IDLE,
184	XRAM_RSP_TRT_COPY,
185	XRAM_RSP_TRT_DIRTY,
186	XRAM_RSP_DIR_LOCK,
187	XRAM_RSP_DIR_UPDT,
188	XRAM_RSP_DIR_RSP,
189	XRAM_RSP_INVAL_LOCK,
190	XRAM_RSP_INVAL_WAIT,
191	XRAM_RSP_INVAL,
192	XRAM_RSP_WRITE_DIRTY,
193	XRAM_RSP_HEAP_ERASE,
194	XRAM_RSP_HEAP_LAST,
195	};
196
197	/* States of the IXR_CMD fsm */
198	enum ixr_cmd_fsm_state_e{
199	IXR_CMD_READ_IDLE,
200	IXR_CMD_WRITE_IDLE,
201	IXR_CMD_LLSC_IDLE,
202	IXR_CMD_XRAM_IDLE,
203	IXR_CMD_READ_NLINE,
204	IXR_CMD_WRITE_NLINE,
205	IXR_CMD_LLSC_NLINE,
206	IXR_CMD_XRAM_DATA,
207	};
208
209	/* States of the LLSC fsm */
210	enum llsc_fsm_state_e{
211	LLSC_IDLE,
212	LL_DIR_LOCK,
213	LL_DIR_HIT,
214	LL_RSP,
215	SC_DIR_LOCK,
216	SC_DIR_HIT,
217	SC_UPT_LOCK,
218	SC_WAIT,
219	SC_HEAP_LOCK,
220	SC_UPT_REQ,
221	SC_UPDATE,
222	SC_TRT_LOCK,
223	SC_INVAL_LOCK,
224	SC_DIR_INVAL,
225	SC_INVAL,
226	SC_XRAM_SEND,
227	SC_HEAP_ERASE,
228	SC_HEAP_LAST,
229	SC_RSP_FALSE,
230	SC_RSP_TRUE,
231	LLSC_TRT_LOCK,
232	LLSC_TRT_SET,
233	LLSC_XRAM_REQ,
234	};
235
236	/* States of the CLEANUP fsm */
237	enum cleanup_fsm_state_e{
238	CLEANUP_IDLE,
239	CLEANUP_DIR_LOCK,
240	CLEANUP_DIR_WRITE,
241	CLEANUP_HEAP_LOCK,
242	CLEANUP_HEAP_SEARCH,
243	CLEANUP_HEAP_CLEAN,
244	CLEANUP_HEAP_FREE,
245	CLEANUP_UPT_LOCK,
246	CLEANUP_UPT_WRITE,
247	CLEANUP_WRITE_RSP,
248	CLEANUP_RSP,
249	};
250
251	/* States of the ALLOC_DIR fsm */
252	enum alloc_dir_fsm_state_e{
253	ALLOC_DIR_READ,
254	ALLOC_DIR_WRITE,
255	ALLOC_DIR_LLSC,
256	ALLOC_DIR_CLEANUP,
257	ALLOC_DIR_XRAM_RSP,
258	};
259
260	/* States of the ALLOC_TRT fsm */
261	enum alloc_trt_fsm_state_e{
262	ALLOC_TRT_READ,
263	ALLOC_TRT_WRITE,
264	ALLOC_TRT_LLSC,
265	ALLOC_TRT_XRAM_RSP,
266	ALLOC_TRT_IXR_RSP,
267	};
268
269	/* States of the ALLOC_UPT fsm */
270	enum alloc_upt_fsm_state_e{
271	ALLOC_UPT_WRITE,
272	ALLOC_UPT_XRAM_RSP,
273	ALLOC_UPT_INIT_RSP,
274	ALLOC_UPT_CLEANUP,
275	ALLOC_UPT_LLSC,
276	};
277
278	/* States of the ALLOC_HEAP fsm */
279	enum alloc_heap_fsm_state_e{
280	ALLOC_HEAP_READ,
281	ALLOC_HEAP_WRITE,
282	ALLOC_HEAP_LLSC,
283	ALLOC_HEAP_CLEANUP,
284	ALLOC_HEAP_XRAM_RSP,
285	};
286
287	uint32_t m_cpt_cycles; // Counter of cycles
288	uint32_t m_cpt_read; // Number of READ transactions
289	uint32_t m_cpt_read_miss; // Number of MISS READ
290	uint32_t m_cpt_write; // Number of WRITE transactions
291	uint32_t m_cpt_write_miss; // Number of MISS WRITE
292	uint32_t m_cpt_write_cells; // Cumulated length for WRITE transactions
293	uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions
294	uint32_t m_cpt_update; // Number of UPDATE transactions
295	uint32_t m_cpt_update_mult; // Number of targets for UPDATE
296	uint32_t m_cpt_inval; // Number of INVAL transactions
297	uint32_t m_cpt_inval_mult; // Number of targets for INVAL
298	uint32_t m_cpt_inval_brdcast; // Number of BROADCAST INVAL
299	uint32_t m_cpt_cleanup; // Number of CLEANUP transactions
300	uint32_t m_cpt_ll; // Number of LL transactions
301	uint32_t m_cpt_sc; // Number of SC transactions
302
303	protected:
304
305	SC_HAS_PROCESS(VciMemCacheV3);
306
307	public:
308	sc_in<bool> p_clk;
309	sc_in<bool> p_resetn;
310	soclib::caba::VciTarget<vci_param> p_vci_tgt;
311	soclib::caba::VciTarget<vci_param> p_vci_tgt_cleanup;
312	soclib::caba::VciInitiator<vci_param> p_vci_ini;
313	soclib::caba::VciInitiator<vci_param> p_vci_ixr;
314
315	VciMemCacheV3(
316	sc_module_name name, // Instance Name
317	const soclib::common::MappingTable &mtp, // Mapping table for primary requets
318	const soclib::common::MappingTable &mtc, // Mapping table for coherence requets
319	const soclib::common::MappingTable &mtx, // Mapping table for XRAM
320	const soclib::common::IntTab &vci_ixr_index, // VCI port to XRAM (initiator)
321	const soclib::common::IntTab &vci_ini_index, // VCI port to PROC (initiator)
322	const soclib::common::IntTab &vci_tgt_index, // VCI port to PROC (target)
323	const soclib::common::IntTab &vci_tgt_index_cleanup, // VCI port to PROC (target) for cleanup
324	size_t nways, // Number of ways per set
325	size_t nsets, // Number of sets
326	size_t nwords, // Number of words per line
327	size_t heap_size=1024); // Size of the heap
328
329	~VciMemCacheV3();
330
331	void transition();
332
333	void genMoore();
334
335	void print_stats();
336
337	private:
338
339	// Component attributes
340	const size_t m_initiators; // Number of initiators
341	const size_t m_heap_size; // Size of the heap
342	const size_t m_ways; // Number of ways in a set
343	const size_t m_sets; // Number of cache sets
344	const size_t m_words; // Number of words in a line
345	const size_t m_srcid_ixr; // Srcid for requests to XRAM
346	const size_t m_srcid_ini; // Srcid for requests to processors
347	std::list<soclib::common::Segment> m_seglist; // memory cached into the cache
348	std::list<soclib::common::Segment> m_cseglist; // coherence segment for the cache
349	vci_addr_t *m_coherence_table; // address(srcid)
350	AtomicTab m_atomic_tab; // atomic access table
351	TransactionTab m_transaction_tab; // xram transaction table
352	UpdateTab m_update_tab; // pending update & invalidate
353	CacheDirectory m_cache_directory; // data cache directory
354	HeapDirectory m_heap_directory; // heap directory
355
356	data_t ***m_cache_data; // data array[set][way][word]
357
358	// adress masks
359	const soclib::common::AddressMaskingTable<vci_addr_t> m_x;
360	const soclib::common::AddressMaskingTable<vci_addr_t> m_y;
361	const soclib::common::AddressMaskingTable<vci_addr_t> m_z;
362	const soclib::common::AddressMaskingTable<vci_addr_t> m_nline;
363
364	//////////////////////////////////////////////////
365	// Others registers
366	//////////////////////////////////////////////////
367	sc_signal<size_t> r_copies_limit; // Limit of the number of copies for one line
368
369	//////////////////////////////////////////////////
370	// Registers controlled by the TGT_CMD fsm
371	//////////////////////////////////////////////////
372
373	// Fifo between TGT_CMD fsm and READ fsm
374	GenericFifo<uint64_t> m_cmd_read_addr_fifo;
375	GenericFifo<size_t> m_cmd_read_length_fifo;
376	GenericFifo<size_t> m_cmd_read_srcid_fifo;
377	GenericFifo<size_t> m_cmd_read_trdid_fifo;
378	GenericFifo<size_t> m_cmd_read_pktid_fifo;
379
380	// Fifo between TGT_CMD fsm and WRITE fsm
381	GenericFifo<uint64_t> m_cmd_write_addr_fifo;
382	GenericFifo<bool> m_cmd_write_eop_fifo;
383	GenericFifo<size_t> m_cmd_write_srcid_fifo;
384	GenericFifo<size_t> m_cmd_write_trdid_fifo;
385	GenericFifo<size_t> m_cmd_write_pktid_fifo;
386	GenericFifo<data_t> m_cmd_write_data_fifo;
387	GenericFifo<be_t> m_cmd_write_be_fifo;
388
389	// Fifo between TGT_CMD fsm and LLSC fsm
390	GenericFifo<uint64_t> m_cmd_llsc_addr_fifo;
391	GenericFifo<bool> m_cmd_llsc_sc_fifo;
392	GenericFifo<size_t> m_cmd_llsc_srcid_fifo;
393	GenericFifo<size_t> m_cmd_llsc_trdid_fifo;
394	GenericFifo<size_t> m_cmd_llsc_pktid_fifo;
395	GenericFifo<data_t> m_cmd_llsc_wdata_fifo;
396
397	sc_signal<int> r_tgt_cmd_fsm;
398
399	sc_signal<size_t> r_index;
400	size_t nseg;
401	size_t ncseg;
402	soclib::common::Segment **m_seg;
403	soclib::common::Segment **m_cseg;
404	///////////////////////////////////////////////////////
405	// Registers controlled by the READ fsm
406	///////////////////////////////////////////////////////
407
408	sc_signal<int> r_read_fsm; // FSM state
409	sc_signal<size_t> r_read_copy; // Srcid of the first copy
410	sc_signal<bool> r_read_copy_inst; // Type of the first copy
411	sc_signal<tag_t> r_read_tag; // cache line tag (in directory)
412	sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory)
413	sc_signal<bool> r_read_lock; // lock bit (in directory)
414	sc_signal<bool> r_read_dirty; // dirty bit (in directory)
415	sc_signal<bool> r_read_inst; // it is an instruction line
416	sc_signal<size_t> r_read_count; // number of copies
417	sc_signal<size_t> r_read_ptr; // pointer to the heap
418	sc_signal<data_t> *r_read_data; // data (one cache line)
419	sc_signal<size_t> r_read_way; // associative way (in cache)
420	sc_signal<size_t> r_read_trt_index; // Transaction Table index
421	sc_signal<size_t> r_read_next_ptr; // Next entry to point to
422	sc_signal<bool> r_read_last_free; // Last free entry
423
424	// Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
425	sc_signal<bool> r_read_to_ixr_cmd_req; // valid request
426	sc_signal<addr_t> r_read_to_ixr_cmd_nline; // cache line index
427	sc_signal<size_t> r_read_to_ixr_cmd_trdid; // index in Transaction Table
428
429	// Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
430	sc_signal<bool> r_read_to_tgt_rsp_req; // valid request
431	sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid
432	sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid
433	sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid
434	sc_signal<data_t> *r_read_to_tgt_rsp_data; // data (one cache line)
435	sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response
436	sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response
437
438	///////////////////////////////////////////////////////////////
439	// Registers controlled by the WRITE fsm
440	///////////////////////////////////////////////////////////////
441
442	sc_signal<int> r_write_fsm; // FSM state
443	sc_signal<addr_t> r_write_address; // first word address
444	sc_signal<size_t> r_write_word_index; // first word index in line
445	sc_signal<size_t> r_write_word_count; // number of words in line
446	sc_signal<size_t> r_write_srcid; // transaction srcid
447	sc_signal<size_t> r_write_trdid; // transaction trdid
448	sc_signal<size_t> r_write_pktid; // transaction pktid
449	sc_signal<data_t> *r_write_data; // data (one cache line)
450	sc_signal<be_t> *r_write_be; // one byte enable per word
451	sc_signal<bool> r_write_byte; // is it a byte write
452	sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory)
453	sc_signal<bool> r_write_lock; // lock bit (in directory)
454	sc_signal<bool> r_write_inst; // instruction bit
455	sc_signal<tag_t> r_write_tag; // cache line tag (in directory)
456	sc_signal<size_t> r_write_copy; // first owner of the line
457	sc_signal<bool> r_write_copy_inst; // is this owner a ICache ?
458	sc_signal<size_t> r_write_count; // number of copies
459	sc_signal<size_t> r_write_ptr; // pointer to the heap
460	sc_signal<size_t> r_write_next_ptr; // next pointer to the heap
461	sc_signal<bool> r_write_to_dec; // need to decrement update counter
462	sc_signal<size_t> r_write_way; // way of the line
463	sc_signal<size_t> r_write_trt_index; // index in Transaction Table
464	sc_signal<size_t> r_write_upt_index; // index in Update Table
465
466	// Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
467	sc_signal<bool> r_write_to_tgt_rsp_req; // valid request
468	sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid
469	sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid
470	sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid
471
472	// Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
473	sc_signal<bool> r_write_to_ixr_cmd_req; // valid request
474	sc_signal<bool> r_write_to_ixr_cmd_write; // write request
475	sc_signal<addr_t> r_write_to_ixr_cmd_nline; // cache line index
476	sc_signal<data_t> *r_write_to_ixr_cmd_data; // cache line data
477	sc_signal<size_t> r_write_to_ixr_cmd_trdid; // index in Transaction Table
478
479	// Buffer between WRITE fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
480	sc_signal<bool> r_write_to_init_cmd_multi_req; // valid multicast request
481	sc_signal<bool> r_write_to_init_cmd_brdcast_req; // valid brdcast request
482	sc_signal<addr_t> r_write_to_init_cmd_nline; // cache line index
483	sc_signal<size_t> r_write_to_init_cmd_trdid; // index in Update Table
484	sc_signal<data_t> *r_write_to_init_cmd_data; // data (one cache line)
485	sc_signal<bool> *r_write_to_init_cmd_we; // word enable
486	sc_signal<size_t> r_write_to_init_cmd_count; // number of words in line
487	sc_signal<size_t> r_write_to_init_cmd_index; // index of first word in line
488	GenericFifo<bool> m_write_to_init_cmd_inst_fifo; // fifo for the L1 type
489	GenericFifo<size_t> m_write_to_init_cmd_srcid_fifo; // fifo for srcids
490
491	// Buffer between WRITE fsm and INIT_RSP fsm (Decrement UPT entry)
492	sc_signal<bool> r_write_to_init_rsp_req; // valid request
493	sc_signal<size_t> r_write_to_init_rsp_upt_index; // index in update table
494
495	/////////////////////////////////////////////////////////
496	// Registers controlled by INIT_RSP fsm
497	//////////////////////////////////////////////////////////
498
499	sc_signal<int> r_init_rsp_fsm; // FSM state
500	sc_signal<size_t> r_init_rsp_upt_index; // index in the Update Table
501	sc_signal<size_t> r_init_rsp_srcid; // pending write srcid
502	sc_signal<size_t> r_init_rsp_trdid; // pending write trdid
503	sc_signal<size_t> r_init_rsp_pktid; // pending write pktid
504	sc_signal<addr_t> r_init_rsp_nline; // pending write nline
505
506	// Buffer between INIT_RSP fsm and TGT_RSP fsm (complete write/update transaction)
507	sc_signal<bool> r_init_rsp_to_tgt_rsp_req; // valid request
508	sc_signal<size_t> r_init_rsp_to_tgt_rsp_srcid; // Transaction srcid
509	sc_signal<size_t> r_init_rsp_to_tgt_rsp_trdid; // Transaction trdid
510	sc_signal<size_t> r_init_rsp_to_tgt_rsp_pktid; // Transaction pktid
511
512	///////////////////////////////////////////////////////
513	// Registers controlled by CLEANUP fsm
514	///////////////////////////////////////////////////////
515
516	sc_signal<int> r_cleanup_fsm; // FSM state
517	sc_signal<size_t> r_cleanup_srcid; // transaction srcid
518	sc_signal<size_t> r_cleanup_trdid; // transaction trdid
519	sc_signal<size_t> r_cleanup_pktid; // transaction pktid
520	sc_signal<addr_t> r_cleanup_nline; // cache line index
521
522	sc_signal<copy_t> r_cleanup_copy; // first copy
523	sc_signal<size_t> r_cleanup_copy_inst; // type of the first copy
524	sc_signal<copy_t> r_cleanup_count; // number of copies
525	sc_signal<size_t> r_cleanup_ptr; // pointer to the heap
526	sc_signal<size_t> r_cleanup_prev_ptr; // previous pointer to the heap
527	sc_signal<size_t> r_cleanup_prev_srcid; // srcid of previous heap entry
528	sc_signal<bool> r_cleanup_prev_inst; // inst bit of previous heap entry
529	sc_signal<size_t> r_cleanup_next_ptr; // next pointer to the heap
530	sc_signal<tag_t> r_cleanup_tag; // cache line tag (in directory)
531	sc_signal<bool> r_cleanup_is_cnt; // inst bit (in directory)
532	sc_signal<bool> r_cleanup_lock; // lock bit (in directory)
533	sc_signal<bool> r_cleanup_inst; // inst bit (in directory)
534	sc_signal<bool> r_cleanup_dirty; // dirty bit (in directory)
535	sc_signal<size_t> r_cleanup_way; // associative way (in cache)
536
537	sc_signal<size_t> r_cleanup_write_srcid; // srcid of write response
538	sc_signal<size_t> r_cleanup_write_trdid; // trdid of write rsp
539	sc_signal<size_t> r_cleanup_write_pktid; // pktid of write rsp
540	sc_signal<bool> r_cleanup_need_rsp; // needs a write rsp
541
542	sc_signal<size_t> r_cleanup_index; // index of the INVAL line (in the UPT)
543
544	// Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
545	sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request
546	sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid
547	sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid
548	sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid
549
550	///////////////////////////////////////////////////////
551	// Registers controlled by LLSC fsm
552	///////////////////////////////////////////////////////
553
554	sc_signal<int> r_llsc_fsm; // FSM state
555	sc_signal<data_t> r_llsc_data; // read data word
556	sc_signal<copy_t> r_llsc_copy; // Srcid of the first copy
557	sc_signal<bool> r_llsc_copy_inst; // Type of the first copy
558	sc_signal<size_t> r_llsc_count; // number of copies
559	sc_signal<size_t> r_llsc_ptr; // pointer to the heap
560	sc_signal<size_t> r_llsc_next_ptr; // next pointer to the heap
561	sc_signal<bool> r_llsc_is_cnt; // is_cnt bit (in directory)
562	sc_signal<bool> r_llsc_dirty; // dirty bit (in directory)
563	sc_signal<bool> r_llsc_inst; // inst bit
564	sc_signal<size_t> r_llsc_way; // way in directory
565	sc_signal<size_t> r_llsc_set; // set in directory
566	sc_signal<data_t> r_llsc_tag; // cache line tag (in directory)
567	sc_signal<size_t> r_llsc_trt_index; // Transaction Table index
568	sc_signal<size_t> r_llsc_upt_index; // Update Table index
569
570	// Buffer between LLSC fsm and INIT_CMD fsm (XRAM read)
571	sc_signal<bool> r_llsc_to_ixr_cmd_req; // valid request
572	sc_signal<addr_t> r_llsc_to_ixr_cmd_nline; // cache line index
573	sc_signal<size_t> r_llsc_to_ixr_cmd_trdid; // index in Transaction Table
574	sc_signal<bool> r_llsc_to_ixr_cmd_write; // write request
575	sc_signal<data_t> *r_llsc_to_ixr_cmd_data; // cache line data
576
577
578	// Buffer between LLSC fsm and TGT_RSP fsm
579	sc_signal<bool> r_llsc_to_tgt_rsp_req; // valid request
580	sc_signal<data_t> r_llsc_to_tgt_rsp_data; // read data word
581	sc_signal<size_t> r_llsc_to_tgt_rsp_srcid; // Transaction srcid
582	sc_signal<size_t> r_llsc_to_tgt_rsp_trdid; // Transaction trdid
583	sc_signal<size_t> r_llsc_to_tgt_rsp_pktid; // Transaction pktid
584
585	// Buffer between LLSC fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
586	sc_signal<bool> r_llsc_to_init_cmd_multi_req; // valid request
587	sc_signal<bool> r_llsc_to_init_cmd_brdcast_req; // brdcast request
588	sc_signal<addr_t> r_llsc_to_init_cmd_nline; // cache line index
589	sc_signal<size_t> r_llsc_to_init_cmd_trdid; // index in Update Table
590	sc_signal<data_t> r_llsc_to_init_cmd_wdata; // data (one word)
591	sc_signal<size_t> r_llsc_to_init_cmd_index; // index of the word in line
592	GenericFifo<bool> m_llsc_to_init_cmd_inst_fifo; // fifo for the L1 type
593	GenericFifo<size_t> m_llsc_to_init_cmd_srcid_fifo; // fifo for srcids
594
595	// Buffer between LLSC fsm and INIT_RSP fsm (Decrement UPT entry)
596	sc_signal<bool> r_llsc_to_init_rsp_req; // valid request
597	sc_signal<size_t> r_llsc_to_init_rsp_upt_index; // index in update table
598
599	////////////////////////////////////////////////////
600	// Registers controlled by the IXR_RSP fsm
601	////////////////////////////////////////////////////
602
603	sc_signal<int> r_ixr_rsp_fsm; // FSM state
604	sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index
605	sc_signal<size_t> r_ixr_rsp_cpt; // word counter
606
607	// Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM)
608	sc_signal<bool> *r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready
609
610	////////////////////////////////////////////////////
611	// Registers controlled by the XRAM_RSP fsm
612	////////////////////////////////////////////////////
613
614	sc_signal<int> r_xram_rsp_fsm; // FSM state
615	sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index
616	TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer
617	sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate
618	sc_signal<bool> r_xram_rsp_victim_is_cnt; // victim line inst bit
619	sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit
620	sc_signal<size_t> r_xram_rsp_victim_way; // victim line way
621	sc_signal<size_t> r_xram_rsp_victim_set; // victim line set
622	sc_signal<addr_t> r_xram_rsp_victim_nline; // victim line index
623	sc_signal<copy_t> r_xram_rsp_victim_copy; // victim line first copy
624	sc_signal<bool> r_xram_rsp_victim_copy_inst; // victim line type of first copy
625	sc_signal<size_t> r_xram_rsp_victim_count; // victim line number of copies
626	sc_signal<size_t> r_xram_rsp_victim_ptr; // victim line pointer to the heap
627	sc_signal<data_t> *r_xram_rsp_victim_data; // victim line data
628	sc_signal<size_t> r_xram_rsp_upt_index; // UPT entry index
629	sc_signal<size_t> r_xram_rsp_next_ptr; // Next pointer to the heap
630
631	// Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache)
632	sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request
633	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid
634	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid
635	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid
636	sc_signal<data_t> *r_xram_rsp_to_tgt_rsp_data; // data (one cache line)
637	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_word; // first word index
638	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length;// length of the response
639
640	// Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches)
641	sc_signal<bool> r_xram_rsp_to_init_cmd_multi_req; // Valid request
642	sc_signal<bool> r_xram_rsp_to_init_cmd_brdcast_req; // Broadcast request
643	sc_signal<addr_t> r_xram_rsp_to_init_cmd_nline; // cache line index;
644	sc_signal<size_t> r_xram_rsp_to_init_cmd_trdid; // index of UPT entry
645	GenericFifo<bool> m_xram_rsp_to_init_cmd_inst_fifo; // fifo for the L1 type
646	GenericFifo<size_t> m_xram_rsp_to_init_cmd_srcid_fifo; // fifo for srcids
647
648	// Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
649	sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request
650	sc_signal<addr_t> r_xram_rsp_to_ixr_cmd_nline; // cache line index
651	sc_signal<data_t> *r_xram_rsp_to_ixr_cmd_data; // cache line data
652	sc_signal<size_t> r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table
653
654	////////////////////////////////////////////////////
655	// Registers controlled by the IXR_CMD fsm
656	////////////////////////////////////////////////////
657
658	sc_signal<int> r_ixr_cmd_fsm;
659	sc_signal<size_t> r_ixr_cmd_cpt;
660
661	////////////////////////////////////////////////////
662	// Registers controlled by TGT_RSP fsm
663	////////////////////////////////////////////////////
664
665	sc_signal<int> r_tgt_rsp_fsm;
666	sc_signal<size_t> r_tgt_rsp_cpt;
667
668	////////////////////////////////////////////////////
669	// Registers controlled by INIT_CMD fsm
670	////////////////////////////////////////////////////
671
672	sc_signal<int> r_init_cmd_fsm;
673	sc_signal<size_t> r_init_cmd_cpt;
674	sc_signal<bool> r_init_cmd_inst;
675
676	////////////////////////////////////////////////////
677	// Registers controlled by ALLOC_DIR fsm
678	////////////////////////////////////////////////////
679
680	sc_signal<int> r_alloc_dir_fsm;
681
682	////////////////////////////////////////////////////
683	// Registers controlled by ALLOC_TRT fsm
684	////////////////////////////////////////////////////
685
686	sc_signal<int> r_alloc_trt_fsm;
687
688	////////////////////////////////////////////////////
689	// Registers controlled by ALLOC_UPT fsm
690	////////////////////////////////////////////////////
691
692	sc_signal<int> r_alloc_upt_fsm;
693
694	////////////////////////////////////////////////////
695	// Registers controlled by ALLOC_HEAP fsm
696	////////////////////////////////////////////////////
697
698	sc_signal<int> r_alloc_heap_fsm;
699
700	}; // end class VciMemCacheV3
701
702	}}
703
704	#endif
705
706	// Local Variables:
707	// tab-width: 4
708	// c-basic-offset: 4
709	// c-file-offsets:((innamespace . 0)(inline-open . 0))
710	// indent-tabs-mode: nil
711	// End:
712
713	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
714

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