source: trunk/modules/vci_mem_cache_v4/caba/metadata/vci_mem_cache_v4.sd @ 273

Last change on this file since 273 was 273, checked in by cfuguet, 11 years ago

Modificating the VCI Memory Cache to align the VHDL and the SOCLIB models.
The primary modification consists to add a state DIR_REQ or HEAP_REQ, in all
FSMs using these two structures.

In these states a FSM take the lock of the DIRECTORY or HEAP, respectively,
and at the end of the cycle sends the READ request. Is in the next cycle,
when the response of the READ is obtained.

With this modifications, the behavior of a Synchonous RAM is emulated.
  • Property svn:eol-style set to native
  • Property svn:executable set to *
  • Property svn:keywords set to "Author Date Id Rev URL Revision"
  • Property svn:mime-type set to text/plain
File size: 2.0 KB
Line 
1
2# -*- python -*-
3
4__id__ = "$Id: vci_mem_cache_v4.sd 273 2012-11-28 10:51:48Z cfuguet $"
5__version__ = "$Revision: 273 $"
6
7Module('caba:vci_mem_cache_v4',
8        classname = 'soclib::caba::VciMemCacheV4',
9
10        tmpl_parameters = [ parameter.Module('vci_param', default = 'caba:vci_param') ],
11
12        header_files = [
13            '../source/include/vci_mem_cache_v4.h',
14            '../source/include/xram_transaction_v4.h',
15            '../source/include/mem_cache_directory_v4.h',
16            '../source/include/update_tab_v4.h'
17        ],
18
19        implementation_files = [ '../source/src/vci_mem_cache_v4.cpp' ],
20
21        uses = [
22            Uses('caba:base_module'),
23            Uses('common:loader'),
24            Uses('common:mapping_table'),
25            Uses('caba:generic_fifo'),
26        ],
27
28        ports = [
29            Port( 'caba:vci_target'   , 'p_vci_tgt' ),
30            Port( 'caba:vci_target'   , 'p_vci_tgt_cleanup' ),
31            Port( 'caba:vci_initiator', 'p_vci_ini' ),
32            Port( 'caba:vci_initiator', 'p_vci_ixr' ),
33            Port( 'caba:bit_in'       , 'p_resetn'  , auto = 'resetn' ),
34            Port( 'caba:clock_in'     , 'p_clk'     , auto = 'clock'  ),
35        ],
36
37        instance_parameters = [
38            parameter.Module( 'mtp', 'common:mapping_table' ),
39            parameter.Module( 'mtc', 'common:mapping_table' ),
40            parameter.Module( 'mtx', 'common:mapping_table' ),
41            parameter.IntTab( 'vci_ixr_index' ),
42            parameter.IntTab( 'vci_ini_index' ),
43            parameter.IntTab( 'vci_tgt_index' ),
44            parameter.IntTab( 'vci_tgt_index_cleanup '),
45            parameter.Int   ( 'nways' ),
46            parameter.Int   ( 'nsets' ),
47            parameter.Int   ( 'nwords' ),
48            parameter.Int   ( 'heap_size' ),
49        ],
50
51        extensions = [
52            'dsx:get_ident='
53            'vci_ini_index:p_vci_ini:mtc,'
54            'vci_tgt_index_cleanup:p_vci_tgt_cleanup:mtc,'
55            'vci_tgt_index:p_vci_tgt:mtp,'
56            'vci_ixr_index:p_vci_ixr:mtx',
57            'dsx:addressable=vci_tgt_index,vci_tgt_index_cleanup',
58        ],
59)
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