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vci_mem_cache_v4.h @ 2

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1	/* -- c++ --
2	* File : vci_mem_cache_v4.h
3	* Date : 26/10/2008
4	* Copyright : UPMC / LIP6
5	* Authors : Alain Greiner / Eric Guthmuller
6	*
7	* SOCLIB_LGPL_HEADER_BEGIN
8	*
9	* This file is part of SoCLib, GNU LGPLv2.1.
10	*
11	* SoCLib is free software; you can redistribute it and/or modify it
12	* under the terms of the GNU Lesser General Public License as published
13	* by the Free Software Foundation; version 2.1 of the License.
14	*
15	* SoCLib is distributed in the hope that it will be useful, but
16	* WITHOUT ANY WARRANTY; without even the implied warranty of
17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18	* Lesser General Public License for more details.
19	*
20	* You should have received a copy of the GNU Lesser General Public
21	* License along with SoCLib; if not, write to the Free Software
22	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23	* 02110-1301 USA
24	*
25	* SOCLIB_LGPL_HEADER_END
26	*
27	* Maintainers: alain eric.guthmuller@polytechnique.edu
28	*/
29	/*
30	*
31	* Modifications done by Christophe Choichillon on the 7/04/2009:
32	* - Adding new states in the CLEANUP FSM : CLEANUP_UPT_LOCK and CLEANUP_UPT_WRITE
33	* - Adding a new VCI target port for the CLEANUP network
34	* - Adding new state in the ALLOC_UPT_FSM : ALLOC_UPT_CLEANUP
35	*
36	* Modifications to do :
37	* - Adding new variables used by the CLEANUP FSM
38	*
39	*/
40
41	#ifndef SOCLIB_CABA_MEM_CACHE_V4_H
42	#define SOCLIB_CABA_MEM_CACHE_V4_H
43
44	#include <inttypes.h>
45	#include <systemc>
46	#include <list>
47	#include <cassert>
48	#include "arithmetics.h"
49	#include "alloc_elems.h"
50	#include "caba_base_module.h"
51	#include "vci_target.h"
52	#include "vci_initiator.h"
53	#include "generic_fifo.h"
54	#include "mapping_table.h"
55	#include "int_tab.h"
56	#include "mem_cache_directory_v4.h"
57	#include "xram_transaction_v4.h"
58	#include "update_tab_v4.h"
59
60	#define TRANSACTION_TAB_LINES 4 // Number of lines in the transaction tab
61	#define UPDATE_TAB_LINES 4 // Number of lines in the update tab
62	#define BROADCAST_ADDR 0x0000000003 // Address to send the broadcast invalidate
63
64	namespace soclib { namespace caba {
65	using namespace sc_core;
66
67	template<typename vci_param>
68	class VciMemCacheV4
69	: public soclib::caba::BaseModule
70	{
71	typedef sc_dt::sc_uint<40> addr_t;
72	typedef typename vci_param::fast_addr_t vci_addr_t;
73	typedef uint32_t data_t;
74	typedef uint32_t tag_t;
75	typedef uint32_t size_t;
76	typedef uint32_t be_t;
77	typedef uint32_t copy_t;
78
79	/* States of the TGT_CMD fsm */
80	enum tgt_cmd_fsm_state_e{
81	TGT_CMD_IDLE,
82	TGT_CMD_READ,
83	TGT_CMD_READ_EOP,
84	TGT_CMD_WRITE,
85	TGT_CMD_ATOMIC,
86	};
87
88	/* States of the TGT_RSP fsm */
89	enum tgt_rsp_fsm_state_e{
90	TGT_RSP_READ_IDLE,
91	TGT_RSP_WRITE_IDLE,
92	TGT_RSP_LLSC_IDLE,
93	TGT_RSP_XRAM_IDLE,
94	TGT_RSP_INIT_IDLE,
95	TGT_RSP_CLEANUP_IDLE,
96	TGT_RSP_READ,
97	TGT_RSP_WRITE,
98	TGT_RSP_LLSC,
99	TGT_RSP_XRAM,
100	TGT_RSP_INIT,
101	TGT_RSP_CLEANUP,
102	};
103
104	/* States of the INIT_CMD fsm */
105	enum init_cmd_fsm_state_e{
106	INIT_CMD_INVAL_IDLE,
107	INIT_CMD_INVAL_NLINE,
108	INIT_CMD_XRAM_BRDCAST,
109	INIT_CMD_UPDT_IDLE,
110	INIT_CMD_WRITE_BRDCAST,
111	INIT_CMD_UPDT_NLINE,
112	INIT_CMD_UPDT_INDEX,
113	INIT_CMD_UPDT_DATA,
114	INIT_CMD_SC_UPDT_IDLE,
115	INIT_CMD_SC_BRDCAST,
116	INIT_CMD_SC_UPDT_NLINE,
117	INIT_CMD_SC_UPDT_INDEX,
118	INIT_CMD_SC_UPDT_DATA,
119	INIT_CMD_SC_UPDT_DATA_HIGH,
120	};
121
122	/* States of the INIT_RSP fsm */
123	enum init_rsp_fsm_state_e{
124	INIT_RSP_IDLE,
125	INIT_RSP_UPT_LOCK,
126	INIT_RSP_UPT_CLEAR,
127	INIT_RSP_END,
128	};
129
130	/* States of the READ fsm */
131	enum read_fsm_state_e{
132	READ_IDLE,
133	READ_DIR_LOCK,
134	READ_DIR_HIT,
135	READ_HEAP_LOCK,
136	READ_HEAP_WRITE,
137	READ_HEAP_ERASE,
138	READ_HEAP_LAST,
139	READ_RSP,
140	READ_TRT_LOCK,
141	READ_TRT_SET,
142	READ_XRAM_REQ,
143	};
144
145	/* States of the WRITE fsm */
146	enum write_fsm_state_e{
147	WRITE_IDLE,
148	WRITE_NEXT,
149	WRITE_DIR_LOCK,
150	WRITE_DIR_HIT_READ,
151	WRITE_DIR_HIT,
152	WRITE_UPT_LOCK,
153	WRITE_HEAP_LOCK,
154	WRITE_UPT_REQ,
155	WRITE_UPDATE,
156	WRITE_UPT_DEC,
157	WRITE_RSP,
158	WRITE_TRT_LOCK,
159	WRITE_TRT_DATA,
160	WRITE_TRT_SET,
161	WRITE_WAIT,
162	WRITE_XRAM_REQ,
163	WRITE_TRT_WRITE_LOCK,
164	WRITE_INVAL_LOCK,
165	WRITE_DIR_INVAL,
166	WRITE_INVAL,
167	WRITE_XRAM_SEND,
168	};
169
170	/* States of the IXR_RSP fsm */
171	enum ixr_rsp_fsm_state_e{
172	IXR_RSP_IDLE,
173	IXR_RSP_ACK,
174	IXR_RSP_TRT_ERASE,
175	IXR_RSP_TRT_READ,
176	};
177
178	/* States of the XRAM_RSP fsm */
179	enum xram_rsp_fsm_state_e{
180	XRAM_RSP_IDLE,
181	XRAM_RSP_TRT_COPY,
182	XRAM_RSP_TRT_DIRTY,
183	XRAM_RSP_DIR_LOCK,
184	XRAM_RSP_DIR_UPDT,
185	XRAM_RSP_DIR_RSP,
186	XRAM_RSP_INVAL_LOCK,
187	XRAM_RSP_INVAL_WAIT,
188	XRAM_RSP_INVAL,
189	XRAM_RSP_WRITE_DIRTY,
190	XRAM_RSP_HEAP_ERASE,
191	XRAM_RSP_HEAP_LAST,
192	};
193
194	/* States of the IXR_CMD fsm */
195	enum ixr_cmd_fsm_state_e{
196	IXR_CMD_READ_IDLE,
197	IXR_CMD_WRITE_IDLE,
198	IXR_CMD_LLSC_IDLE,
199	IXR_CMD_XRAM_IDLE,
200	IXR_CMD_READ_NLINE,
201	IXR_CMD_WRITE_NLINE,
202	IXR_CMD_LLSC_NLINE,
203	IXR_CMD_XRAM_DATA,
204	};
205
206	/* States of the LLSC fsm */
207	enum llsc_fsm_state_e{
208	LLSC_IDLE,
209	SC_DIR_LOCK,
210	SC_DIR_HIT_READ,
211	SC_DIR_HIT_WRITE,
212	SC_UPT_LOCK,
213	SC_WAIT,
214	SC_HEAP_LOCK,
215	SC_UPT_REQ,
216	SC_UPDATE,
217	SC_TRT_LOCK,
218	SC_INVAL_LOCK,
219	SC_DIR_INVAL,
220	SC_INVAL,
221	SC_XRAM_SEND,
222	SC_RSP_FALSE,
223	SC_RSP_TRUE,
224	LLSC_TRT_LOCK,
225	LLSC_TRT_SET,
226	LLSC_XRAM_REQ,
227	};
228
229	/* States of the CLEANUP fsm */
230	enum cleanup_fsm_state_e{
231	CLEANUP_IDLE,
232	CLEANUP_DIR_LOCK,
233	CLEANUP_DIR_WRITE,
234	CLEANUP_HEAP_LOCK,
235	CLEANUP_HEAP_SEARCH,
236	CLEANUP_HEAP_CLEAN,
237	CLEANUP_HEAP_FREE,
238	CLEANUP_UPT_LOCK,
239	CLEANUP_UPT_WRITE,
240	CLEANUP_WRITE_RSP,
241	CLEANUP_RSP,
242	};
243
244	/* States of the ALLOC_DIR fsm */
245	enum alloc_dir_fsm_state_e{
246	ALLOC_DIR_READ,
247	ALLOC_DIR_WRITE,
248	ALLOC_DIR_LLSC,
249	ALLOC_DIR_CLEANUP,
250	ALLOC_DIR_XRAM_RSP,
251	};
252
253	/* States of the ALLOC_TRT fsm */
254	enum alloc_trt_fsm_state_e{
255	ALLOC_TRT_READ,
256	ALLOC_TRT_WRITE,
257	ALLOC_TRT_LLSC,
258	ALLOC_TRT_XRAM_RSP,
259	ALLOC_TRT_IXR_RSP,
260	};
261
262	/* States of the ALLOC_UPT fsm */
263	enum alloc_upt_fsm_state_e{
264	ALLOC_UPT_WRITE,
265	ALLOC_UPT_XRAM_RSP,
266	ALLOC_UPT_INIT_RSP,
267	ALLOC_UPT_CLEANUP,
268	ALLOC_UPT_LLSC,
269	};
270
271	/* States of the ALLOC_HEAP fsm */
272	enum alloc_heap_fsm_state_e{
273	ALLOC_HEAP_READ,
274	ALLOC_HEAP_WRITE,
275	ALLOC_HEAP_LLSC,
276	ALLOC_HEAP_CLEANUP,
277	ALLOC_HEAP_XRAM_RSP,
278	};
279
280	uint32_t m_cpt_cycles; // Counter of cycles
281	uint32_t m_cpt_read; // Number of READ transactions
282	uint32_t m_cpt_read_miss; // Number of MISS READ
283	uint32_t m_cpt_write; // Number of WRITE transactions
284	uint32_t m_cpt_write_miss; // Number of MISS WRITE
285	uint32_t m_cpt_write_cells; // Cumulated length for WRITE transactions
286	uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions
287	uint32_t m_cpt_update; // Number of UPDATE transactions
288	uint32_t m_cpt_update_mult; // Number of targets for UPDATE
289	uint32_t m_cpt_inval; // Number of INVAL transactions
290	uint32_t m_cpt_inval_mult; // Number of targets for INVAL
291	uint32_t m_cpt_inval_brdcast; // Number of BROADCAST INVAL
292	uint32_t m_cpt_cleanup; // Number of CLEANUP transactions
293	uint32_t m_cpt_ll; // Number of LL transactions
294	uint32_t m_cpt_sc; // Number of SC transactions
295
296	protected:
297
298	SC_HAS_PROCESS(VciMemCacheV4);
299
300	public:
301	sc_in<bool> p_clk;
302	sc_in<bool> p_resetn;
303	soclib::caba::VciTarget<vci_param> p_vci_tgt;
304	soclib::caba::VciTarget<vci_param> p_vci_tgt_cleanup;
305	soclib::caba::VciInitiator<vci_param> p_vci_ini;
306	soclib::caba::VciInitiator<vci_param> p_vci_ixr;
307
308	VciMemCacheV4(
309	sc_module_name name, // Instance Name
310	const soclib::common::MappingTable &mtp, // Mapping table for primary requets
311	const soclib::common::MappingTable &mtc, // Mapping table for coherence requets
312	const soclib::common::MappingTable &mtx, // Mapping table for XRAM
313	const soclib::common::IntTab &vci_ixr_index, // VCI port to XRAM (initiator)
314	const soclib::common::IntTab &vci_ini_index, // VCI port to PROC (initiator)
315	const soclib::common::IntTab &vci_tgt_index, // VCI port to PROC (target)
316	const soclib::common::IntTab &vci_tgt_index_cleanup, // VCI port to PROC (target) for cleanup
317	size_t nways, // Number of ways per set
318	size_t nsets, // Number of sets
319	size_t nwords, // Number of words per line
320	size_t heap_size=1024); // Size of the heap
321
322	~VciMemCacheV4();
323
324	void transition();
325
326	void genMoore();
327
328	void print_stats();
329
330	private:
331
332	// Component attributes
333	const size_t m_initiators; // Number of initiators
334	const size_t m_heap_size; // Size of the heap
335	const size_t m_ways; // Number of ways in a set
336	const size_t m_sets; // Number of cache sets
337	const size_t m_words; // Number of words in a line
338	const size_t m_srcid_ixr; // Srcid for requests to XRAM
339	const size_t m_srcid_ini; // Srcid for requests to processors
340	std::list<soclib::common::Segment> m_seglist; // memory cached into the cache
341	std::list<soclib::common::Segment> m_cseglist; // coherence segment for the cache
342	vci_addr_t *m_coherence_table; // address(srcid)
343	TransactionTab m_transaction_tab; // xram transaction table
344	UpdateTab m_update_tab; // pending update & invalidate
345	CacheDirectory m_cache_directory; // data cache directory
346	HeapDirectory m_heap_directory; // heap directory
347
348	data_t ***m_cache_data; // data array[set][way][word]
349
350	// adress masks
351	const soclib::common::AddressMaskingTable<vci_addr_t> m_x;
352	const soclib::common::AddressMaskingTable<vci_addr_t> m_y;
353	const soclib::common::AddressMaskingTable<vci_addr_t> m_z;
354	const soclib::common::AddressMaskingTable<vci_addr_t> m_nline;
355
356	//////////////////////////////////////////////////
357	// Others registers
358	//////////////////////////////////////////////////
359	sc_signal<size_t> r_copies_limit; // Limit of the number of copies for one line
360
361	//////////////////////////////////////////////////
362	// Registers controlled by the TGT_CMD fsm
363	//////////////////////////////////////////////////
364
365	// Fifo between TGT_CMD fsm and READ fsm
366	GenericFifo<uint64_t> m_cmd_read_addr_fifo;
367	GenericFifo<size_t> m_cmd_read_length_fifo;
368	GenericFifo<size_t> m_cmd_read_srcid_fifo;
369	GenericFifo<size_t> m_cmd_read_trdid_fifo;
370	GenericFifo<size_t> m_cmd_read_pktid_fifo;
371
372	// Fifo between TGT_CMD fsm and WRITE fsm
373	GenericFifo<uint64_t> m_cmd_write_addr_fifo;
374	GenericFifo<bool> m_cmd_write_eop_fifo;
375	GenericFifo<size_t> m_cmd_write_srcid_fifo;
376	GenericFifo<size_t> m_cmd_write_trdid_fifo;
377	GenericFifo<size_t> m_cmd_write_pktid_fifo;
378	GenericFifo<data_t> m_cmd_write_data_fifo;
379	GenericFifo<be_t> m_cmd_write_be_fifo;
380
381	// Fifo between TGT_CMD fsm and LLSC fsm
382	GenericFifo<uint64_t> m_cmd_llsc_addr_fifo;
383	GenericFifo<bool> m_cmd_llsc_eop_fifo;
384	GenericFifo<size_t> m_cmd_llsc_srcid_fifo;
385	GenericFifo<size_t> m_cmd_llsc_trdid_fifo;
386	GenericFifo<size_t> m_cmd_llsc_pktid_fifo;
387	GenericFifo<data_t> m_cmd_llsc_wdata_fifo;
388
389	sc_signal<int> r_tgt_cmd_fsm;
390
391	sc_signal<size_t> r_index;
392	size_t nseg;
393	size_t ncseg;
394	soclib::common::Segment **m_seg;
395	soclib::common::Segment **m_cseg;
396	///////////////////////////////////////////////////////
397	// Registers controlled by the READ fsm
398	///////////////////////////////////////////////////////
399
400	sc_signal<int> r_read_fsm; // FSM state
401	sc_signal<size_t> r_read_copy; // Srcid of the first copy
402	sc_signal<bool> r_read_copy_inst; // Type of the first copy
403	sc_signal<tag_t> r_read_tag; // cache line tag (in directory)
404	sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory)
405	sc_signal<bool> r_read_lock; // lock bit (in directory)
406	sc_signal<bool> r_read_dirty; // dirty bit (in directory)
407	sc_signal<size_t> r_read_count; // number of copies
408	sc_signal<size_t> r_read_ptr; // pointer to the heap
409	sc_signal<data_t> *r_read_data; // data (one cache line)
410	sc_signal<size_t> r_read_way; // associative way (in cache)
411	sc_signal<size_t> r_read_trt_index; // Transaction Table index
412	sc_signal<size_t> r_read_next_ptr; // Next entry to point to
413	sc_signal<bool> r_read_last_free; // Last free entry
414
415	// Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
416	sc_signal<bool> r_read_to_ixr_cmd_req; // valid request
417	sc_signal<addr_t> r_read_to_ixr_cmd_nline; // cache line index
418	sc_signal<size_t> r_read_to_ixr_cmd_trdid; // index in Transaction Table
419
420	// Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
421	sc_signal<bool> r_read_to_tgt_rsp_req; // valid request
422	sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid
423	sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid
424	sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid
425	sc_signal<data_t> *r_read_to_tgt_rsp_data; // data (one cache line)
426	sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response
427	sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response
428
429	///////////////////////////////////////////////////////////////
430	// Registers controlled by the WRITE fsm
431	///////////////////////////////////////////////////////////////
432
433	sc_signal<int> r_write_fsm; // FSM state
434	sc_signal<addr_t> r_write_address; // first word address
435	sc_signal<size_t> r_write_word_index; // first word index in line
436	sc_signal<size_t> r_write_word_count; // number of words in line
437	sc_signal<size_t> r_write_srcid; // transaction srcid
438	sc_signal<size_t> r_write_trdid; // transaction trdid
439	sc_signal<size_t> r_write_pktid; // transaction pktid
440	sc_signal<data_t> *r_write_data; // data (one cache line)
441	sc_signal<be_t> *r_write_be; // one byte enable per word
442	sc_signal<bool> r_write_byte; // is it a byte write
443	sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory)
444	sc_signal<bool> r_write_lock; // lock bit (in directory)
445	sc_signal<tag_t> r_write_tag; // cache line tag (in directory)
446	sc_signal<size_t> r_write_copy; // first owner of the line
447	sc_signal<bool> r_write_copy_inst; // is this owner a ICache ?
448	sc_signal<size_t> r_write_count; // number of copies
449	sc_signal<size_t> r_write_ptr; // pointer to the heap
450	sc_signal<size_t> r_write_next_ptr; // next pointer to the heap
451	sc_signal<bool> r_write_to_dec; // need to decrement update counter
452	sc_signal<size_t> r_write_way; // way of the line
453	sc_signal<size_t> r_write_trt_index; // index in Transaction Table
454	sc_signal<size_t> r_write_upt_index; // index in Update Table
455
456	// Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
457	sc_signal<bool> r_write_to_tgt_rsp_req; // valid request
458	sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid
459	sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid
460	sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid
461
462	// Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
463	sc_signal<bool> r_write_to_ixr_cmd_req; // valid request
464	sc_signal<bool> r_write_to_ixr_cmd_write; // write request
465	sc_signal<addr_t> r_write_to_ixr_cmd_nline; // cache line index
466	sc_signal<data_t> *r_write_to_ixr_cmd_data; // cache line data
467	sc_signal<size_t> r_write_to_ixr_cmd_trdid; // index in Transaction Table
468
469	// Buffer between WRITE fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
470	sc_signal<bool> r_write_to_init_cmd_multi_req; // valid multicast request
471	sc_signal<bool> r_write_to_init_cmd_brdcast_req; // valid brdcast request
472	sc_signal<addr_t> r_write_to_init_cmd_nline; // cache line index
473	sc_signal<size_t> r_write_to_init_cmd_trdid; // index in Update Table
474	sc_signal<data_t> *r_write_to_init_cmd_data; // data (one cache line)
475	sc_signal<be_t> *r_write_to_init_cmd_be; // word enable
476	sc_signal<size_t> r_write_to_init_cmd_count; // number of words in line
477	sc_signal<size_t> r_write_to_init_cmd_index; // index of first word in line
478	GenericFifo<bool> m_write_to_init_cmd_inst_fifo; // fifo for the L1 type
479	GenericFifo<size_t> m_write_to_init_cmd_srcid_fifo; // fifo for srcids
480
481	// Buffer between WRITE fsm and INIT_RSP fsm (Decrement UPT entry)
482	sc_signal<bool> r_write_to_init_rsp_req; // valid request
483	sc_signal<size_t> r_write_to_init_rsp_upt_index; // index in update table
484
485	/////////////////////////////////////////////////////////
486	// Registers controlled by INIT_RSP fsm
487	//////////////////////////////////////////////////////////
488
489	sc_signal<int> r_init_rsp_fsm; // FSM state
490	sc_signal<size_t> r_init_rsp_upt_index; // index in the Update Table
491	sc_signal<size_t> r_init_rsp_srcid; // pending write srcid
492	sc_signal<size_t> r_init_rsp_trdid; // pending write trdid
493	sc_signal<size_t> r_init_rsp_pktid; // pending write pktid
494	sc_signal<addr_t> r_init_rsp_nline; // pending write nline
495
496	// Buffer between INIT_RSP fsm and TGT_RSP fsm (complete write/update transaction)
497	sc_signal<bool> r_init_rsp_to_tgt_rsp_req; // valid request
498	sc_signal<size_t> r_init_rsp_to_tgt_rsp_srcid; // Transaction srcid
499	sc_signal<size_t> r_init_rsp_to_tgt_rsp_trdid; // Transaction trdid
500	sc_signal<size_t> r_init_rsp_to_tgt_rsp_pktid; // Transaction pktid
501
502	///////////////////////////////////////////////////////
503	// Registers controlled by CLEANUP fsm
504	///////////////////////////////////////////////////////
505
506	sc_signal<int> r_cleanup_fsm; // FSM state
507	sc_signal<size_t> r_cleanup_srcid; // transaction srcid
508	sc_signal<size_t> r_cleanup_trdid; // transaction trdid
509	sc_signal<size_t> r_cleanup_pktid; // transaction pktid
510	sc_signal<addr_t> r_cleanup_nline; // cache line index
511
512	sc_signal<copy_t> r_cleanup_copy; // first copy
513	sc_signal<size_t> r_cleanup_copy_inst; // type of the first copy
514	sc_signal<copy_t> r_cleanup_count; // number of copies
515	sc_signal<size_t> r_cleanup_ptr; // pointer to the heap
516	sc_signal<size_t> r_cleanup_prev_ptr; // previous pointer to the heap
517	sc_signal<size_t> r_cleanup_prev_srcid; // srcid of previous heap entry
518	sc_signal<bool> r_cleanup_prev_inst; // inst bit of previous heap entry
519	sc_signal<size_t> r_cleanup_next_ptr; // next pointer to the heap
520	sc_signal<tag_t> r_cleanup_tag; // cache line tag (in directory)
521	sc_signal<bool> r_cleanup_is_cnt; // inst bit (in directory)
522	sc_signal<bool> r_cleanup_lock; // lock bit (in directory)
523	sc_signal<bool> r_cleanup_dirty; // dirty bit (in directory)
524	sc_signal<size_t> r_cleanup_way; // associative way (in cache)
525
526	sc_signal<size_t> r_cleanup_write_srcid; // srcid of write response
527	sc_signal<size_t> r_cleanup_write_trdid; // trdid of write rsp
528	sc_signal<size_t> r_cleanup_write_pktid; // pktid of write rsp
529	sc_signal<bool> r_cleanup_need_rsp; // needs a write rsp
530
531	sc_signal<size_t> r_cleanup_index; // index of the INVAL line (in the UPT)
532
533	// Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
534	sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request
535	sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid
536	sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid
537	sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid
538
539	///////////////////////////////////////////////////////
540	// Registers controlled by LLSC fsm
541	///////////////////////////////////////////////////////
542
543	sc_signal<int> r_llsc_fsm; // FSM state
544	sc_signal<data_t> r_llsc_wdata; // write data word
545	sc_signal<data_t> *r_llsc_rdata; // read data word
546	sc_signal<uint32_t> r_llsc_lfsr; // lfsr for random introducing
547	sc_signal<size_t> r_llsc_cpt; // size of command
548	sc_signal<copy_t> r_llsc_copy; // Srcid of the first copy
549	sc_signal<bool> r_llsc_copy_inst; // Type of the first copy
550	sc_signal<size_t> r_llsc_count; // number of copies
551	sc_signal<size_t> r_llsc_ptr; // pointer to the heap
552	sc_signal<size_t> r_llsc_next_ptr; // next pointer to the heap
553	sc_signal<bool> r_llsc_is_cnt; // is_cnt bit (in directory)
554	sc_signal<bool> r_llsc_dirty; // dirty bit (in directory)
555	sc_signal<size_t> r_llsc_way; // way in directory
556	sc_signal<size_t> r_llsc_set; // set in directory
557	sc_signal<data_t> r_llsc_tag; // cache line tag (in directory)
558	sc_signal<size_t> r_llsc_trt_index; // Transaction Table index
559	sc_signal<size_t> r_llsc_upt_index; // Update Table index
560
561	// Buffer between LLSC fsm and INIT_CMD fsm (XRAM read)
562	sc_signal<bool> r_llsc_to_ixr_cmd_req; // valid request
563	sc_signal<addr_t> r_llsc_to_ixr_cmd_nline; // cache line index
564	sc_signal<size_t> r_llsc_to_ixr_cmd_trdid; // index in Transaction Table
565	sc_signal<bool> r_llsc_to_ixr_cmd_write; // write request
566	sc_signal<data_t> *r_llsc_to_ixr_cmd_data; // cache line data
567
568
569	// Buffer between LLSC fsm and TGT_RSP fsm
570	sc_signal<bool> r_llsc_to_tgt_rsp_req; // valid request
571	sc_signal<data_t> r_llsc_to_tgt_rsp_data; // read data word
572	sc_signal<size_t> r_llsc_to_tgt_rsp_srcid; // Transaction srcid
573	sc_signal<size_t> r_llsc_to_tgt_rsp_trdid; // Transaction trdid
574	sc_signal<size_t> r_llsc_to_tgt_rsp_pktid; // Transaction pktid
575
576	// Buffer between LLSC fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
577	sc_signal<bool> r_llsc_to_init_cmd_multi_req; // valid request
578	sc_signal<bool> r_llsc_to_init_cmd_brdcast_req; // brdcast request
579	sc_signal<addr_t> r_llsc_to_init_cmd_nline; // cache line index
580	sc_signal<size_t> r_llsc_to_init_cmd_trdid; // index in Update Table
581	sc_signal<data_t> r_llsc_to_init_cmd_wdata; // data (one word)
582	sc_signal<bool> r_llsc_to_init_cmd_is_long; // it is a 64 bits SC
583	sc_signal<data_t> r_llsc_to_init_cmd_wdata_high; // data high (one word)
584	sc_signal<size_t> r_llsc_to_init_cmd_index; // index of the word in line
585	GenericFifo<bool> m_llsc_to_init_cmd_inst_fifo; // fifo for the L1 type
586	GenericFifo<size_t> m_llsc_to_init_cmd_srcid_fifo; // fifo for srcids
587
588	// Buffer between LLSC fsm and INIT_RSP fsm (Decrement UPT entry)
589	sc_signal<bool> r_llsc_to_init_rsp_req; // valid request
590	sc_signal<size_t> r_llsc_to_init_rsp_upt_index; // index in update table
591
592	////////////////////////////////////////////////////
593	// Registers controlled by the IXR_RSP fsm
594	////////////////////////////////////////////////////
595
596	sc_signal<int> r_ixr_rsp_fsm; // FSM state
597	sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index
598	sc_signal<size_t> r_ixr_rsp_cpt; // word counter
599
600	// Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM)
601	sc_signal<bool> *r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready
602
603	////////////////////////////////////////////////////
604	// Registers controlled by the XRAM_RSP fsm
605	////////////////////////////////////////////////////
606
607	sc_signal<int> r_xram_rsp_fsm; // FSM state
608	sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index
609	TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer
610	sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate
611	sc_signal<bool> r_xram_rsp_victim_is_cnt; // victim line inst bit
612	sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit
613	sc_signal<size_t> r_xram_rsp_victim_way; // victim line way
614	sc_signal<size_t> r_xram_rsp_victim_set; // victim line set
615	sc_signal<addr_t> r_xram_rsp_victim_nline; // victim line index
616	sc_signal<copy_t> r_xram_rsp_victim_copy; // victim line first copy
617	sc_signal<bool> r_xram_rsp_victim_copy_inst; // victim line type of first copy
618	sc_signal<size_t> r_xram_rsp_victim_count; // victim line number of copies
619	sc_signal<size_t> r_xram_rsp_victim_ptr; // victim line pointer to the heap
620	sc_signal<data_t> *r_xram_rsp_victim_data; // victim line data
621	sc_signal<size_t> r_xram_rsp_upt_index; // UPT entry index
622	sc_signal<size_t> r_xram_rsp_next_ptr; // Next pointer to the heap
623
624	// Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache)
625	sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request
626	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid
627	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid
628	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid
629	sc_signal<data_t> *r_xram_rsp_to_tgt_rsp_data; // data (one cache line)
630	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_word; // first word index
631	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length;// length of the response
632
633	// Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches)
634	sc_signal<bool> r_xram_rsp_to_init_cmd_multi_req; // Valid request
635	sc_signal<bool> r_xram_rsp_to_init_cmd_brdcast_req; // Broadcast request
636	sc_signal<addr_t> r_xram_rsp_to_init_cmd_nline; // cache line index;
637	sc_signal<size_t> r_xram_rsp_to_init_cmd_trdid; // index of UPT entry
638	GenericFifo<bool> m_xram_rsp_to_init_cmd_inst_fifo; // fifo for the L1 type
639	GenericFifo<size_t> m_xram_rsp_to_init_cmd_srcid_fifo; // fifo for srcids
640
641	// Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
642	sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request
643	sc_signal<addr_t> r_xram_rsp_to_ixr_cmd_nline; // cache line index
644	sc_signal<data_t> *r_xram_rsp_to_ixr_cmd_data; // cache line data
645	sc_signal<size_t> r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table
646
647	////////////////////////////////////////////////////
648	// Registers controlled by the IXR_CMD fsm
649	////////////////////////////////////////////////////
650
651	sc_signal<int> r_ixr_cmd_fsm;
652	sc_signal<size_t> r_ixr_cmd_cpt;
653
654	////////////////////////////////////////////////////
655	// Registers controlled by TGT_RSP fsm
656	////////////////////////////////////////////////////
657
658	sc_signal<int> r_tgt_rsp_fsm;
659	sc_signal<size_t> r_tgt_rsp_cpt;
660
661	////////////////////////////////////////////////////
662	// Registers controlled by INIT_CMD fsm
663	////////////////////////////////////////////////////
664
665	sc_signal<int> r_init_cmd_fsm;
666	sc_signal<size_t> r_init_cmd_cpt;
667	sc_signal<bool> r_init_cmd_inst;
668
669	////////////////////////////////////////////////////
670	// Registers controlled by ALLOC_DIR fsm
671	////////////////////////////////////////////////////
672
673	sc_signal<int> r_alloc_dir_fsm;
674
675	////////////////////////////////////////////////////
676	// Registers controlled by ALLOC_TRT fsm
677	////////////////////////////////////////////////////
678
679	sc_signal<int> r_alloc_trt_fsm;
680
681	////////////////////////////////////////////////////
682	// Registers controlled by ALLOC_UPT fsm
683	////////////////////////////////////////////////////
684
685	sc_signal<int> r_alloc_upt_fsm;
686
687	////////////////////////////////////////////////////
688	// Registers controlled by ALLOC_HEAP fsm
689	////////////////////////////////////////////////////
690
691	sc_signal<int> r_alloc_heap_fsm;
692
693	}; // end class VciMemCacheV4
694
695	}}
696
697	#endif
698
699	// Local Variables:
700	// tab-width: 4
701	// c-basic-offset: 4
702	// c-file-offsets:((innamespace . 0)(inline-open . 0))
703	// indent-tabs-mode: nil
704	// End:
705
706	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
707

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