Context Navigation

vci_mem_cache_v4.h @ 245

Last change on this file since 245 was 245, checked in by alain, 12 years ago
ntroducing a segmentation violation checking
Property svn:eol-style set to `native` Property svn:keywords set to `"Author Date Id Rev URL Revision"` Property svn:mime-type set to `text/plain`
File size: 33.3 KB

Line
1	/* -- c++ --
2	* File : vci_mem_cache_v4.h
3	* Date : 26/10/2008
4	* Copyright : UPMC / LIP6
5	* Authors : Alain Greiner / Eric Guthmuller
6	*
7	* SOCLIB_LGPL_HEADER_BEGIN
8	*
9	* This file is part of SoCLib, GNU LGPLv2.1.
10	*
11	* SoCLib is free software; you can redistribute it and/or modify it
12	* under the terms of the GNU Lesser General Public License as published
13	* by the Free Software Foundation; version 2.1 of the License.
14	*
15	* SoCLib is distributed in the hope that it will be useful, but
16	* WITHOUT ANY WARRANTY; without even the implied warranty of
17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18	* Lesser General Public License for more details.
19	*
20	* You should have received a copy of the GNU Lesser General Public
21	* License along with SoCLib; if not, write to the Free Software
22	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23	* 02110-1301 USA
24	*
25	* SOCLIB_LGPL_HEADER_END
26	*
27	* Maintainers: alain eric.guthmuller@polytechnique.edu
28	*/
29	/*
30	*
31	* Modifications done by Christophe Choichillon on the 7/04/2009:
32	* - Adding new states in the CLEANUP FSM : CLEANUP_UPT_LOCK and CLEANUP_UPT_WRITE
33	* - Adding a new VCI target port for the CLEANUP network
34	* - Adding new state in the ALLOC_UPT_FSM : ALLOC_UPT_CLEANUP
35	*
36	* Modifications to do :
37	* - Adding new variables used by the CLEANUP FSM
38	*
39	*/
40
41	#ifndef SOCLIB_CABA_MEM_CACHE_V4_H
42	#define SOCLIB_CABA_MEM_CACHE_V4_H
43
44	#include <inttypes.h>
45	#include <systemc>
46	#include <list>
47	#include <cassert>
48	#include "arithmetics.h"
49	#include "alloc_elems.h"
50	#include "caba_base_module.h"
51	#include "vci_target.h"
52	#include "vci_initiator.h"
53	#include "generic_fifo.h"
54	#include "mapping_table.h"
55	#include "int_tab.h"
56	#include "mem_cache_directory_v4.h"
57	#include "xram_transaction_v4.h"
58	#include "update_tab_v4.h"
59
60	#define TRANSACTION_TAB_LINES 4 // Number of lines in the transaction tab
61	#define UPDATE_TAB_LINES 4 // Number of lines in the update tab
62
63	namespace soclib { namespace caba {
64	using namespace sc_core;
65
66	template<typename vci_param>
67	class VciMemCacheV4
68	: public soclib::caba::BaseModule
69	{
70	typedef sc_dt::sc_uint<40> addr_t;
71	typedef typename vci_param::fast_addr_t vci_addr_t;
72	typedef uint32_t data_t;
73	typedef uint32_t tag_t;
74	typedef uint32_t size_t;
75	typedef uint32_t be_t;
76	typedef uint32_t copy_t;
77
78	/* States of the TGT_CMD fsm */
79	enum tgt_cmd_fsm_state_e{
80	TGT_CMD_IDLE,
81	TGT_CMD_READ,
82	TGT_CMD_WRITE,
83	TGT_CMD_ATOMIC,
84	};
85
86	/* States of the TGT_RSP fsm */
87	enum tgt_rsp_fsm_state_e{
88	TGT_RSP_READ_IDLE,
89	TGT_RSP_WRITE_IDLE,
90	TGT_RSP_SC_IDLE,
91	TGT_RSP_XRAM_IDLE,
92	TGT_RSP_INIT_IDLE,
93	TGT_RSP_CLEANUP_IDLE,
94	TGT_RSP_READ,
95	TGT_RSP_WRITE,
96	TGT_RSP_SC,
97	TGT_RSP_XRAM,
98	TGT_RSP_INIT,
99	TGT_RSP_CLEANUP,
100	};
101
102	/* States of the INIT_CMD fsm */
103	enum init_cmd_fsm_state_e{
104	INIT_CMD_INVAL_IDLE,
105	INIT_CMD_INVAL_NLINE,
106	INIT_CMD_XRAM_BRDCAST,
107	INIT_CMD_UPDT_IDLE,
108	INIT_CMD_WRITE_BRDCAST,
109	INIT_CMD_UPDT_NLINE,
110	INIT_CMD_UPDT_INDEX,
111	INIT_CMD_UPDT_DATA,
112	INIT_CMD_SC_UPDT_IDLE,
113	INIT_CMD_SC_BRDCAST,
114	INIT_CMD_SC_UPDT_NLINE,
115	INIT_CMD_SC_UPDT_INDEX,
116	INIT_CMD_SC_UPDT_DATA,
117	INIT_CMD_SC_UPDT_DATA_HIGH,
118	};
119
120	/* States of the INIT_RSP fsm */
121	enum init_rsp_fsm_state_e{
122	INIT_RSP_IDLE,
123	INIT_RSP_UPT_LOCK,
124	INIT_RSP_UPT_CLEAR,
125	INIT_RSP_END,
126	};
127
128	/* States of the READ fsm */
129	enum read_fsm_state_e{
130	READ_IDLE,
131	READ_DIR_LOCK,
132	READ_DIR_HIT,
133	READ_HEAP_LOCK,
134	READ_HEAP_WRITE,
135	READ_HEAP_ERASE,
136	READ_HEAP_LAST,
137	READ_RSP,
138	READ_TRT_LOCK,
139	READ_TRT_SET,
140	READ_TRT_REQ,
141	};
142
143	/* States of the WRITE fsm */
144	enum write_fsm_state_e{
145	WRITE_IDLE,
146	WRITE_NEXT,
147	WRITE_DIR_LOCK,
148	WRITE_DIR_READ,
149	WRITE_DIR_HIT,
150	WRITE_UPT_LOCK,
151	WRITE_UPT_HEAP_LOCK,
152	WRITE_UPT_REQ,
153	WRITE_UPT_NEXT,
154	WRITE_UPT_DEC,
155	WRITE_RSP,
156	WRITE_MISS_TRT_LOCK,
157	WRITE_MISS_TRT_DATA,
158	WRITE_MISS_TRT_SET,
159	WRITE_MISS_XRAM_REQ,
160	WRITE_BC_TRT_LOCK,
161	WRITE_BC_UPT_LOCK,
162	WRITE_BC_DIR_INVAL,
163	WRITE_BC_CC_SEND,
164	WRITE_BC_XRAM_REQ,
165	WRITE_WAIT,
166	};
167
168	/* States of the IXR_RSP fsm */
169	enum ixr_rsp_fsm_state_e{
170	IXR_RSP_IDLE,
171	IXR_RSP_ACK,
172	IXR_RSP_TRT_ERASE,
173	IXR_RSP_TRT_READ,
174	};
175
176	/* States of the XRAM_RSP fsm */
177	enum xram_rsp_fsm_state_e{
178	XRAM_RSP_IDLE,
179	XRAM_RSP_TRT_COPY,
180	XRAM_RSP_TRT_DIRTY,
181	XRAM_RSP_DIR_LOCK,
182	XRAM_RSP_DIR_UPDT,
183	XRAM_RSP_DIR_RSP,
184	XRAM_RSP_INVAL_LOCK,
185	XRAM_RSP_INVAL_WAIT,
186	XRAM_RSP_INVAL,
187	XRAM_RSP_WRITE_DIRTY,
188	XRAM_RSP_HEAP_ERASE,
189	XRAM_RSP_HEAP_LAST,
190	XRAM_RSP_ERROR_ERASE,
191	XRAM_RSP_ERROR_RSP,
192	};
193
194	/* States of the IXR_CMD fsm */
195	enum ixr_cmd_fsm_state_e{
196	IXR_CMD_READ_IDLE,
197	IXR_CMD_WRITE_IDLE,
198	IXR_CMD_SC_IDLE,
199	IXR_CMD_XRAM_IDLE,
200	IXR_CMD_READ_NLINE,
201	IXR_CMD_WRITE_NLINE,
202	IXR_CMD_SC_NLINE,
203	IXR_CMD_XRAM_DATA,
204	};
205
206	/* States of the SC fsm */
207	enum sc_fsm_state_e{
208	SC_IDLE,
209	SC_DIR_LOCK,
210	SC_DIR_HIT_READ,
211	SC_DIR_HIT_WRITE,
212	SC_UPT_LOCK,
213	SC_UPT_HEAP_LOCK,
214	SC_UPT_REQ,
215	SC_UPT_NEXT,
216	SC_BC_TRT_LOCK,
217	SC_BC_UPT_LOCK,
218	SC_BC_DIR_INVAL,
219	SC_BC_CC_SEND,
220	SC_BC_XRAM_REQ,
221	SC_RSP_FAIL,
222	SC_RSP_SUCCESS,
223	SC_MISS_TRT_LOCK,
224	SC_MISS_TRT_SET,
225	SC_MISS_XRAM_REQ,
226	SC_WAIT,
227	};
228
229	/* States of the CLEANUP fsm */
230	enum cleanup_fsm_state_e{
231	CLEANUP_IDLE,
232	CLEANUP_DIR_LOCK,
233	CLEANUP_DIR_WRITE,
234	CLEANUP_HEAP_LOCK,
235	CLEANUP_HEAP_SEARCH,
236	CLEANUP_HEAP_CLEAN,
237	CLEANUP_HEAP_FREE,
238	CLEANUP_UPT_LOCK,
239	CLEANUP_UPT_WRITE,
240	CLEANUP_WRITE_RSP,
241	CLEANUP_RSP,
242	};
243
244	/* States of the ALLOC_DIR fsm */
245	enum alloc_dir_fsm_state_e{
246	ALLOC_DIR_READ,
247	ALLOC_DIR_WRITE,
248	ALLOC_DIR_SC,
249	ALLOC_DIR_CLEANUP,
250	ALLOC_DIR_XRAM_RSP,
251	};
252
253	/* States of the ALLOC_TRT fsm */
254	enum alloc_trt_fsm_state_e{
255	ALLOC_TRT_READ,
256	ALLOC_TRT_WRITE,
257	ALLOC_TRT_SC,
258	ALLOC_TRT_XRAM_RSP,
259	ALLOC_TRT_IXR_RSP,
260	};
261
262	/* States of the ALLOC_UPT fsm */
263	enum alloc_upt_fsm_state_e{
264	ALLOC_UPT_WRITE,
265	ALLOC_UPT_XRAM_RSP,
266	ALLOC_UPT_INIT_RSP,
267	ALLOC_UPT_CLEANUP,
268	ALLOC_UPT_SC,
269	};
270
271	/* States of the ALLOC_HEAP fsm */
272	enum alloc_heap_fsm_state_e{
273	ALLOC_HEAP_READ,
274	ALLOC_HEAP_WRITE,
275	ALLOC_HEAP_SC,
276	ALLOC_HEAP_CLEANUP,
277	ALLOC_HEAP_XRAM_RSP,
278	};
279
280	// debug variables (for each FSM)
281	size_t m_debug_start_cycle;
282	bool m_debug_ok;
283	bool m_debug_global;
284	bool m_debug_tgt_cmd_fsm;
285	bool m_debug_tgt_rsp_fsm;
286	bool m_debug_init_cmd_fsm;
287	bool m_debug_init_rsp_fsm;
288	bool m_debug_read_fsm;
289	bool m_debug_write_fsm;
290	bool m_debug_sc_fsm;
291	bool m_debug_cleanup_fsm;
292	bool m_debug_ixr_cmd_fsm;
293	bool m_debug_ixr_rsp_fsm;
294	bool m_debug_xram_rsp_fsm;
295	bool m_debug_previous_hit;
296	size_t m_debug_previous_count;
297
298	bool m_monitor_ok;
299	vci_addr_t m_monitor_base;
300	vci_addr_t m_monitor_length;
301
302	// instrumentation counters
303	uint32_t m_cpt_cycles; // Counter of cycles
304	uint32_t m_cpt_read; // Number of READ transactions
305	uint32_t m_cpt_read_miss; // Number of MISS READ
306	uint32_t m_cpt_write; // Number of WRITE transactions
307	uint32_t m_cpt_write_miss; // Number of MISS WRITE
308	uint32_t m_cpt_write_cells; // Cumulated length for WRITE transactions
309	uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions
310	uint32_t m_cpt_update; // Number of UPDATE transactions
311	uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt
312	uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt
313	uint32_t m_cpt_update_mult; // Number of targets for UPDATE
314	uint32_t m_cpt_inval; // Number of INVAL transactions
315	uint32_t m_cpt_inval_mult; // Number of targets for INVAL
316	uint32_t m_cpt_inval_brdcast; // Number of BROADCAST INVAL
317	uint32_t m_cpt_cleanup; // Number of CLEANUP transactions
318	uint32_t m_cpt_ll; // Number of LL transactions
319	uint32_t m_cpt_sc; // Number of SC transactions
320
321	size_t m_prev_count;
322
323	protected:
324
325	SC_HAS_PROCESS(VciMemCacheV4);
326
327	public:
328	sc_in<bool> p_clk;
329	sc_in<bool> p_resetn;
330	soclib::caba::VciTarget<vci_param> p_vci_tgt;
331	soclib::caba::VciTarget<vci_param> p_vci_tgt_cleanup;
332	soclib::caba::VciInitiator<vci_param> p_vci_ini;
333	soclib::caba::VciInitiator<vci_param> p_vci_ixr;
334
335	VciMemCacheV4(
336	sc_module_name name, // Instance Name
337	const soclib::common::MappingTable &mtp, // Mapping table for primary requets
338	const soclib::common::MappingTable &mtc, // Mapping table for coherence requets
339	const soclib::common::MappingTable &mtx, // Mapping table for XRAM
340	const soclib::common::IntTab &vci_ixr_index, // VCI port to XRAM (initiator)
341	const soclib::common::IntTab &vci_ini_index, // VCI port to PROC (initiator)
342	const soclib::common::IntTab &vci_tgt_index, // VCI port to PROC (target)
343	const soclib::common::IntTab &vci_tgt_index_cleanup,// VCI port to PROC (target) for cleanup
344	size_t nways, // Number of ways per set
345	size_t nsets, // Number of sets
346	size_t nwords, // Number of words per line
347	size_t heap_size=1024, // Size of the heap
348	size_t transaction_tab_lines=TRANSACTION_TAB_LINES, // Size of the TRT
349	size_t update_tab_lines=UPDATE_TAB_LINES, // Size of the UPT
350	size_t debug_start_cycle=0,
351	bool debug_ok=false);
352
353	~VciMemCacheV4();
354
355	void print_stats();
356	void print_trace();
357	void copies_monitor(vci_addr_t addr);
358	void start_monitor(vci_addr_t addr, vci_addr_t length);
359	void stop_monitor();
360
361	private:
362
363	void transition();
364	void genMoore();
365	void check_monitor( const char *buf, vci_addr_t addr, data_t data);
366
367	// Component attributes
368	const size_t m_initiators; // Number of initiators
369	const size_t m_heap_size; // Size of the heap
370	const size_t m_ways; // Number of ways in a set
371	const size_t m_sets; // Number of cache sets
372	const size_t m_words; // Number of words in a line
373	const size_t m_srcid_ixr; // Srcid for requests to XRAM
374	const size_t m_srcid_ini; // Srcid for requests to processors
375	std::list<soclib::common::Segment> m_seglist; // memory cached into the cache
376	std::list<soclib::common::Segment> m_cseglist; // coherence segment for the cache
377	vci_addr_t *m_coherence_table; // address(srcid)
378	uint32_t m_transaction_tab_lines;
379	TransactionTab m_transaction_tab; // xram transaction table
380	uint32_t m_update_tab_lines;
381	UpdateTab m_update_tab; // pending update & invalidate
382	CacheDirectory m_cache_directory; // data cache directory
383	HeapDirectory m_heap; // heap for copies
384
385	data_t ***m_cache_data; // data array[set][way][word]
386
387	// adress masks
388	const soclib::common::AddressMaskingTable<vci_addr_t> m_x;
389	const soclib::common::AddressMaskingTable<vci_addr_t> m_y;
390	const soclib::common::AddressMaskingTable<vci_addr_t> m_z;
391	const soclib::common::AddressMaskingTable<vci_addr_t> m_nline;
392
393	// broadcast address
394	vci_addr_t m_broadcast_address;
395
396	//////////////////////////////////////////////////
397	// Others registers
398	//////////////////////////////////////////////////
399	sc_signal<size_t> r_copies_limit; // Limit of the number of copies for one line
400	sc_signal<size_t> xxx_count;
401
402	//////////////////////////////////////////////////
403	// Registers controlled by the TGT_CMD fsm
404	//////////////////////////////////////////////////
405
406	// Fifo between TGT_CMD fsm and READ fsm
407	GenericFifo<uint64_t> m_cmd_read_addr_fifo;
408	GenericFifo<size_t> m_cmd_read_length_fifo;
409	GenericFifo<size_t> m_cmd_read_srcid_fifo;
410	GenericFifo<size_t> m_cmd_read_trdid_fifo;
411	GenericFifo<size_t> m_cmd_read_pktid_fifo;
412
413	// Fifo between TGT_CMD fsm and WRITE fsm
414	GenericFifo<uint64_t> m_cmd_write_addr_fifo;
415	GenericFifo<bool> m_cmd_write_eop_fifo;
416	GenericFifo<size_t> m_cmd_write_srcid_fifo;
417	GenericFifo<size_t> m_cmd_write_trdid_fifo;
418	GenericFifo<size_t> m_cmd_write_pktid_fifo;
419	GenericFifo<data_t> m_cmd_write_data_fifo;
420	GenericFifo<be_t> m_cmd_write_be_fifo;
421
422	// Fifo between TGT_CMD fsm and SC fsm
423	GenericFifo<uint64_t> m_cmd_sc_addr_fifo;
424	GenericFifo<bool> m_cmd_sc_eop_fifo;
425	GenericFifo<size_t> m_cmd_sc_srcid_fifo;
426	GenericFifo<size_t> m_cmd_sc_trdid_fifo;
427	GenericFifo<size_t> m_cmd_sc_pktid_fifo;
428	GenericFifo<data_t> m_cmd_sc_wdata_fifo;
429
430	sc_signal<int> r_tgt_cmd_fsm;
431
432	size_t m_nseg;
433	size_t m_ncseg;
434	soclib::common::Segment **m_seg;
435	soclib::common::Segment **m_cseg;
436
437	///////////////////////////////////////////////////////
438	// Registers controlled by the READ fsm
439	///////////////////////////////////////////////////////
440
441	sc_signal<int> r_read_fsm; // FSM state
442	sc_signal<size_t> r_read_copy; // Srcid of the first copy
443	sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy
444	sc_signal<bool> r_read_copy_inst; // Type of the first copy
445	sc_signal<tag_t> r_read_tag; // cache line tag (in directory)
446	sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory)
447	sc_signal<bool> r_read_lock; // lock bit (in directory)
448	sc_signal<bool> r_read_dirty; // dirty bit (in directory)
449	sc_signal<size_t> r_read_count; // number of copies
450	sc_signal<size_t> r_read_ptr; // pointer to the heap
451	sc_signal<data_t> *r_read_data; // data (one cache line)
452	sc_signal<size_t> r_read_way; // associative way (in cache)
453	sc_signal<size_t> r_read_trt_index; // Transaction Table index
454	sc_signal<size_t> r_read_next_ptr; // Next entry to point to
455	sc_signal<bool> r_read_last_free; // Last free entry
456
457	// Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
458	sc_signal<bool> r_read_to_ixr_cmd_req; // valid request
459	sc_signal<addr_t> r_read_to_ixr_cmd_nline; // cache line index
460	sc_signal<size_t> r_read_to_ixr_cmd_trdid; // index in Transaction Table
461
462	// Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
463	sc_signal<bool> r_read_to_tgt_rsp_req; // valid request
464	sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid
465	sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid
466	sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid
467	sc_signal<data_t> *r_read_to_tgt_rsp_data; // data (one cache line)
468	sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response
469	sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response
470
471	///////////////////////////////////////////////////////////////
472	// Registers controlled by the WRITE fsm
473	///////////////////////////////////////////////////////////////
474
475	sc_signal<int> r_write_fsm; // FSM state
476	sc_signal<addr_t> r_write_address; // first word address
477	sc_signal<size_t> r_write_word_index; // first word index in line
478	sc_signal<size_t> r_write_word_count; // number of words in line
479	sc_signal<size_t> r_write_srcid; // transaction srcid
480	sc_signal<size_t> r_write_trdid; // transaction trdid
481	sc_signal<size_t> r_write_pktid; // transaction pktid
482	sc_signal<data_t> *r_write_data; // data (one cache line)
483	sc_signal<be_t> *r_write_be; // one byte enable per word
484	sc_signal<bool> r_write_byte; // (BE != 0X0) and (BE != 0xF)
485	sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory)
486	sc_signal<bool> r_write_lock; // lock bit (in directory)
487	sc_signal<tag_t> r_write_tag; // cache line tag (in directory)
488	sc_signal<size_t> r_write_copy; // first owner of the line
489	sc_signal<size_t> r_write_copy_cache; // first owner of the line
490	sc_signal<bool> r_write_copy_inst; // is this owner a ICache ?
491	sc_signal<size_t> r_write_count; // number of copies
492	sc_signal<size_t> r_write_ptr; // pointer to the heap
493	sc_signal<size_t> r_write_next_ptr; // next pointer to the heap
494	sc_signal<bool> r_write_to_dec; // need to decrement update counter
495	sc_signal<size_t> r_write_way; // way of the line
496	sc_signal<size_t> r_write_trt_index; // index in Transaction Table
497	sc_signal<size_t> r_write_upt_index; // index in Update Table
498
499	// Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
500	sc_signal<bool> r_write_to_tgt_rsp_req; // valid request
501	sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid
502	sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid
503	sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid
504
505	// Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
506	sc_signal<bool> r_write_to_ixr_cmd_req; // valid request
507	sc_signal<bool> r_write_to_ixr_cmd_write; // write request
508	sc_signal<addr_t> r_write_to_ixr_cmd_nline; // cache line index
509	sc_signal<data_t> *r_write_to_ixr_cmd_data; // cache line data
510	sc_signal<size_t> r_write_to_ixr_cmd_trdid; // index in Transaction Table
511
512	// Buffer between WRITE fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
513	sc_signal<bool> r_write_to_init_cmd_multi_req; // valid multicast request
514	sc_signal<bool> r_write_to_init_cmd_brdcast_req; // valid brdcast request
515	sc_signal<addr_t> r_write_to_init_cmd_nline; // cache line index
516	sc_signal<size_t> r_write_to_init_cmd_trdid; // index in Update Table
517	sc_signal<data_t> *r_write_to_init_cmd_data; // data (one cache line)
518	sc_signal<be_t> *r_write_to_init_cmd_be; // word enable
519	sc_signal<size_t> r_write_to_init_cmd_count; // number of words in line
520	sc_signal<size_t> r_write_to_init_cmd_index; // index of first word in line
521	GenericFifo<bool> m_write_to_init_cmd_inst_fifo; // fifo for the L1 type
522	GenericFifo<size_t> m_write_to_init_cmd_srcid_fifo; // fifo for srcids
523	GenericFifo<size_t> m_write_to_init_cmd_cache_id_fifo; // fifo for srcids
524
525	// Buffer between WRITE fsm and INIT_RSP fsm (Decrement UPT entry)
526	sc_signal<bool> r_write_to_init_rsp_req; // valid request
527	sc_signal<size_t> r_write_to_init_rsp_upt_index; // index in update table
528
529	/////////////////////////////////////////////////////////
530	// Registers controlled by INIT_RSP fsm
531	//////////////////////////////////////////////////////////
532
533	sc_signal<int> r_init_rsp_fsm; // FSM state
534	sc_signal<size_t> r_init_rsp_upt_index; // index in the Update Table
535	sc_signal<size_t> r_init_rsp_srcid; // pending write srcid
536	sc_signal<size_t> r_init_rsp_trdid; // pending write trdid
537	sc_signal<size_t> r_init_rsp_pktid; // pending write pktid
538	sc_signal<addr_t> r_init_rsp_nline; // pending write nline
539
540	// Buffer between INIT_RSP fsm and TGT_RSP fsm (complete write/update transaction)
541	sc_signal<bool> r_init_rsp_to_tgt_rsp_req; // valid request
542	sc_signal<size_t> r_init_rsp_to_tgt_rsp_srcid; // Transaction srcid
543	sc_signal<size_t> r_init_rsp_to_tgt_rsp_trdid; // Transaction trdid
544	sc_signal<size_t> r_init_rsp_to_tgt_rsp_pktid; // Transaction pktid
545
546	///////////////////////////////////////////////////////
547	// Registers controlled by CLEANUP fsm
548	///////////////////////////////////////////////////////
549
550	sc_signal<int> r_cleanup_fsm; // FSM state
551	sc_signal<size_t> r_cleanup_srcid; // transaction srcid
552	sc_signal<size_t> r_cleanup_trdid; // transaction trdid
553	sc_signal<size_t> r_cleanup_pktid; // transaction pktid
554	sc_signal<addr_t> r_cleanup_nline; // cache line index
555
556	sc_signal<copy_t> r_cleanup_copy; // first copy
557	sc_signal<copy_t> r_cleanup_copy_cache; // first copy
558	sc_signal<size_t> r_cleanup_copy_inst; // type of the first copy
559	sc_signal<copy_t> r_cleanup_count; // number of copies
560	sc_signal<size_t> r_cleanup_ptr; // pointer to the heap
561	sc_signal<size_t> r_cleanup_prev_ptr; // previous pointer to the heap
562	sc_signal<size_t> r_cleanup_prev_srcid; // srcid of previous heap entry
563	sc_signal<size_t> r_cleanup_prev_cache_id; // srcid of previous heap entry
564	sc_signal<bool> r_cleanup_prev_inst; // inst bit of previous heap entry
565	sc_signal<size_t> r_cleanup_next_ptr; // next pointer to the heap
566	sc_signal<tag_t> r_cleanup_tag; // cache line tag (in directory)
567	sc_signal<bool> r_cleanup_is_cnt; // inst bit (in directory)
568	sc_signal<bool> r_cleanup_lock; // lock bit (in directory)
569	sc_signal<bool> r_cleanup_dirty; // dirty bit (in directory)
570	sc_signal<size_t> r_cleanup_way; // associative way (in cache)
571
572	sc_signal<size_t> r_cleanup_write_srcid; // srcid of write response
573	sc_signal<size_t> r_cleanup_write_trdid; // trdid of write rsp
574	sc_signal<size_t> r_cleanup_write_pktid; // pktid of write rsp
575	sc_signal<bool> r_cleanup_need_rsp; // needs a write rsp
576
577	sc_signal<size_t> r_cleanup_index; // index of the INVAL line (in the UPT)
578
579	// Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
580	sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request
581	sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid
582	sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid
583	sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid
584
585	///////////////////////////////////////////////////////
586	// Registers controlled by SC fsm
587	///////////////////////////////////////////////////////
588
589	sc_signal<int> r_sc_fsm; // FSM state
590	sc_signal<data_t> r_sc_wdata; // write data word
591	sc_signal<data_t> *r_sc_rdata; // read data word
592	sc_signal<uint32_t> r_sc_lfsr; // lfsr for random introducing
593	sc_signal<size_t> r_sc_cpt; // size of command
594	sc_signal<copy_t> r_sc_copy; // Srcid of the first copy
595	sc_signal<copy_t> r_sc_copy_cache; // Srcid of the first copy
596	sc_signal<bool> r_sc_copy_inst; // Type of the first copy
597	sc_signal<size_t> r_sc_count; // number of copies
598	sc_signal<size_t> r_sc_ptr; // pointer to the heap
599	sc_signal<size_t> r_sc_next_ptr; // next pointer to the heap
600	sc_signal<bool> r_sc_is_cnt; // is_cnt bit (in directory)
601	sc_signal<bool> r_sc_dirty; // dirty bit (in directory)
602	sc_signal<size_t> r_sc_way; // way in directory
603	sc_signal<size_t> r_sc_set; // set in directory
604	sc_signal<data_t> r_sc_tag; // cache line tag (in directory)
605	sc_signal<size_t> r_sc_trt_index; // Transaction Table index
606	sc_signal<size_t> r_sc_upt_index; // Update Table index
607
608	// Buffer between SC fsm and INIT_CMD fsm (XRAM read)
609	sc_signal<bool> r_sc_to_ixr_cmd_req; // valid request
610	sc_signal<addr_t> r_sc_to_ixr_cmd_nline; // cache line index
611	sc_signal<size_t> r_sc_to_ixr_cmd_trdid; // index in Transaction Table
612	sc_signal<bool> r_sc_to_ixr_cmd_write; // write request
613	sc_signal<data_t> *r_sc_to_ixr_cmd_data; // cache line data
614
615
616	// Buffer between SC fsm and TGT_RSP fsm
617	sc_signal<bool> r_sc_to_tgt_rsp_req; // valid request
618	sc_signal<data_t> r_sc_to_tgt_rsp_data; // read data word
619	sc_signal<size_t> r_sc_to_tgt_rsp_srcid; // Transaction srcid
620	sc_signal<size_t> r_sc_to_tgt_rsp_trdid; // Transaction trdid
621	sc_signal<size_t> r_sc_to_tgt_rsp_pktid; // Transaction pktid
622
623	// Buffer between SC fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
624	sc_signal<bool> r_sc_to_init_cmd_multi_req; // valid request
625	sc_signal<bool> r_sc_to_init_cmd_brdcast_req; // brdcast request
626	sc_signal<addr_t> r_sc_to_init_cmd_nline; // cache line index
627	sc_signal<size_t> r_sc_to_init_cmd_trdid; // index in Update Table
628	sc_signal<data_t> r_sc_to_init_cmd_wdata; // data (one word)
629	sc_signal<bool> r_sc_to_init_cmd_is_long; // it is a 64 bits SC
630	sc_signal<data_t> r_sc_to_init_cmd_wdata_high; // data high (one word)
631	sc_signal<size_t> r_sc_to_init_cmd_index; // index of the word in line
632	GenericFifo<bool> m_sc_to_init_cmd_inst_fifo; // fifo for the L1 type
633	GenericFifo<size_t> m_sc_to_init_cmd_srcid_fifo; // fifo for srcids
634	GenericFifo<size_t> m_sc_to_init_cmd_cache_id_fifo; // fifo for srcids
635
636	// Buffer between SC fsm and INIT_RSP fsm (Decrement UPT entry)
637	sc_signal<bool> r_sc_to_init_rsp_req; // valid request
638	sc_signal<size_t> r_sc_to_init_rsp_upt_index; // index in update table
639
640	////////////////////////////////////////////////////
641	// Registers controlled by the IXR_RSP fsm
642	////////////////////////////////////////////////////
643
644	sc_signal<int> r_ixr_rsp_fsm; // FSM state
645	sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index
646	sc_signal<size_t> r_ixr_rsp_cpt; // word counter
647
648	// Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM)
649	sc_signal<bool> *r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready
650
651	////////////////////////////////////////////////////
652	// Registers controlled by the XRAM_RSP fsm
653	////////////////////////////////////////////////////
654
655	sc_signal<int> r_xram_rsp_fsm; // FSM state
656	sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index
657	TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer
658	sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate
659	sc_signal<bool> r_xram_rsp_victim_is_cnt; // victim line inst bit
660	sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit
661	sc_signal<size_t> r_xram_rsp_victim_way; // victim line way
662	sc_signal<size_t> r_xram_rsp_victim_set; // victim line set
663	sc_signal<addr_t> r_xram_rsp_victim_nline; // victim line index
664	sc_signal<copy_t> r_xram_rsp_victim_copy; // victim line first copy
665	sc_signal<copy_t> r_xram_rsp_victim_copy_cache;// victim line first copy
666	sc_signal<bool> r_xram_rsp_victim_copy_inst; // victim line type of first copy
667	sc_signal<size_t> r_xram_rsp_victim_count; // victim line number of copies
668	sc_signal<size_t> r_xram_rsp_victim_ptr; // victim line pointer to the heap
669	sc_signal<data_t> *r_xram_rsp_victim_data; // victim line data
670	sc_signal<size_t> r_xram_rsp_upt_index; // UPT entry index
671	sc_signal<size_t> r_xram_rsp_next_ptr; // Next pointer to the heap
672
673	// Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache)
674	sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request
675	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid
676	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid
677	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid
678	sc_signal<data_t> *r_xram_rsp_to_tgt_rsp_data; // data (one cache line)
679	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_word; // first word index
680	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length;// length of the response
681	sc_signal<bool> r_xram_rsp_to_tgt_rsp_rerror;// send error to requester
682
683	// Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches)
684	sc_signal<bool> r_xram_rsp_to_init_cmd_multi_req; // Valid request
685	sc_signal<bool> r_xram_rsp_to_init_cmd_brdcast_req; // Broadcast request
686	sc_signal<addr_t> r_xram_rsp_to_init_cmd_nline; // cache line index;
687	sc_signal<size_t> r_xram_rsp_to_init_cmd_trdid; // index of UPT entry
688	GenericFifo<bool> m_xram_rsp_to_init_cmd_inst_fifo; // fifo for the L1 type
689	GenericFifo<size_t> m_xram_rsp_to_init_cmd_srcid_fifo; // fifo for srcids
690	GenericFifo<size_t> m_xram_rsp_to_init_cmd_cache_id_fifo; // fifo for srcids
691
692	// Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
693	sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request
694	sc_signal<addr_t> r_xram_rsp_to_ixr_cmd_nline; // cache line index
695	sc_signal<data_t> *r_xram_rsp_to_ixr_cmd_data; // cache line data
696	sc_signal<size_t> r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table
697
698	////////////////////////////////////////////////////
699	// Registers controlled by the IXR_CMD fsm
700	////////////////////////////////////////////////////
701
702	sc_signal<int> r_ixr_cmd_fsm;
703	sc_signal<size_t> r_ixr_cmd_cpt;
704
705	////////////////////////////////////////////////////
706	// Registers controlled by TGT_RSP fsm
707	////////////////////////////////////////////////////
708
709	sc_signal<int> r_tgt_rsp_fsm;
710	sc_signal<size_t> r_tgt_rsp_cpt;
711
712	////////////////////////////////////////////////////
713	// Registers controlled by INIT_CMD fsm
714	////////////////////////////////////////////////////
715
716	sc_signal<int> r_init_cmd_fsm;
717	sc_signal<size_t> r_init_cmd_cpt;
718	sc_signal<bool> r_init_cmd_inst;
719
720	////////////////////////////////////////////////////
721	// Registers controlled by ALLOC_DIR fsm
722	////////////////////////////////////////////////////
723
724	sc_signal<int> r_alloc_dir_fsm;
725
726	////////////////////////////////////////////////////
727	// Registers controlled by ALLOC_TRT fsm
728	////////////////////////////////////////////////////
729
730	sc_signal<int> r_alloc_trt_fsm;
731
732	////////////////////////////////////////////////////
733	// Registers controlled by ALLOC_UPT fsm
734	////////////////////////////////////////////////////
735
736	sc_signal<int> r_alloc_upt_fsm;
737
738	////////////////////////////////////////////////////
739	// Registers controlled by ALLOC_HEAP fsm
740	////////////////////////////////////////////////////
741
742	sc_signal<int> r_alloc_heap_fsm;
743
744	}; // end class VciMemCacheV4
745
746	}}
747
748	#endif
749
750	// Local Variables:
751	// tab-width: 2
752	// c-basic-offset: 2
753	// c-file-offsets:((innamespace . 0)(inline-open . 0))
754	// indent-tabs-mode: nil
755	// End:
756
757	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
758

Note: See TracBrowser for help on using the repository browser.

Download in other formats:

Original Format