Context Navigation

vci_mem_cache_v4.h @ 273

Last change on this file since 273 was 273, checked in by cfuguet, 11 years ago

Modificating the VCI Memory Cache to align the VHDL and the SOCLIB models.
The primary modification consists to add a state DIR_REQ or HEAP_REQ, in all
FSMs using these two structures.

In these states a FSM take the lock of the DIRECTORY or HEAP, respectively,
and at the end of the cycle sends the READ request. Is in the next cycle,
when the response of the READ is obtained.

With this modifications, the behavior of a Synchonous RAM is emulated.

Property svn:eol-style set to native
Property svn:keywords set to "Author Date Id Rev URL Revision"
Property svn:mime-type set to text/plain

File size: 32.6 KB

Line
1	/* -- c++ --
2	* File : vci_mem_cache_v4.h
3	* Date : 26/10/2008
4	* Copyright : UPMC / LIP6
5	* Authors : Alain Greiner / Eric Guthmuller
6	*
7	* SOCLIB_LGPL_HEADER_BEGIN
8	*
9	* This file is part of SoCLib, GNU LGPLv2.1.
10	*
11	* SoCLib is free software; you can redistribute it and/or modify it
12	* under the terms of the GNU Lesser General Public License as published
13	* by the Free Software Foundation; version 2.1 of the License.
14	*
15	* SoCLib is distributed in the hope that it will be useful, but
16	* WITHOUT ANY WARRANTY; without even the implied warranty of
17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18	* Lesser General Public License for more details.
19	*
20	* You should have received a copy of the GNU Lesser General Public
21	* License along with SoCLib; if not, write to the Free Software
22	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23	* 02110-1301 USA
24	*
25	* SOCLIB_LGPL_HEADER_END
26	*
27	* Maintainers: alain eric.guthmuller@polytechnique.edu
28	* cesar.fuguet-tortolero@lip6.fr
29	*
30	* Modifications done by Christophe Choichillon on the 7/04/2009:
31	* - Adding new states in the CLEANUP FSM : CLEANUP_UPT_LOCK and CLEANUP_UPT_WRITE
32	* - Adding a new VCI target port for the CLEANUP network
33	* - Adding new state in the ALLOC_UPT_FSM : ALLOC_UPT_CLEANUP
34	*
35	* Modifications to do :
36	* - Adding new variables used by the CLEANUP FSM
37	*
38	*/
39
40	#ifndef SOCLIB_CABA_MEM_CACHE_V4_H
41	#define SOCLIB_CABA_MEM_CACHE_V4_H
42
43	#include <inttypes.h>
44	#include <systemc>
45	#include <list>
46	#include <cassert>
47	#include "arithmetics.h"
48	#include "alloc_elems.h"
49	#include "caba_base_module.h"
50	#include "vci_target.h"
51	#include "vci_initiator.h"
52	#include "generic_fifo.h"
53	#include "mapping_table.h"
54	#include "int_tab.h"
55	#include "mem_cache_directory_v4.h"
56	#include "xram_transaction_v4.h"
57	#include "update_tab_v4.h"
58
59	#define TRANSACTION_TAB_LINES 4 // Number of lines in the transaction tab
60	#define UPDATE_TAB_LINES 4 // Number of lines in the update tab
61
62	namespace soclib { namespace caba {
63	using namespace sc_core;
64
65	template<typename vci_param>
66	class VciMemCacheV4
67	: public soclib::caba::BaseModule
68	{
69	typedef sc_dt::sc_uint<40> addr_t;
70	typedef typename vci_param::fast_addr_t vci_addr_t;
71	typedef uint32_t data_t;
72	typedef uint32_t tag_t;
73	typedef uint32_t size_t;
74	typedef uint32_t be_t;
75	typedef uint32_t copy_t;
76
77	/* States of the TGT_CMD fsm */
78	enum tgt_cmd_fsm_state_e{
79	TGT_CMD_IDLE,
80	TGT_CMD_READ,
81	TGT_CMD_WRITE,
82	TGT_CMD_ATOMIC
83	};
84
85	/* States of the TGT_RSP fsm */
86	enum tgt_rsp_fsm_state_e{
87	TGT_RSP_READ_IDLE,
88	TGT_RSP_WRITE_IDLE,
89	TGT_RSP_SC_IDLE,
90	TGT_RSP_XRAM_IDLE,
91	TGT_RSP_INIT_IDLE,
92	TGT_RSP_CLEANUP_IDLE,
93	TGT_RSP_READ,
94	TGT_RSP_WRITE,
95	TGT_RSP_SC,
96	TGT_RSP_XRAM,
97	TGT_RSP_INIT,
98	TGT_RSP_CLEANUP
99	};
100
101	/* States of the INIT_CMD fsm */
102	enum init_cmd_fsm_state_e{
103	INIT_CMD_INVAL_IDLE,
104	INIT_CMD_INVAL_NLINE,
105	INIT_CMD_XRAM_BRDCAST,
106	INIT_CMD_UPDT_IDLE,
107	INIT_CMD_WRITE_BRDCAST,
108	INIT_CMD_UPDT_NLINE,
109	INIT_CMD_UPDT_INDEX,
110	INIT_CMD_UPDT_DATA,
111	INIT_CMD_SC_UPDT_IDLE,
112	INIT_CMD_SC_BRDCAST,
113	INIT_CMD_SC_UPDT_NLINE,
114	INIT_CMD_SC_UPDT_INDEX,
115	INIT_CMD_SC_UPDT_DATA,
116	INIT_CMD_SC_UPDT_DATA_HIGH
117	};
118
119	/* States of the INIT_RSP fsm */
120	enum init_rsp_fsm_state_e{
121	INIT_RSP_IDLE,
122	INIT_RSP_UPT_LOCK,
123	INIT_RSP_UPT_CLEAR,
124	INIT_RSP_END
125	};
126
127	/* States of the READ fsm */
128	enum read_fsm_state_e{
129	READ_IDLE,
130	READ_DIR_REQ,
131	READ_DIR_LOCK,
132	READ_DIR_HIT,
133	READ_HEAP_REQ,
134	READ_HEAP_LOCK,
135	READ_HEAP_WRITE,
136	READ_HEAP_ERASE,
137	READ_HEAP_LAST,
138	READ_RSP,
139	READ_TRT_LOCK,
140	READ_TRT_SET,
141	READ_TRT_REQ
142	};
143
144	/* States of the WRITE fsm */
145	enum write_fsm_state_e{
146	WRITE_IDLE,
147	WRITE_NEXT,
148	WRITE_DIR_REQ,
149	WRITE_DIR_LOCK,
150	WRITE_DIR_READ,
151	WRITE_DIR_HIT,
152	WRITE_UPT_LOCK,
153	WRITE_UPT_HEAP_LOCK,
154	WRITE_UPT_REQ,
155	WRITE_UPT_NEXT,
156	WRITE_UPT_DEC,
157	WRITE_RSP,
158	WRITE_MISS_TRT_LOCK,
159	WRITE_MISS_TRT_DATA,
160	WRITE_MISS_TRT_SET,
161	WRITE_MISS_XRAM_REQ,
162	WRITE_BC_TRT_LOCK,
163	WRITE_BC_UPT_LOCK,
164	WRITE_BC_DIR_INVAL,
165	WRITE_BC_CC_SEND,
166	WRITE_BC_XRAM_REQ,
167	WRITE_WAIT
168	};
169
170	/* States of the IXR_RSP fsm */
171	enum ixr_rsp_fsm_state_e{
172	IXR_RSP_IDLE,
173	IXR_RSP_ACK,
174	IXR_RSP_TRT_ERASE,
175	IXR_RSP_TRT_READ
176	};
177
178	/* States of the XRAM_RSP fsm */
179	enum xram_rsp_fsm_state_e{
180	XRAM_RSP_IDLE,
181	XRAM_RSP_TRT_COPY,
182	XRAM_RSP_TRT_DIRTY,
183	XRAM_RSP_DIR_LOCK,
184	XRAM_RSP_DIR_UPDT,
185	XRAM_RSP_DIR_RSP,
186	XRAM_RSP_INVAL_LOCK,
187	XRAM_RSP_INVAL_WAIT,
188	XRAM_RSP_INVAL,
189	XRAM_RSP_WRITE_DIRTY,
190	XRAM_RSP_HEAP_REQ,
191	XRAM_RSP_HEAP_ERASE,
192	XRAM_RSP_HEAP_LAST,
193	XRAM_RSP_ERROR_ERASE,
194	XRAM_RSP_ERROR_RSP
195	};
196
197	/* States of the IXR_CMD fsm */
198	enum ixr_cmd_fsm_state_e{
199	IXR_CMD_READ_IDLE,
200	IXR_CMD_WRITE_IDLE,
201	IXR_CMD_SC_IDLE,
202	IXR_CMD_XRAM_IDLE,
203	IXR_CMD_READ_NLINE,
204	IXR_CMD_WRITE_NLINE,
205	IXR_CMD_SC_NLINE,
206	IXR_CMD_XRAM_DATA
207	};
208
209	/* States of the SC fsm */
210	enum sc_fsm_state_e{
211	SC_IDLE,
212	SC_DIR_REQ,
213	SC_DIR_LOCK,
214	SC_DIR_HIT_READ,
215	SC_DIR_HIT_WRITE,
216	SC_UPT_LOCK,
217	SC_UPT_HEAP_LOCK,
218	SC_UPT_REQ,
219	SC_UPT_NEXT,
220	SC_BC_TRT_LOCK,
221	SC_BC_UPT_LOCK,
222	SC_BC_DIR_INVAL,
223	SC_BC_CC_SEND,
224	SC_BC_XRAM_REQ,
225	SC_RSP_FAIL,
226	SC_RSP_SUCCESS,
227	SC_MISS_TRT_LOCK,
228	SC_MISS_TRT_SET,
229	SC_MISS_XRAM_REQ,
230	SC_WAIT
231	};
232
233	/* States of the CLEANUP fsm */
234	enum cleanup_fsm_state_e{
235	CLEANUP_IDLE,
236	CLEANUP_DIR_REQ,
237	CLEANUP_DIR_LOCK,
238	CLEANUP_DIR_WRITE,
239	CLEANUP_HEAP_REQ,
240	CLEANUP_HEAP_LOCK,
241	CLEANUP_HEAP_SEARCH,
242	CLEANUP_HEAP_CLEAN,
243	CLEANUP_HEAP_FREE,
244	CLEANUP_UPT_LOCK,
245	CLEANUP_UPT_WRITE,
246	CLEANUP_WRITE_RSP,
247	CLEANUP_RSP
248	};
249
250	/* States of the ALLOC_DIR fsm */
251	enum alloc_dir_fsm_state_e{
252	ALLOC_DIR_RESET,
253	ALLOC_DIR_READ,
254	ALLOC_DIR_WRITE,
255	ALLOC_DIR_SC,
256	ALLOC_DIR_CLEANUP,
257	ALLOC_DIR_XRAM_RSP
258	};
259
260	/* States of the ALLOC_TRT fsm */
261	enum alloc_trt_fsm_state_e{
262	ALLOC_TRT_READ,
263	ALLOC_TRT_WRITE,
264	ALLOC_TRT_SC,
265	ALLOC_TRT_XRAM_RSP,
266	ALLOC_TRT_IXR_RSP
267	};
268
269	/* States of the ALLOC_UPT fsm */
270	enum alloc_upt_fsm_state_e{
271	ALLOC_UPT_WRITE,
272	ALLOC_UPT_XRAM_RSP,
273	ALLOC_UPT_INIT_RSP,
274	ALLOC_UPT_CLEANUP,
275	ALLOC_UPT_SC
276	};
277
278	/* States of the ALLOC_HEAP fsm */
279	enum alloc_heap_fsm_state_e{
280	ALLOC_HEAP_RESET,
281	ALLOC_HEAP_READ,
282	ALLOC_HEAP_WRITE,
283	ALLOC_HEAP_SC,
284	ALLOC_HEAP_CLEANUP,
285	ALLOC_HEAP_XRAM_RSP
286	};
287
288	// debug variables (for each FSM)
289	size_t m_debug_start_cycle;
290	bool m_debug_ok;
291	bool m_debug_global;
292	bool m_debug_tgt_cmd_fsm;
293	bool m_debug_tgt_rsp_fsm;
294	bool m_debug_init_cmd_fsm;
295	bool m_debug_init_rsp_fsm;
296	bool m_debug_read_fsm;
297	bool m_debug_write_fsm;
298	bool m_debug_sc_fsm;
299	bool m_debug_cleanup_fsm;
300	bool m_debug_ixr_cmd_fsm;
301	bool m_debug_ixr_rsp_fsm;
302	bool m_debug_xram_rsp_fsm;
303	bool m_debug_previous_hit;
304	size_t m_debug_previous_count;
305
306	bool m_monitor_ok;
307	vci_addr_t m_monitor_base;
308	vci_addr_t m_monitor_length;
309
310	// instrumentation counters
311	uint32_t m_cpt_cycles; // Counter of cycles
312	uint32_t m_cpt_read; // Number of READ transactions
313	uint32_t m_cpt_read_miss; // Number of MISS READ
314	uint32_t m_cpt_write; // Number of WRITE transactions
315	uint32_t m_cpt_write_miss; // Number of MISS WRITE
316	uint32_t m_cpt_write_cells; // Cumulated length for WRITE transactions
317	uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions
318	uint32_t m_cpt_update; // Number of UPDATE transactions
319	uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt
320	uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt
321	uint32_t m_cpt_update_mult; // Number of targets for UPDATE
322	uint32_t m_cpt_inval; // Number of INVAL transactions
323	uint32_t m_cpt_inval_mult; // Number of targets for INVAL
324	uint32_t m_cpt_inval_brdcast; // Number of BROADCAST INVAL
325	uint32_t m_cpt_cleanup; // Number of CLEANUP transactions
326	uint32_t m_cpt_ll; // Number of LL transactions
327	uint32_t m_cpt_sc; // Number of SC transactions
328
329	size_t m_prev_count;
330
331	protected:
332
333	SC_HAS_PROCESS(VciMemCacheV4);
334
335	public:
336	sc_in<bool> p_clk;
337	sc_in<bool> p_resetn;
338	soclib::caba::VciTarget<vci_param> p_vci_tgt;
339	soclib::caba::VciTarget<vci_param> p_vci_tgt_cleanup;
340	soclib::caba::VciInitiator<vci_param> p_vci_ini;
341	soclib::caba::VciInitiator<vci_param> p_vci_ixr;
342
343	VciMemCacheV4(
344	sc_module_name name, // Instance Name
345	const soclib::common::MappingTable &mtp, // Mapping table for primary requets
346	const soclib::common::MappingTable &mtc, // Mapping table for coherence requets
347	const soclib::common::MappingTable &mtx, // Mapping table for XRAM
348	const soclib::common::IntTab &vci_ixr_index, // VCI port to XRAM (initiator)
349	const soclib::common::IntTab &vci_ini_index, // VCI port to PROC (initiator)
350	const soclib::common::IntTab &vci_tgt_index, // VCI port to PROC (target)
351	const soclib::common::IntTab &vci_tgt_index_cleanup,// VCI port to PROC (target) for cleanup
352	size_t nways, // Number of ways per set
353	size_t nsets, // Number of sets
354	size_t nwords, // Number of words per line
355	size_t heap_size=1024, // Size of the heap
356	size_t transaction_tab_lines=TRANSACTION_TAB_LINES, // Size of the TRT
357	size_t update_tab_lines=UPDATE_TAB_LINES, // Size of the UPT
358	size_t debug_start_cycle=0,
359	bool debug_ok=false);
360
361	~VciMemCacheV4();
362
363	void print_stats();
364	void print_trace();
365	void copies_monitor(vci_addr_t addr);
366	void start_monitor(vci_addr_t addr, vci_addr_t length);
367	void stop_monitor();
368
369	private:
370
371	void transition();
372	void genMoore();
373	void check_monitor( const char *buf, vci_addr_t addr, data_t data);
374
375	// Component attributes
376	std::list<soclib::common::Segment> m_seglist; // memory cached into the cache
377	std::list<soclib::common::Segment> m_cseglist; // coherence segment for the cache
378
379	const size_t m_initiators; // Number of initiators
380	const size_t m_heap_size; // Size of the heap
381	const size_t m_ways; // Number of ways in a set
382	const size_t m_sets; // Number of cache sets
383	const size_t m_words; // Number of words in a line
384	const size_t m_srcid_ixr; // Srcid for requests to XRAM
385	const size_t m_srcid_ini; // Srcid for requests to processors
386
387	uint32_t m_transaction_tab_lines;
388	TransactionTab m_transaction_tab; // xram transaction table
389	uint32_t m_update_tab_lines;
390	UpdateTab m_update_tab; // pending update & invalidate
391	CacheDirectory m_cache_directory; // data cache directory
392	HeapDirectory m_heap; // heap for copies
393
394	data_t *** m_cache_data; // data array[set][way][word]
395
396	// adress masks
397	const soclib::common::AddressMaskingTable<vci_addr_t> m_x;
398	const soclib::common::AddressMaskingTable<vci_addr_t> m_y;
399	const soclib::common::AddressMaskingTable<vci_addr_t> m_z;
400	const soclib::common::AddressMaskingTable<vci_addr_t> m_nline;
401
402	// broadcast address
403	vci_addr_t m_broadcast_address;
404
405	//////////////////////////////////////////////////
406	// Others registers
407	//////////////////////////////////////////////////
408	sc_signal<size_t> r_copies_limit; // Limit of the number of copies for one line
409	sc_signal<size_t> xxx_count;
410
411	//////////////////////////////////////////////////
412	// Registers controlled by the TGT_CMD fsm
413	//////////////////////////////////////////////////
414
415	// Fifo between TGT_CMD fsm and READ fsm
416	GenericFifo<uint64_t> m_cmd_read_addr_fifo;
417	GenericFifo<size_t> m_cmd_read_length_fifo;
418	GenericFifo<size_t> m_cmd_read_srcid_fifo;
419	GenericFifo<size_t> m_cmd_read_trdid_fifo;
420	GenericFifo<size_t> m_cmd_read_pktid_fifo;
421
422	// Fifo between TGT_CMD fsm and WRITE fsm
423	GenericFifo<uint64_t> m_cmd_write_addr_fifo;
424	GenericFifo<bool> m_cmd_write_eop_fifo;
425	GenericFifo<size_t> m_cmd_write_srcid_fifo;
426	GenericFifo<size_t> m_cmd_write_trdid_fifo;
427	GenericFifo<size_t> m_cmd_write_pktid_fifo;
428	GenericFifo<data_t> m_cmd_write_data_fifo;
429	GenericFifo<be_t> m_cmd_write_be_fifo;
430
431	// Fifo between TGT_CMD fsm and SC fsm
432	GenericFifo<uint64_t> m_cmd_sc_addr_fifo;
433	GenericFifo<bool> m_cmd_sc_eop_fifo;
434	GenericFifo<size_t> m_cmd_sc_srcid_fifo;
435	GenericFifo<size_t> m_cmd_sc_trdid_fifo;
436	GenericFifo<size_t> m_cmd_sc_pktid_fifo;
437	GenericFifo<data_t> m_cmd_sc_wdata_fifo;
438
439	sc_signal<int> r_tgt_cmd_fsm;
440
441	size_t m_nseg;
442	size_t m_ncseg;
443	soclib::common::Segment **m_seg;
444	soclib::common::Segment **m_cseg;
445	///////////////////////////////////////////////////////
446	// Registers controlled by the READ fsm
447	///////////////////////////////////////////////////////
448
449	sc_signal<int> r_read_fsm; // FSM state
450	sc_signal<size_t> r_read_copy; // Srcid of the first copy
451	sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy
452	sc_signal<bool> r_read_copy_inst; // Type of the first copy
453	sc_signal<tag_t> r_read_tag; // cache line tag (in directory)
454	sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory)
455	sc_signal<bool> r_read_lock; // lock bit (in directory)
456	sc_signal<bool> r_read_dirty; // dirty bit (in directory)
457	sc_signal<size_t> r_read_count; // number of copies
458	sc_signal<size_t> r_read_ptr; // pointer to the heap
459	sc_signal<data_t> * r_read_data; // data (one cache line)
460	sc_signal<size_t> r_read_way; // associative way (in cache)
461	sc_signal<size_t> r_read_trt_index; // Transaction Table index
462	sc_signal<size_t> r_read_next_ptr; // Next entry to point to
463	sc_signal<bool> r_read_last_free; // Last free entry
464
465	// Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
466	sc_signal<bool> r_read_to_ixr_cmd_req; // valid request
467	sc_signal<addr_t> r_read_to_ixr_cmd_nline; // cache line index
468	sc_signal<size_t> r_read_to_ixr_cmd_trdid; // index in Transaction Table
469
470	// Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
471	sc_signal<bool> r_read_to_tgt_rsp_req; // valid request
472	sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid
473	sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid
474	sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid
475	sc_signal<data_t> * r_read_to_tgt_rsp_data; // data (one cache line)
476	sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response
477	sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response
478
479	///////////////////////////////////////////////////////////////
480	// Registers controlled by the WRITE fsm
481	///////////////////////////////////////////////////////////////
482
483	sc_signal<int> r_write_fsm; // FSM state
484	sc_signal<addr_t> r_write_address; // first word address
485	sc_signal<size_t> r_write_word_index; // first word index in line
486	sc_signal<size_t> r_write_word_count; // number of words in line
487	sc_signal<size_t> r_write_srcid; // transaction srcid
488	sc_signal<size_t> r_write_trdid; // transaction trdid
489	sc_signal<size_t> r_write_pktid; // transaction pktid
490	sc_signal<data_t> * r_write_data; // data (one cache line)
491	sc_signal<be_t> * r_write_be; // one byte enable per word
492	sc_signal<bool> r_write_byte; // (BE != 0X0) and (BE != 0xF)
493	sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory)
494	sc_signal<bool> r_write_lock; // lock bit (in directory)
495	sc_signal<tag_t> r_write_tag; // cache line tag (in directory)
496	sc_signal<size_t> r_write_copy; // first owner of the line
497	sc_signal<size_t> r_write_copy_cache; // first owner of the line
498	sc_signal<bool> r_write_copy_inst; // is this owner a ICache ?
499	sc_signal<size_t> r_write_count; // number of copies
500	sc_signal<size_t> r_write_ptr; // pointer to the heap
501	sc_signal<size_t> r_write_next_ptr; // next pointer to the heap
502	sc_signal<bool> r_write_to_dec; // need to decrement update counter
503	sc_signal<size_t> r_write_way; // way of the line
504	sc_signal<size_t> r_write_trt_index; // index in Transaction Table
505	sc_signal<size_t> r_write_upt_index; // index in Update Table
506
507	// Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
508	sc_signal<bool> r_write_to_tgt_rsp_req; // valid request
509	sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid
510	sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid
511	sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid
512
513	// Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
514	sc_signal<bool> r_write_to_ixr_cmd_req; // valid request
515	sc_signal<bool> r_write_to_ixr_cmd_write; // write request
516	sc_signal<addr_t> r_write_to_ixr_cmd_nline; // cache line index
517	sc_signal<data_t> * r_write_to_ixr_cmd_data; // cache line data
518	sc_signal<size_t> r_write_to_ixr_cmd_trdid; // index in Transaction Table
519
520	// Buffer between WRITE fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
521	sc_signal<bool> r_write_to_init_cmd_multi_req; // valid multicast request
522	sc_signal<bool> r_write_to_init_cmd_brdcast_req; // valid brdcast request
523	sc_signal<addr_t> r_write_to_init_cmd_nline; // cache line index
524	sc_signal<size_t> r_write_to_init_cmd_trdid; // index in Update Table
525	sc_signal<data_t> * r_write_to_init_cmd_data; // data (one cache line)
526	sc_signal<be_t> * r_write_to_init_cmd_be; // word enable
527	sc_signal<size_t> r_write_to_init_cmd_count; // number of words in line
528	sc_signal<size_t> r_write_to_init_cmd_index; // index of first word in line
529	GenericFifo<bool> m_write_to_init_cmd_inst_fifo; // fifo for the L1 type
530	GenericFifo<size_t> m_write_to_init_cmd_srcid_fifo; // fifo for srcids
531	GenericFifo<size_t> m_write_to_init_cmd_cache_id_fifo; // fifo for srcids
532
533	// Buffer between WRITE fsm and INIT_RSP fsm (Decrement UPT entry)
534	sc_signal<bool> r_write_to_init_rsp_req; // valid request
535	sc_signal<size_t> r_write_to_init_rsp_upt_index; // index in update table
536
537	/////////////////////////////////////////////////////////
538	// Registers controlled by INIT_RSP fsm
539	//////////////////////////////////////////////////////////
540
541	sc_signal<int> r_init_rsp_fsm; // FSM state
542	sc_signal<size_t> r_init_rsp_upt_index; // index in the Update Table
543	sc_signal<size_t> r_init_rsp_srcid; // pending write srcid
544	sc_signal<size_t> r_init_rsp_trdid; // pending write trdid
545	sc_signal<size_t> r_init_rsp_pktid; // pending write pktid
546	sc_signal<addr_t> r_init_rsp_nline; // pending write nline
547
548	// Buffer between INIT_RSP fsm and TGT_RSP fsm (complete write/update transaction)
549	sc_signal<bool> r_init_rsp_to_tgt_rsp_req; // valid request
550	sc_signal<size_t> r_init_rsp_to_tgt_rsp_srcid; // Transaction srcid
551	sc_signal<size_t> r_init_rsp_to_tgt_rsp_trdid; // Transaction trdid
552	sc_signal<size_t> r_init_rsp_to_tgt_rsp_pktid; // Transaction pktid
553
554	///////////////////////////////////////////////////////
555	// Registers controlled by CLEANUP fsm
556	///////////////////////////////////////////////////////
557
558	sc_signal<int> r_cleanup_fsm; // FSM state
559	sc_signal<size_t> r_cleanup_srcid; // transaction srcid
560	sc_signal<size_t> r_cleanup_trdid; // transaction trdid
561	sc_signal<size_t> r_cleanup_pktid; // transaction pktid
562	sc_signal<addr_t> r_cleanup_nline; // cache line index
563
564	sc_signal<copy_t> r_cleanup_copy; // first copy
565	sc_signal<copy_t> r_cleanup_copy_cache; // first copy
566	sc_signal<size_t> r_cleanup_copy_inst; // type of the first copy
567	sc_signal<copy_t> r_cleanup_count; // number of copies
568	sc_signal<size_t> r_cleanup_ptr; // pointer to the heap
569	sc_signal<size_t> r_cleanup_prev_ptr; // previous pointer to the heap
570	sc_signal<size_t> r_cleanup_prev_srcid; // srcid of previous heap entry
571	sc_signal<size_t> r_cleanup_prev_cache_id; // srcid of previous heap entry
572	sc_signal<bool> r_cleanup_prev_inst; // inst bit of previous heap entry
573	sc_signal<size_t> r_cleanup_next_ptr; // next pointer to the heap
574	sc_signal<tag_t> r_cleanup_tag; // cache line tag (in directory)
575	sc_signal<bool> r_cleanup_is_cnt; // inst bit (in directory)
576	sc_signal<bool> r_cleanup_lock; // lock bit (in directory)
577	sc_signal<bool> r_cleanup_dirty; // dirty bit (in directory)
578	sc_signal<size_t> r_cleanup_way; // associative way (in cache)
579
580	sc_signal<size_t> r_cleanup_write_srcid; // srcid of write response
581	sc_signal<size_t> r_cleanup_write_trdid; // trdid of write rsp
582	sc_signal<size_t> r_cleanup_write_pktid; // pktid of write rsp
583	sc_signal<bool> r_cleanup_need_rsp; // needs a write rsp
584
585	sc_signal<size_t> r_cleanup_index; // index of the INVAL line (in the UPT)
586
587	// Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
588	sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request
589	sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid
590	sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid
591	sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid
592
593	///////////////////////////////////////////////////////
594	// Registers controlled by SC fsm
595	///////////////////////////////////////////////////////
596
597	sc_signal<int> r_sc_fsm; // FSM state
598	sc_signal<data_t> r_sc_wdata; // write data word
599	sc_signal<data_t> * r_sc_rdata; // read data word
600	sc_signal<uint32_t> r_sc_lfsr; // lfsr for random introducing
601	sc_signal<size_t> r_sc_cpt; // size of command
602	sc_signal<copy_t> r_sc_copy; // Srcid of the first copy
603	sc_signal<copy_t> r_sc_copy_cache; // Srcid of the first copy
604	sc_signal<bool> r_sc_copy_inst; // Type of the first copy
605	sc_signal<size_t> r_sc_count; // number of copies
606	sc_signal<size_t> r_sc_ptr; // pointer to the heap
607	sc_signal<size_t> r_sc_next_ptr; // next pointer to the heap
608	sc_signal<bool> r_sc_is_cnt; // is_cnt bit (in directory)
609	sc_signal<bool> r_sc_dirty; // dirty bit (in directory)
610	sc_signal<size_t> r_sc_way; // way in directory
611	sc_signal<size_t> r_sc_set; // set in directory
612	sc_signal<data_t> r_sc_tag; // cache line tag (in directory)
613	sc_signal<size_t> r_sc_trt_index; // Transaction Table index
614	sc_signal<size_t> r_sc_upt_index; // Update Table index
615
616	// Buffer between SC fsm and INIT_CMD fsm (XRAM read)
617	sc_signal<bool> r_sc_to_ixr_cmd_req; // valid request
618	sc_signal<addr_t> r_sc_to_ixr_cmd_nline; // cache line index
619	sc_signal<size_t> r_sc_to_ixr_cmd_trdid; // index in Transaction Table
620	sc_signal<bool> r_sc_to_ixr_cmd_write; // write request
621	sc_signal<data_t> * r_sc_to_ixr_cmd_data; // cache line data
622
623
624	// Buffer between SC fsm and TGT_RSP fsm
625	sc_signal<bool> r_sc_to_tgt_rsp_req; // valid request
626	sc_signal<data_t> r_sc_to_tgt_rsp_data; // read data word
627	sc_signal<size_t> r_sc_to_tgt_rsp_srcid; // Transaction srcid
628	sc_signal<size_t> r_sc_to_tgt_rsp_trdid; // Transaction trdid
629	sc_signal<size_t> r_sc_to_tgt_rsp_pktid; // Transaction pktid
630
631	// Buffer between SC fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
632	sc_signal<bool> r_sc_to_init_cmd_multi_req; // valid request
633	sc_signal<bool> r_sc_to_init_cmd_brdcast_req; // brdcast request
634	sc_signal<addr_t> r_sc_to_init_cmd_nline; // cache line index
635	sc_signal<size_t> r_sc_to_init_cmd_trdid; // index in Update Table
636	sc_signal<data_t> r_sc_to_init_cmd_wdata; // data (one word)
637	sc_signal<bool> r_sc_to_init_cmd_is_long; // it is a 64 bits SC
638	sc_signal<data_t> r_sc_to_init_cmd_wdata_high; // data high (one word)
639	sc_signal<size_t> r_sc_to_init_cmd_index; // index of the word in line
640	GenericFifo<bool> m_sc_to_init_cmd_inst_fifo; // fifo for the L1 type
641	GenericFifo<size_t> m_sc_to_init_cmd_srcid_fifo; // fifo for srcids
642	GenericFifo<size_t> m_sc_to_init_cmd_cache_id_fifo; // fifo for srcids
643
644	// Buffer between SC fsm and INIT_RSP fsm (Decrement UPT entry)
645	sc_signal<bool> r_sc_to_init_rsp_req; // valid request
646	sc_signal<size_t> r_sc_to_init_rsp_upt_index; // index in update table
647
648	////////////////////////////////////////////////////
649	// Registers controlled by the IXR_RSP fsm
650	////////////////////////////////////////////////////
651
652	sc_signal<int> r_ixr_rsp_fsm; // FSM state
653	sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index
654	sc_signal<size_t> r_ixr_rsp_cpt; // word counter
655
656	// Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM)
657	sc_signal<bool> * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready
658
659	////////////////////////////////////////////////////
660	// Registers controlled by the XRAM_RSP fsm
661	////////////////////////////////////////////////////
662
663	sc_signal<int> r_xram_rsp_fsm; // FSM state
664	sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index
665	TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer
666	sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate
667	sc_signal<bool> r_xram_rsp_victim_is_cnt; // victim line inst bit
668	sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit
669	sc_signal<size_t> r_xram_rsp_victim_way; // victim line way
670	sc_signal<size_t> r_xram_rsp_victim_set; // victim line set
671	sc_signal<addr_t> r_xram_rsp_victim_nline; // victim line index
672	sc_signal<copy_t> r_xram_rsp_victim_copy; // victim line first copy
673	sc_signal<copy_t> r_xram_rsp_victim_copy_cache; // victim line first copy
674	sc_signal<bool> r_xram_rsp_victim_copy_inst; // victim line type of first copy
675	sc_signal<size_t> r_xram_rsp_victim_count; // victim line number of copies
676	sc_signal<size_t> r_xram_rsp_victim_ptr; // victim line pointer to the heap
677	sc_signal<data_t> * r_xram_rsp_victim_data; // victim line data
678	sc_signal<size_t> r_xram_rsp_upt_index; // UPT entry index
679	sc_signal<size_t> r_xram_rsp_next_ptr; // Next pointer to the heap
680
681	// Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache)
682	sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request
683	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid
684	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid
685	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid
686	sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data; // data (one cache line)
687	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_word; // first word index
688	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length; // length of the response
689	sc_signal<bool> r_xram_rsp_to_tgt_rsp_rerror; // send error to requester
690
691	// Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches)
692	sc_signal<bool> r_xram_rsp_to_init_cmd_multi_req; // Valid request
693	sc_signal<bool> r_xram_rsp_to_init_cmd_brdcast_req; // Broadcast request
694	sc_signal<addr_t> r_xram_rsp_to_init_cmd_nline; // cache line index;
695	sc_signal<size_t> r_xram_rsp_to_init_cmd_trdid; // index of UPT entry
696	GenericFifo<bool> m_xram_rsp_to_init_cmd_inst_fifo; // fifo for the L1 type
697	GenericFifo<size_t> m_xram_rsp_to_init_cmd_srcid_fifo; // fifo for srcids
698	GenericFifo<size_t> m_xram_rsp_to_init_cmd_cache_id_fifo; // fifo for srcids
699
700	// Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
701	sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request
702	sc_signal<addr_t> r_xram_rsp_to_ixr_cmd_nline; // cache line index
703	sc_signal<data_t> * r_xram_rsp_to_ixr_cmd_data; // cache line data
704	sc_signal<size_t> r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table
705
706	////////////////////////////////////////////////////
707	// Registers controlled by the IXR_CMD fsm
708	////////////////////////////////////////////////////
709
710	sc_signal<int> r_ixr_cmd_fsm;
711	sc_signal<size_t> r_ixr_cmd_cpt;
712
713	////////////////////////////////////////////////////
714	// Registers controlled by TGT_RSP fsm
715	////////////////////////////////////////////////////
716
717	sc_signal<int> r_tgt_rsp_fsm;
718	sc_signal<size_t> r_tgt_rsp_cpt;
719
720	////////////////////////////////////////////////////
721	// Registers controlled by INIT_CMD fsm
722	////////////////////////////////////////////////////
723
724	sc_signal<int> r_init_cmd_fsm;
725	sc_signal<size_t> r_init_cmd_cpt;
726	sc_signal<bool> r_init_cmd_inst;
727
728	////////////////////////////////////////////////////
729	// Registers controlled by ALLOC_DIR fsm
730	////////////////////////////////////////////////////
731
732	sc_signal<int> r_alloc_dir_fsm;
733	sc_signal<unsigned> r_alloc_dir_reset_cpt;
734
735	////////////////////////////////////////////////////
736	// Registers controlled by ALLOC_TRT fsm
737	////////////////////////////////////////////////////
738
739	sc_signal<int> r_alloc_trt_fsm;
740
741	////////////////////////////////////////////////////
742	// Registers controlled by ALLOC_UPT fsm
743	////////////////////////////////////////////////////
744
745	sc_signal<int> r_alloc_upt_fsm;
746
747	////////////////////////////////////////////////////
748	// Registers controlled by ALLOC_HEAP fsm
749	////////////////////////////////////////////////////
750
751	sc_signal<int> r_alloc_heap_fsm;
752	sc_signal<unsigned> r_alloc_heap_reset_cpt;
753	}; // end class VciMemCacheV4
754
755	}}
756
757	#endif
758
759	// Local Variables:
760	// tab-width: 2
761	// c-basic-offset: 2
762	// c-file-offsets:((innamespace . 0)(inline-open . 0))
763	// indent-tabs-mode: nil
764	// End:
765
766	// vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2
767

Note: See TracBrowser for help on using the repository browser.

Download in other formats:

Original Format