source: trunk/modules/vci_synthetic_target/caba/source/include/vci_synthetic_target.h @ 181

Last change on this file since 181 was 181, checked in by choichil, 12 years ago

Adding synthetic target made from vci_simple_ram

File size: 3.9 KB
Line 
1/* -*- c++ -*-
2 *
3 * SOCLIB_LGPL_HEADER_BEGIN
4 *
5 * This file is part of SoCLib, GNU LGPLv2.1.
6 *
7 * SoCLib is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU Lesser General Public License as published
9 * by the Free Software Foundation; version 2.1 of the License.
10 *
11 * SoCLib is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with SoCLib; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
19 * 02110-1301 USA
20 *
21 * SOCLIB_LGPL_HEADER_END
22 *
23 * Copyright (c) UPMC, Lip6, Asim
24 *         Christophe Choichillon <choichillon.christophe@gmail.com>, 2011
25 *
26 * Maintainers: Christophe Choichillon
27 */
28#ifndef SOCLIB_CABA_VCI_SYNTHETIC_TARGET_H
29#define SOCLIB_CABA_VCI_SYNTHETIC_TARGET_H
30
31#include <systemc>
32#include <vector>
33#include <list>
34#include <cassert>
35#include "caba_base_module.h"
36#include "vci_target.h"
37#include "mapping_table.h"
38#include "int_tab.h"
39#include "loader.h"
40#include "linked_access_buffer.h"
41#include "soclib_endian.h"
42
43namespace soclib {
44namespace caba {
45
46using namespace sc_core;
47
48template<typename vci_param>
49class VciSyntheticTarget
50        : public soclib::caba::BaseModule
51{
52public:
53
54        typedef typename vci_param::data_t  vci_data_t;
55        typedef typename vci_param::addr_t  vci_addr_t;
56        typedef typename vci_param::be_t    vci_be_t;
57        typedef typename vci_param::srcid_t vci_srcid_t;
58        typedef typename vci_param::trdid_t vci_trdid_t;
59        typedef typename vci_param::pktid_t vci_pktid_t;
60
61        typedef uint32_t       ram_t;
62
63    enum fsm_state_e {
64        FSM_IDLE,
65        FSM_CMD_GET,
66        FSM_CMD_WRITE,
67        FSM_CMD_ERROR,
68        FSM_RSP_READ,
69        FSM_RSP_WRITE,
70        FSM_RSP_LL,
71        FSM_RSP_SC,
72        FSM_RSP_ERROR,
73    };
74
75private:
76
77    soclib::common::Loader                  m_loader;
78    std::list<soclib::common::Segment>      m_seglist;
79    const uint32_t                          m_latency;
80
81    soclib::common::LinkedAccessBuffer<
82        vci_addr_t, vci_srcid_t>            r_llsc_buf;
83
84    sc_signal<int>                          r_fsm_state;
85    sc_signal<size_t>                       r_flit_count;
86    sc_signal<size_t>                       r_seg_index;
87    sc_signal<vci_addr_t>                   r_address;
88    sc_signal<vci_data_t>                   r_wdata;
89    sc_signal<vci_be_t>                     r_be;
90    sc_signal<vci_srcid_t>                  r_srcid;
91    sc_signal<vci_trdid_t>                  r_trdid;
92    sc_signal<vci_pktid_t>                  r_pktid;
93    sc_signal<bool>                         r_contig;
94    sc_signal<uint32_t>                     r_latency_count;
95
96    size_t                                  m_nbseg;
97    ram_t                                   **m_ram;
98    soclib::common::Segment                 **m_seg;
99
100    // Activity counters
101    uint32_t                            m_cpt_read;   // Count READ access
102    uint32_t                            m_cpt_write;  // Count WRITE access
103
104protected:
105
106        SC_HAS_PROCESS(VciSyntheticTarget);
107
108public:
109
110    // Ports
111    sc_in<bool>                             p_resetn;
112    sc_in<bool>                             p_clk;
113    soclib::caba::VciTarget<vci_param>      p_vci;
114
115    VciSyntheticTarget(sc_module_name insname,
116                 const soclib::common::IntTab index,
117                 const soclib::common::MappingTable &mt,
118                 const soclib::common::Loader &loader,
119                 const uint32_t latency = 0);
120
121    ~VciSyntheticTarget();
122
123    void print_trace();
124    void printStatistics();
125
126private:
127
128    bool write(size_t seg, vci_addr_t addr, vci_data_t wdata, vci_be_t be);
129    bool read( size_t seg, vci_addr_t addr, vci_data_t &rdata );
130    void transition();
131    void genMoore();
132    void reload();
133    void reset();
134
135};
136
137}}
138
139#endif
140
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