| 1 | /////////////////////////////////////////////////////////////////////////////// |
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| 2 | // File: top.cpp (for tsar_generic_iob platform) |
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| 3 | // Author: Alain Greiner |
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| 4 | // Copyright: UPMC/LIP6 |
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| 5 | // Date : august 2013 / updated march 2015 |
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| 6 | // This program is released under the GNU public license |
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| 7 | /////////////////////////////////////////////////////////////////////////////// |
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| 8 | // This file define a generic TSAR architecture with an external IO network |
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| 9 | // emulating a PCI or Hypertransport I/O bus to access 7 external peripherals: |
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| 10 | // |
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| 11 | // - BROM : boot ROM |
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| 12 | // - FBUF : Frame Buffer |
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| 13 | // - MTTY : multi TTY (up to 8 channels) |
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| 14 | // - MNIC : Network controller (up to 4 channels) |
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| 15 | // - DISK : Block device controler (BDV / HBA / SDC) |
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| 16 | // - IOPI : HWI to SWI translator. |
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| 17 | // |
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| 18 | // This I/0 bus is connected to internal address space through two IOB bridges |
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| 19 | // located in cluster[0][0] and cluster[X_SIZE-1][Y_SIZE-1]. |
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| 20 | // |
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| 21 | // The internal physical address space is 40 bits, and the cluster index |
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| 22 | // is defined by the 8 MSB bits, using a fixed format: X is encoded on 4 bits, |
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| 23 | // Y is encoded on 4 bits, whatever the actual mesh size. |
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| 24 | // => at most 16 * 16 clusters. Each cluster contains up to 4 processors. |
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| 25 | // |
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| 26 | // It contains 3 networks: |
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| 27 | // |
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| 28 | // 1) the "INT" network supports Read/Write transactions |
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| 29 | // between processors and L2 caches or peripherals. |
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| 30 | // (VCI ADDDRESS = 40 bits / VCI DATA width = 32 bits) |
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| 31 | // It supports also coherence transactions between L1 & L2 caches. |
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| 32 | // 3) the "RAM" network emulates the 3D network between L2 caches |
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| 33 | // and L3 caches, and is implemented as a 2D mesh between the L2 caches, |
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| 34 | // the two IO bridges and the physical RAMs disributed in all clusters. |
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| 35 | // (VCI ADDRESS = 40 bits / VCI DATA = 64 bits) |
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| 36 | // 4) the IOX network connects the two IO bridge components to the |
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| 37 | // 7 external peripheral controllers. |
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| 38 | // (VCI ADDDRESS = 40 bits / VCI DATA width = 64 bits) |
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| 39 | // |
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| 40 | // The external peripherals HWI IRQs are translated to WTI IRQs by the |
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| 41 | // external IOPIC component, that must be configured by the OS to route |
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| 42 | // these WTI IRQS to one or several internal XICU components. |
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| 43 | // - IOPIC HWI[3:0] connected to IRQ_NIC_RX[3:0] |
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| 44 | // - IOPIC HWI[7:4] connected to IRQ_NIC_TX[3:0] |
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| 45 | // - IOPIC HWI[12] connected to IRQ_IOC |
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| 46 | // - IOPIC HWI[23:16] connected to IRQ_TTY_RX[7:0] |
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| 47 | // - IOPIC HWI[31:24] connected to IRQ_TTY_TX[7:0] |
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| 48 | // |
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| 49 | // Each cluster contains the following component: |
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| 50 | // - From 1 to 8 MIP32 processors |
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| 51 | // - One L2 cache controller |
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| 52 | // - One XICU component, |
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| 53 | // - One multi channels DMA controler (number of channels is defined by nprocs) |
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| 54 | // The XICU component is mainly used to handle WTI IRQs, as at most |
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| 55 | // (nprocs + 1) HWI IRQs are connected to XICU in each cluster: |
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| 56 | // - IRQ_IN[0] : MMC |
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| 57 | // - IRQ_IN[1 to nprocs] : DMA |
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| 58 | // |
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| 59 | // All clusters are identical, but cluster(0,0) and cluster(XMAX-1,YMAX-1) |
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| 60 | // contain an extra IO bridge component and two DSPIN local-xbar to multiplex |
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| 61 | // the MEMC and IOB access to RAM network. These IOB0 & IOB1 components are |
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| 62 | // connected to the three networks (INT, RAM, IOX). |
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| 63 | // |
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| 64 | // - It uses two dspin_local_crossbar per cluster to implement the |
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| 65 | // local interconnect correponding to the INT network. |
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| 66 | // - It uses three dspin_local_crossbar per cluster to implement the |
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| 67 | // local interconnect correponding to the coherence INT network. |
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| 68 | // - It uses two virtual_dspin_router per cluster to implement |
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| 69 | // the INT network (routing both the direct and coherence trafic). |
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| 70 | // - It uses two dspin_router per cluster to implement the RAM network. |
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| 71 | // - It uses the vci_cc_vcache_wrapper. |
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| 72 | // - It uses the vci_mem_cache. |
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| 73 | // - It contains one vci_xicu and one vci_multi_dma per cluster. |
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| 74 | // - It contains one vci_simple ram per cluster to model the L3 cache. |
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| 75 | // |
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| 76 | // The TsarIobCluster component is defined in files |
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| 77 | // tsar_iob_cluster.* (with * = cpp, h, sd) |
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| 78 | // |
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| 79 | // The main hardware parameters must be defined in the hard_config.h file : |
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| 80 | // - X_WIDTH : number of bits for x cluster coordinate |
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| 81 | // - Y_WIDTH : number of bits for y cluster coordinate |
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| 82 | // - P_WIDTH : number of bits for local processor coordinate |
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| 83 | // - X_SIZE : number of clusters in a row |
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| 84 | // - Y_SIZE : number of clusters in a column |
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| 85 | // - NB_PROCS_MAX : number of processors per cluster (up to 8) |
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| 86 | // - NB_DMA_CHANNELS : number of DMA channels per cluster (>= NB_PROCS_MAX) |
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| 87 | // - NB_TXT_CHANNELS : number of TTY channels in I/O network (up to 16) |
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| 88 | // - NB_NIC_CHANNELS : number of NIC channels in I/O network (up to 4) |
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| 89 | // - FBUF_X_SIZE : width of frame buffer (pixels) |
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| 90 | // - FBUF_Y_SIZE : heigth of frame buffer (lines) |
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| 91 | // - ICU_NB_HWI : number of ICU HWIs (>= NB_PROCS_MAX + 1) |
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| 92 | // - ICU_NB_PTI : number of ICU PTIs (>= NB_PROCS_MAX) |
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| 93 | // - ICU_NB_WTI : number of ICU WTIs (>= 4*NB_PROCS_MAX) |
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| 94 | // - ICU_NB_OUT : number of ICU output IRQs (>= 4*NB_PROCS_MAX) |
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| 95 | // - USE_IOC_XYZ : IOC type (XYZ in HBA / BDV / SDC) |
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| 96 | // |
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| 97 | // Some other hardware parameters must be defined in this top.cpp file: |
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| 98 | // - XRAM_LATENCY : external ram latency |
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| 99 | // - MEMC_WAYS : L2 cache number of ways |
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| 100 | // - MEMC_SETS : L2 cache number of sets |
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| 101 | // - L1_IWAYS |
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| 102 | // - L1_ISETS |
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| 103 | // - L1_DWAYS |
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| 104 | // - L1_DSETS |
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| 105 | // - DISK_IMAGE_NAME : file pathname for block device |
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| 106 | // |
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| 107 | // General policy for 40 bits physical address decoding: |
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| 108 | // All physical segments base addresses are multiple of 1 Mbytes |
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| 109 | // (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) |
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| 110 | // The (x_width + y_width) MSB bits (left aligned) define |
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| 111 | // the cluster index, and the LADR bits define the local index: |
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| 112 | // |X_ID|Y_ID| LADR | OFFSET | |
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| 113 | // | 4 | 4 | 8 | 24 | |
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| 114 | // |
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| 115 | // General policy for 14 bits SRCID decoding: |
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| 116 | // Each component is identified by (x_id, y_id, l_id) tuple. |
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| 117 | // |X_ID|Y_ID| L_ID | |
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| 118 | // | 4 | 4 | 6 | |
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| 119 | // |
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| 120 | // The NIC controler has one VCI target port, and one VCI initiator port, |
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| 121 | // but it uses several LOCAL_SRCID values to distinguish channels. |
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| 122 | // because there is not enough bits in 4 bits TRDID field. |
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| 123 | ///////////////////////////////////////////////////////////////////////// |
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| 124 | |
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| 125 | #include <systemc> |
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| 126 | #include <sys/time.h> |
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| 127 | #include <iostream> |
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| 128 | #include <sstream> |
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| 129 | #include <cstdlib> |
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| 130 | #include <cstdarg> |
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| 131 | #include <stdint.h> |
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| 132 | |
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| 133 | #include "gdbserver.h" |
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| 134 | #include "mapping_table.h" |
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| 135 | |
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| 136 | #include "tsar_iob_cluster.h" |
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| 137 | #include "vci_chbuf_dma.h" |
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| 138 | #include "vci_tty_tsar.h" |
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| 139 | #include "vci_master_nic.h" |
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| 140 | #include "vci_simple_rom.h" |
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| 141 | #include "vci_multi_ahci.h" |
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| 142 | #include "vci_block_device_tsar.h" |
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| 143 | #include "vci_ahci_sdc.h" |
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| 144 | #include "sd_card.h" |
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| 145 | #include "vci_framebuffer.h" |
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| 146 | #include "vci_iox_network.h" |
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| 147 | #include "vci_iopic.h" |
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| 148 | |
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| 149 | #include "alloc_elems.h" |
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| 150 | |
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| 151 | |
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| 152 | ////////////////////////////////////////////////////////////////// |
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| 153 | // Virtual disk selection => OS selection |
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| 154 | ////////////////////////////////////////////////////////////////// |
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| 155 | |
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| 156 | #define USE_ALMOS 1 |
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| 157 | #define USE_GIET 0 |
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| 158 | |
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| 159 | #if ( USE_ALMOS + USE_GIET != 1 ) |
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| 160 | #error "OS UNDEFINED" |
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| 161 | #endif |
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| 162 | |
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| 163 | #if USE_ALMOS |
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| 164 | #define DISK_IMAGE_NAME "almos_virt_hdd.dmg" |
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| 165 | #endif |
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| 166 | |
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| 167 | #if USE_GIET |
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| 168 | #define DISK_IMAGE_NAME "giet_virt_hdd.dmg" |
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| 169 | #endif |
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| 170 | ////////////////////////////////////////////////////////////////// |
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| 171 | // Parallelisation |
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| 172 | ////////////////////////////////////////////////////////////////// |
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| 173 | |
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| 174 | #if USE_OPENMP |
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| 175 | #include <omp.h> |
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| 176 | #endif |
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| 177 | |
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| 178 | ////////////////////////////////////////////////////////////////// |
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| 179 | // DSPIN parameters |
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| 180 | ////////////////////////////////////////////////////////////////// |
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| 181 | |
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| 182 | #define dspin_int_cmd_width 39 |
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| 183 | #define dspin_int_rsp_width 32 |
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| 184 | |
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| 185 | #define dspin_ram_cmd_width 64 |
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| 186 | #define dspin_ram_rsp_width 64 |
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| 187 | |
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| 188 | ////////////////////////////////////////////////////////////////// |
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| 189 | // VCI fields width for the 3 VCI networks |
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| 190 | ////////////////////////////////////////////////////////////////// |
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| 191 | |
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| 192 | #define vci_cell_width_int 4 |
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| 193 | #define vci_cell_width_ext 8 |
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| 194 | |
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| 195 | #define vci_plen_width 8 |
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| 196 | #define vci_address_width 40 |
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| 197 | #define vci_rerror_width 1 |
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| 198 | #define vci_clen_width 1 |
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| 199 | #define vci_rflag_width 1 |
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| 200 | #define vci_srcid_width 14 |
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| 201 | #define vci_pktid_width 4 |
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| 202 | #define vci_trdid_width 4 |
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| 203 | #define vci_wrplen_width 1 |
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| 204 | |
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| 205 | //////////////////////////////////////////////////////////// |
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| 206 | // Main Hardware Parameters values |
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| 207 | //////////////////////i///////////////////////////////////// |
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| 208 | |
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| 209 | #include "hard_config.h" |
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| 210 | |
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| 211 | //////////////////////////////////////////////////////////// |
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| 212 | // Secondary Hardware Parameters values |
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| 213 | //////////////////////i///////////////////////////////////// |
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| 214 | |
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| 215 | #define XMAX X_SIZE |
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| 216 | #define YMAX Y_SIZE |
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| 217 | |
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| 218 | #define XRAM_LATENCY 0 |
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| 219 | |
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| 220 | #define MEMC_WAYS 16 |
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| 221 | #define MEMC_SETS 256 |
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| 222 | |
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| 223 | #define L1_IWAYS 4 |
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| 224 | #define L1_ISETS 64 |
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| 225 | |
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| 226 | #define L1_DWAYS 4 |
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| 227 | #define L1_DSETS 64 |
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| 228 | |
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| 229 | #define ROM_SOFT_NAME "../../softs/tsar_boot/preloader.elf" |
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| 230 | |
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| 231 | #define NORTH 0 |
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| 232 | #define SOUTH 1 |
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| 233 | #define EAST 2 |
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| 234 | #define WEST 3 |
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| 235 | |
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| 236 | #define cluster(x,y) ((y) + ((x) << 4)) |
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| 237 | |
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| 238 | //////////////////////////////////////////////////////////// |
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| 239 | // DEBUG Parameters default values |
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| 240 | //////////////////////i///////////////////////////////////// |
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| 241 | |
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| 242 | #define MAX_FROZEN_CYCLES 1000000 |
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| 243 | |
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| 244 | ///////////////////////////////////////////////////////// |
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| 245 | // Physical segments definition |
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| 246 | ///////////////////////////////////////////////////////// |
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| 247 | |
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| 248 | // All physical segments base addresses and sizes are defined |
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| 249 | // in the hard_config.h file. For replicated segments, the |
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| 250 | // base address is incremented by a cluster offset: |
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| 251 | // offset = cluster(x,y) << (address_width-x_width-y_width); |
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| 252 | |
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| 253 | //////////////////////////////////////////////////////////////////////// |
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| 254 | // SRCID definition |
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| 255 | //////////////////////////////////////////////////////////////////////// |
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| 256 | // All initiators are in the same indexing space (14 bits). |
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| 257 | // The SRCID is structured in two fields: |
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| 258 | // - The 8 MSB bits define the cluster index. |
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| 259 | // - The 6 LSB bits define the local index. |
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| 260 | // |
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| 261 | // Two different initiators cannot have the same SRCID, but a given |
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| 262 | // initiator can have two alias SRCIDs: |
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| 263 | // - Internal initiators (procs, mdma) are replicated in all clusters, |
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| 264 | // and each initiator has one single SRCID. |
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| 265 | // - External initiators (DISK,IOPI,MNIC) are not replicated, but can |
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| 266 | // be accessed in 2 clusters : cluster_iob0 and cluster_iob1. |
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| 267 | // They have the same local index, but two different cluster indexes. |
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| 268 | // As cluster_iob0 and cluster_iob1 contain both internal initiators |
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| 269 | // and external initiators, they must have different local indexes. |
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| 270 | // - Moreover, the MNIC has one single initiator port but can starts |
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| 271 | // 64 parallel transactions: 8 channels * 4 bursts * 2 directions. |
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| 272 | // The direction and burst index are specified in the TRDID field, |
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| 273 | // but the channel is specified in the SRCID field (8 values for |
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| 274 | // one single port). |
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| 275 | // |
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| 276 | // Consequence: For a local interconnect, the INI_ID port index |
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| 277 | // is NOT equal to the SRCID local index, and the local interconnect |
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| 278 | // must make a translation: SRCID => INI_ID |
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| 279 | //////////////////////////////////////////////////////////////////////// |
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| 280 | |
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| 281 | #define PROC_LOCAL_SRCID 0x00 // from 0x0 to 0x7 |
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| 282 | #define MDMA_LOCAL_SRCID 0x08 |
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| 283 | #define IOBX_LOCAL_SRCID 0x09 |
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| 284 | #define MEMC_LOCAL_SRCID 0x0A |
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| 285 | #define DISK_LOCAL_SRCID 0x0C |
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| 286 | #define IOPI_LOCAL_SRCID 0x0D |
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| 287 | |
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| 288 | #define MNI0_LOCAL_SRCID 0x10 // NIC channel 0 |
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| 289 | #define MNI1_LOCAL_SRCID 0x11 // NIC channel 1 |
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| 290 | #define MNI2_LOCAL_SRCID 0x12 // NIC channel 2 |
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| 291 | #define MNI3_LOCAL_SRCID 0x13 // NIC channel 3 |
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| 292 | #define MNI4_LOCAL_SRCID 0x14 // NIC channel 4 |
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| 293 | #define MNI5_LOCAL_SRCID 0x15 // NIC channel 5 |
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| 294 | #define MNI6_LOCAL_SRCID 0x16 // NIC channel 6 |
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| 295 | #define MNI7_LOCAL_SRCID 0x17 // NIC channel 7 |
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| 296 | |
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| 297 | /////////////////////////////////////////////////////////////////////// |
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| 298 | // TGT_ID and INI_ID port indexing for INT local interconnect |
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| 299 | /////////////////////////////////////////////////////////////////////// |
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| 300 | |
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| 301 | #define INT_MEMC_TGT_ID 0 |
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| 302 | #define INT_XICU_TGT_ID 1 |
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| 303 | #define INT_MDMA_TGT_ID 2 |
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| 304 | #define INT_IOBX_TGT_ID 3 |
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| 305 | |
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| 306 | #define INT_PROC_INI_ID 0 // from 0 to (NB_PROCS_MAX-1) |
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| 307 | #define INT_MDMA_INI_ID (NB_PROCS_MAX) |
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| 308 | #define INT_IOBX_INI_ID (NB_PROCS_MAX+1) |
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| 309 | |
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| 310 | /////////////////////////////////////////////////////////////////////// |
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| 311 | // TGT_ID and INI_ID port indexing for RAM local interconnect |
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| 312 | /////////////////////////////////////////////////////////////////////// |
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| 313 | |
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| 314 | #define RAM_XRAM_TGT_ID 0 |
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| 315 | |
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| 316 | #define RAM_MEMC_INI_ID 0 |
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| 317 | #define RAM_IOBX_INI_ID 1 |
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| 318 | |
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| 319 | /////////////////////////////////////////////////////////////////////// |
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| 320 | // TGT_ID and INI_ID port indexing for I0X local interconnect |
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| 321 | /////////////////////////////////////////////////////////////////////// |
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| 322 | |
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| 323 | #define IOX_FBUF_TGT_ID 0 |
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| 324 | #define IOX_DISK_TGT_ID 1 |
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| 325 | #define IOX_MNIC_TGT_ID 2 |
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| 326 | #define IOX_BROM_TGT_ID 3 |
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| 327 | #define IOX_MTTY_TGT_ID 4 |
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| 328 | #define IOX_IOPI_TGT_ID 5 |
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| 329 | #define IOX_IOB0_TGT_ID 6 |
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| 330 | #define IOX_IOB1_TGT_ID 7 |
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| 331 | |
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| 332 | #define IOX_DISK_INI_ID 0 |
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| 333 | #define IOX_IOPI_INI_ID 1 |
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| 334 | #define IOX_MNIC_INI_ID 2 |
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| 335 | #define IOX_IOB0_INI_ID 3 |
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| 336 | #define IOX_IOB1_INI_ID 4 |
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| 337 | |
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| 338 | //////////////////////////////////////////////////////////////////////// |
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| 339 | int _main(int argc, char *argv[]) |
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| 340 | //////////////////////////////////////////////////////////////////////// |
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| 341 | { |
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| 342 | using namespace sc_core; |
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| 343 | using namespace soclib::caba; |
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| 344 | using namespace soclib::common; |
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| 345 | |
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| 346 | char soft_name[256] = ROM_SOFT_NAME; // pathname: binary code |
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| 347 | size_t ncycles = 4000000000; // simulated cycles |
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| 348 | char disk_name[256] = DISK_IMAGE_NAME; // pathname: disk image |
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| 349 | ssize_t threads = 1; // simulator's threads number |
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| 350 | bool debug_ok = false; // trace activated when non-zero |
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| 351 | uint32_t debug_from = 0; // trace start cycle |
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| 352 | uint32_t debug_order = 0; // ln2( trace_period ) |
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| 353 | uint32_t debug_mask = 0; // trace_period - 1 |
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| 354 | uint32_t debug_memc_id = 0xFFFFFFFF; // index of traced memc |
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| 355 | uint32_t debug_proc_id = 0xFFFFFFFF; // index of traced proc |
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| 356 | bool debug_iob = false; // trace iob0 (& iob1) when true |
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| 357 | bool debug_ioc = false; // trace disk when true |
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| 358 | bool debug_nic = false; // trace mnic when true |
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| 359 | bool debug_txt = false; // trace mtty when true |
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| 360 | bool debug_fbf = false; // trace fbuf when true |
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| 361 | uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor |
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| 362 | size_t cluster_iob0 = cluster(0,0); // cluster containing IOB0 |
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| 363 | size_t cluster_iob1 = cluster(XMAX-1,YMAX-1); // cluster containing IOB1 |
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| 364 | size_t x_width = X_WIDTH; // # of bits for x |
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| 365 | size_t y_width = Y_WIDTH; // # of bits for y |
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| 366 | size_t p_width = P_WIDTH; // # of bits for lpid |
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| 367 | |
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| 368 | #if USE_OPENMP |
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| 369 | size_t simul_period = 1000000; |
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| 370 | #else |
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| 371 | size_t simul_period = 1; |
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| 372 | #endif |
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| 373 | |
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| 374 | assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and |
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| 375 | "ERROR: we must have X_WIDTH == Y_WIDTH == 4"); |
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| 376 | |
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| 377 | assert( P_WIDTH <= 4 and |
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| 378 | "ERROR: we must have P_WIDTH <= 4"); |
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| 379 | |
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| 380 | ////////////// command line arguments ////////////////////// |
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| 381 | if (argc > 1) |
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| 382 | { |
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| 383 | for (int n = 1; n < argc; n = n + 2) |
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| 384 | { |
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| 385 | if ((strcmp(argv[n],"-NCYCLES") == 0) && (n+1<argc)) |
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| 386 | { |
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| 387 | ncycles = atoi(argv[n+1]); |
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| 388 | } |
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| 389 | else if ((strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) ) |
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| 390 | { |
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| 391 | debug_ok = true; |
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| 392 | debug_from = atoi(argv[n+1]); |
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| 393 | } |
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| 394 | else if ((strcmp(argv[n],"-ORDER") == 0) && (n+1<argc) ) |
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| 395 | { |
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| 396 | debug_order = atoi(argv[n+1]); |
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| 397 | debug_mask = (1<<debug_order) - 1; |
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| 398 | } |
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| 399 | else if ((strcmp(argv[n],"-DISK") == 0) && (n+1<argc) ) |
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| 400 | { |
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| 401 | strcpy(disk_name, argv[n+1]); |
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| 402 | } |
|---|
| 403 | else if ((strcmp(argv[n],"-MEMCID") == 0) && (n+1<argc) ) |
|---|
| 404 | { |
|---|
| 405 | debug_memc_id = atoi(argv[n+1]); |
|---|
| 406 | size_t x = debug_memc_id >> 4; |
|---|
| 407 | size_t y = debug_memc_id & 0xF; |
|---|
| 408 | if( (x>=XMAX) || (y>=YMAX) ) |
|---|
| 409 | { |
|---|
| 410 | std::cout << "MEMCID parameter doesn't fit XMAX/YMAX" << std::endl; |
|---|
| 411 | std::cout << " - MEMCID = " << std::hex << debug_memc_id << std::endl; |
|---|
| 412 | std::cout << " - XMAX = " << std::hex << XMAX << std::endl; |
|---|
| 413 | std::cout << " - YMAX = " << std::hex << YMAX << std::endl; |
|---|
| 414 | exit(0); |
|---|
| 415 | } |
|---|
| 416 | } |
|---|
| 417 | else if ((strcmp(argv[n],"-IOB") == 0) && (n+1<argc) ) |
|---|
| 418 | { |
|---|
| 419 | debug_iob = atoi(argv[n+1]); |
|---|
| 420 | } |
|---|
| 421 | else if ((strcmp(argv[n],"-IOC") == 0) && (n+1<argc) ) |
|---|
| 422 | { |
|---|
| 423 | debug_ioc = atoi(argv[n+1]); |
|---|
| 424 | } |
|---|
| 425 | else if ((strcmp(argv[n],"-NIC") == 0) && (n+1<argc) ) |
|---|
| 426 | { |
|---|
| 427 | debug_nic = atoi(argv[n+1]); |
|---|
| 428 | } |
|---|
| 429 | else if ((strcmp(argv[n],"-TXT") == 0) && (n+1<argc) ) |
|---|
| 430 | { |
|---|
| 431 | debug_txt = atoi(argv[n+1]); |
|---|
| 432 | } |
|---|
| 433 | else if ((strcmp(argv[n],"-FBF") == 0) && (n+1<argc) ) |
|---|
| 434 | { |
|---|
| 435 | debug_fbf = atoi(argv[n+1]); |
|---|
| 436 | } |
|---|
| 437 | else if ((strcmp(argv[n],"-PROCID") == 0) && (n+1<argc) ) |
|---|
| 438 | { |
|---|
| 439 | debug_proc_id = atoi(argv[n+1]); |
|---|
| 440 | size_t cluster_xy = debug_proc_id >> P_WIDTH ; |
|---|
| 441 | size_t x = cluster_xy >> 4; |
|---|
| 442 | size_t y = cluster_xy & 0xF; |
|---|
| 443 | if( (x>=XMAX) || (y>=YMAX) ) |
|---|
| 444 | { |
|---|
| 445 | std::cout << "PROCID parameter does'nt fit XMAX/YMAX" << std::endl; |
|---|
| 446 | std::cout << " - PROCID = " << std::hex << debug_proc_id << std::endl; |
|---|
| 447 | std::cout << " - XMAX = " << std::hex << XMAX << std::endl; |
|---|
| 448 | std::cout << " - YMAX = " << std::hex << YMAX << std::endl; |
|---|
| 449 | exit(0); |
|---|
| 450 | } |
|---|
| 451 | } |
|---|
| 452 | else if ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc)) |
|---|
| 453 | { |
|---|
| 454 | threads = atoi(argv[n+1]); |
|---|
| 455 | threads = (threads < 1) ? 1 : threads; |
|---|
| 456 | } |
|---|
| 457 | else if ((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc)) |
|---|
| 458 | { |
|---|
| 459 | frozen_cycles = atoi(argv[n+1]); |
|---|
| 460 | } |
|---|
| 461 | else |
|---|
| 462 | { |
|---|
| 463 | std::cout << " Arguments are (key,value) couples." << std::endl; |
|---|
| 464 | std::cout << " The order is not important." << std::endl; |
|---|
| 465 | std::cout << " Accepted arguments are :" << std::endl << std::endl; |
|---|
| 466 | std::cout << " - NCYCLES number_of_simulated_cycles" << std::endl; |
|---|
| 467 | std::cout << " - DEBUG debug_start_cycle" << std::endl; |
|---|
| 468 | std::cout << " - THREADS simulator's threads number" << std::endl; |
|---|
| 469 | std::cout << " - FROZEN max_number_of_cycles" << std::endl; |
|---|
| 470 | std::cout << " - MEMCID index_memc_to_be_traced" << std::endl; |
|---|
| 471 | std::cout << " - PROCID index_proc_to_be_traced" << std::endl; |
|---|
| 472 | std::cout << " - IOB non_zero_value" << std::endl; |
|---|
| 473 | std::cout << " - IOC non_zero_value" << std::endl; |
|---|
| 474 | std::cout << " - NIC non_zero_value" << std::endl; |
|---|
| 475 | std::cout << " - TXT non_zero_value" << std::endl; |
|---|
| 476 | std::cout << " - FBF non_zero_value" << std::endl; |
|---|
| 477 | exit(0); |
|---|
| 478 | } |
|---|
| 479 | } |
|---|
| 480 | } |
|---|
| 481 | |
|---|
| 482 | // checking hardware parameters |
|---|
| 483 | assert( (XMAX <= 16) and |
|---|
| 484 | "Error in tsar_generic_iob : XMAX parameter cannot be larger than 16" ); |
|---|
| 485 | |
|---|
| 486 | assert( (YMAX <= 16) and |
|---|
| 487 | "Error in tsar_generic_iob : YMAX parameter cannot be larger than 16" ); |
|---|
| 488 | |
|---|
| 489 | assert( (NB_PROCS_MAX <= 8) and |
|---|
| 490 | "Error in tsar_generic_iob : NB_PROCS_MAX parameter cannot be larger than 8" ); |
|---|
| 491 | |
|---|
| 492 | assert( (ICU_NB_HWI > NB_PROCS_MAX) and |
|---|
| 493 | "Error in tsar_generic_iob : ICU_NB_HWI cannot be smaller than NB_PROCS_MAX" ); |
|---|
| 494 | |
|---|
| 495 | assert( (ICU_NB_PTI >= NB_PROCS_MAX) and |
|---|
| 496 | "Error in tsar_generic_iob : ICU_NB_PTI cannot be smaller than NB_PROCS_MAX" ); |
|---|
| 497 | |
|---|
| 498 | assert( (ICU_NB_WTI >= 4*NB_PROCS_MAX) and |
|---|
| 499 | "Error in tsar_generic_iob : ICU_NB_WTI cannot be smaller than 4*NB_PROCS_MAX" ); |
|---|
| 500 | |
|---|
| 501 | assert( (ICU_NB_OUT >= 4*NB_PROCS_MAX) and |
|---|
| 502 | "Error in tsar_generic_iob : ICU_NB_OUT cannot be smaller than 4*NB_PROCS_MAX" ); |
|---|
| 503 | |
|---|
| 504 | assert( (NB_TXT_CHANNELS >= 1) and (NB_TXT_CHANNELS <= 8) and |
|---|
| 505 | "Error in tsar_generic_iob : NB_TXT_CHANNELS parameter cannot be larger than 16" ); |
|---|
| 506 | |
|---|
| 507 | assert( (NB_NIC_CHANNELS <= 8) and |
|---|
| 508 | "Error in tsar_generic_iob : NB_NIC_CHANNELS parameter cannot be larger than 4" ); |
|---|
| 509 | |
|---|
| 510 | assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and |
|---|
| 511 | "Error in tsar_generic_iob : You must have X_WIDTH == Y_WIDTH == 4"); |
|---|
| 512 | |
|---|
| 513 | assert( ((USE_IOC_HBA + USE_IOC_BDV + USE_IOC_SDC) == 1) and |
|---|
| 514 | "Error in tsar_generic_iob : NoIOC controller found in hard_config.h"); |
|---|
| 515 | |
|---|
| 516 | std::cout << std::endl << std::dec |
|---|
| 517 | << " - XMAX = " << XMAX << std::endl |
|---|
| 518 | << " - YMAX = " << YMAX << std::endl |
|---|
| 519 | << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl |
|---|
| 520 | << " - NB_TXT_CHANNELS = " << NB_TXT_CHANNELS << std::endl |
|---|
| 521 | << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl |
|---|
| 522 | << " - MEMC_WAYS = " << MEMC_WAYS << std::endl |
|---|
| 523 | << " - MEMC_SETS = " << MEMC_SETS << std::endl |
|---|
| 524 | << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl |
|---|
| 525 | << " - MAX_FROZEN = " << frozen_cycles << std::endl |
|---|
| 526 | << " - NCYCLES = " << ncycles << std::endl |
|---|
| 527 | << " - SOFT_FILENAME = " << soft_name << std::endl |
|---|
| 528 | << " - DISK_IMAGENAME = " << disk_name << std::endl |
|---|
| 529 | << " - OPENMP THREADS = " << threads << std::endl |
|---|
| 530 | << " - DEBUG_PROCID = " << debug_proc_id << std::endl |
|---|
| 531 | << " - DEBUG_MEMCID = " << debug_memc_id << std::endl; |
|---|
| 532 | |
|---|
| 533 | std::cout << std::endl; |
|---|
| 534 | |
|---|
| 535 | #if USE_OPENMP |
|---|
| 536 | omp_set_dynamic(false); |
|---|
| 537 | omp_set_num_threads(threads); |
|---|
| 538 | std::cerr << "Built with openmp version " << _OPENMP << std::endl; |
|---|
| 539 | #endif |
|---|
| 540 | |
|---|
| 541 | // Define VciParams objects |
|---|
| 542 | typedef soclib::caba::VciParams<vci_cell_width_int, |
|---|
| 543 | vci_plen_width, |
|---|
| 544 | vci_address_width, |
|---|
| 545 | vci_rerror_width, |
|---|
| 546 | vci_clen_width, |
|---|
| 547 | vci_rflag_width, |
|---|
| 548 | vci_srcid_width, |
|---|
| 549 | vci_pktid_width, |
|---|
| 550 | vci_trdid_width, |
|---|
| 551 | vci_wrplen_width> vci_param_int; |
|---|
| 552 | |
|---|
| 553 | typedef soclib::caba::VciParams<vci_cell_width_ext, |
|---|
| 554 | vci_plen_width, |
|---|
| 555 | vci_address_width, |
|---|
| 556 | vci_rerror_width, |
|---|
| 557 | vci_clen_width, |
|---|
| 558 | vci_rflag_width, |
|---|
| 559 | vci_srcid_width, |
|---|
| 560 | vci_pktid_width, |
|---|
| 561 | vci_trdid_width, |
|---|
| 562 | vci_wrplen_width> vci_param_ext; |
|---|
| 563 | |
|---|
| 564 | ///////////////////////////////////////////////////////////////////// |
|---|
| 565 | // INT network mapping table |
|---|
| 566 | // - two levels address decoding for commands |
|---|
| 567 | // - two levels srcid decoding for responses |
|---|
| 568 | // - NB_PROCS_MAX + 2 (MDMA, IOBX) local initiators per cluster |
|---|
| 569 | // - 4 local targets (MEMC, XICU, MDMA, IOBX) per cluster |
|---|
| 570 | ///////////////////////////////////////////////////////////////////// |
|---|
| 571 | MappingTable maptab_int( vci_address_width, |
|---|
| 572 | IntTab(x_width + y_width, 16 - x_width - y_width), |
|---|
| 573 | IntTab(x_width + y_width, vci_srcid_width - x_width - y_width), |
|---|
| 574 | 0x00FF000000); |
|---|
| 575 | |
|---|
| 576 | for (size_t x = 0; x < XMAX; x++) |
|---|
| 577 | { |
|---|
| 578 | for (size_t y = 0; y < YMAX; y++) |
|---|
| 579 | { |
|---|
| 580 | uint64_t offset = ((uint64_t)cluster(x,y)) |
|---|
| 581 | << (vci_address_width-x_width-y_width); |
|---|
| 582 | bool config = true; |
|---|
| 583 | bool cacheable = true; |
|---|
| 584 | |
|---|
| 585 | // the four following segments are defined in all clusters |
|---|
| 586 | |
|---|
| 587 | std::ostringstream smemc_conf; |
|---|
| 588 | smemc_conf << "int_seg_memc_conf_" << x << "_" << y; |
|---|
| 589 | maptab_int.add(Segment(smemc_conf.str(), SEG_MMC_BASE+offset, SEG_MMC_SIZE, |
|---|
| 590 | IntTab(cluster(x,y), INT_MEMC_TGT_ID), not cacheable, config )); |
|---|
| 591 | |
|---|
| 592 | std::ostringstream smemc_xram; |
|---|
| 593 | smemc_xram << "int_seg_memc_xram_" << x << "_" << y; |
|---|
| 594 | maptab_int.add(Segment(smemc_xram.str(), SEG_RAM_BASE+offset, SEG_RAM_SIZE, |
|---|
| 595 | IntTab(cluster(x,y), INT_MEMC_TGT_ID), cacheable)); |
|---|
| 596 | |
|---|
| 597 | std::ostringstream sxicu; |
|---|
| 598 | sxicu << "int_seg_xicu_" << x << "_" << y; |
|---|
| 599 | maptab_int.add(Segment(sxicu.str(), SEG_ICU_BASE+offset, SEG_ICU_SIZE, |
|---|
| 600 | IntTab(cluster(x,y), INT_XICU_TGT_ID), not cacheable)); |
|---|
| 601 | |
|---|
| 602 | std::ostringstream smdma; |
|---|
| 603 | smdma << "int_seg_mdma_" << x << "_" << y; |
|---|
| 604 | maptab_int.add(Segment(smdma.str(), SEG_DMA_BASE+offset, SEG_DMA_SIZE, |
|---|
| 605 | IntTab(cluster(x,y), INT_MDMA_TGT_ID), not cacheable)); |
|---|
| 606 | |
|---|
| 607 | // the following segments are only defined in cluster_iob0 or in cluster_iob1 |
|---|
| 608 | |
|---|
| 609 | if ( (cluster(x,y) == cluster_iob0) or (cluster(x,y) == cluster_iob1) ) |
|---|
| 610 | { |
|---|
| 611 | std::ostringstream siobx; |
|---|
| 612 | siobx << "int_seg_iobx_" << x << "_" << y; |
|---|
| 613 | maptab_int.add(Segment(siobx.str(), SEG_IOB_BASE+offset, SEG_IOB_SIZE, |
|---|
| 614 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable, config )); |
|---|
| 615 | |
|---|
| 616 | std::ostringstream stty; |
|---|
| 617 | stty << "int_seg_mtty_" << x << "_" << y; |
|---|
| 618 | maptab_int.add(Segment(stty.str(), SEG_TXT_BASE+offset, SEG_TXT_SIZE, |
|---|
| 619 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
|---|
| 620 | |
|---|
| 621 | std::ostringstream sfbf; |
|---|
| 622 | sfbf << "int_seg_fbuf_" << x << "_" << y; |
|---|
| 623 | maptab_int.add(Segment(sfbf.str(), SEG_FBF_BASE+offset, SEG_FBF_SIZE, |
|---|
| 624 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
|---|
| 625 | |
|---|
| 626 | std::ostringstream sdsk; |
|---|
| 627 | sdsk << "int_seg_disk_" << x << "_" << y; |
|---|
| 628 | maptab_int.add(Segment(sdsk.str(), SEG_IOC_BASE+offset, SEG_IOC_SIZE, |
|---|
| 629 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
|---|
| 630 | |
|---|
| 631 | std::ostringstream snic; |
|---|
| 632 | snic << "int_seg_mnic_" << x << "_" << y; |
|---|
| 633 | maptab_int.add(Segment(snic.str(), SEG_NIC_BASE+offset, SEG_NIC_SIZE, |
|---|
| 634 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
|---|
| 635 | |
|---|
| 636 | std::ostringstream srom; |
|---|
| 637 | srom << "int_seg_brom_" << x << "_" << y; |
|---|
| 638 | maptab_int.add(Segment(srom.str(), SEG_ROM_BASE+offset, SEG_ROM_SIZE, |
|---|
| 639 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), cacheable )); |
|---|
| 640 | |
|---|
| 641 | std::ostringstream spic; |
|---|
| 642 | spic << "int_seg_iopi_" << x << "_" << y; |
|---|
| 643 | maptab_int.add(Segment(spic.str(), SEG_PIC_BASE+offset, SEG_PIC_SIZE, |
|---|
| 644 | IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); |
|---|
| 645 | } |
|---|
| 646 | |
|---|
| 647 | // This define the mapping between the SRCIDs |
|---|
| 648 | // and the port index on the local interconnect. |
|---|
| 649 | |
|---|
| 650 | maptab_int.srcid_map( IntTab( cluster(x,y), MDMA_LOCAL_SRCID ), |
|---|
| 651 | IntTab( cluster(x,y), INT_MDMA_INI_ID ) ); |
|---|
| 652 | |
|---|
| 653 | maptab_int.srcid_map( IntTab( cluster(x,y), IOBX_LOCAL_SRCID ), |
|---|
| 654 | IntTab( cluster(x,y), INT_IOBX_INI_ID ) ); |
|---|
| 655 | |
|---|
| 656 | maptab_int.srcid_map( IntTab( cluster(x,y), IOPI_LOCAL_SRCID ), |
|---|
| 657 | IntTab( cluster(x,y), INT_IOBX_INI_ID ) ); |
|---|
| 658 | |
|---|
| 659 | for ( size_t p = 0 ; p < NB_PROCS_MAX; p++ ) |
|---|
| 660 | maptab_int.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+p ), |
|---|
| 661 | IntTab( cluster(x,y), INT_PROC_INI_ID+p ) ); |
|---|
| 662 | } |
|---|
| 663 | } |
|---|
| 664 | std::cout << "INT network " << maptab_int << std::endl; |
|---|
| 665 | |
|---|
| 666 | ///////////////////////////////////////////////////////////////////////// |
|---|
| 667 | // RAM network mapping table |
|---|
| 668 | // - two levels address decoding for commands |
|---|
| 669 | // - two levels srcid decoding for responses |
|---|
| 670 | // - 2 local initiators (MEMC, IOBX) per cluster |
|---|
| 671 | // (IOBX component only in cluster_iob0 and cluster_iob1) |
|---|
| 672 | // - 1 local target (XRAM) per cluster |
|---|
| 673 | //////////////////////////////////////////////////////////////////////// |
|---|
| 674 | MappingTable maptab_ram( vci_address_width, |
|---|
| 675 | IntTab(x_width+y_width, 0), |
|---|
| 676 | IntTab(x_width+y_width, vci_srcid_width - x_width - y_width), |
|---|
| 677 | 0x00FF000000); |
|---|
| 678 | |
|---|
| 679 | for (size_t x = 0; x < XMAX; x++) |
|---|
| 680 | { |
|---|
| 681 | for (size_t y = 0; y < YMAX ; y++) |
|---|
| 682 | { |
|---|
| 683 | uint64_t offset = ((uint64_t)cluster(x,y)) |
|---|
| 684 | << (vci_address_width-x_width-y_width); |
|---|
| 685 | |
|---|
| 686 | std::ostringstream sxram; |
|---|
| 687 | sxram << "ext_seg_xram_" << x << "_" << y; |
|---|
| 688 | maptab_ram.add(Segment(sxram.str(), SEG_RAM_BASE+offset, |
|---|
| 689 | SEG_RAM_SIZE, IntTab(cluster(x,y), RAM_XRAM_TGT_ID), false)); |
|---|
| 690 | } |
|---|
| 691 | } |
|---|
| 692 | |
|---|
| 693 | // This define the mapping between the initiators SRCID |
|---|
| 694 | // and the port index on the RAM local interconnect. |
|---|
| 695 | // This routing table is used to route the response to the |
|---|
| 696 | // relevant initiator: external peripherals transactions |
|---|
| 697 | // use IOBX port, while MEMC transactions use MEMC port. |
|---|
| 698 | |
|---|
| 699 | maptab_ram.srcid_map( IntTab( cluster_iob0, DISK_LOCAL_SRCID ), |
|---|
| 700 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
|---|
| 701 | maptab_ram.srcid_map( IntTab( cluster_iob1, DISK_LOCAL_SRCID ), |
|---|
| 702 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
|---|
| 703 | |
|---|
| 704 | maptab_ram.srcid_map( IntTab( cluster_iob0, IOPI_LOCAL_SRCID ), |
|---|
| 705 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
|---|
| 706 | maptab_ram.srcid_map( IntTab( cluster_iob1, IOPI_LOCAL_SRCID ), |
|---|
| 707 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
|---|
| 708 | |
|---|
| 709 | maptab_ram.srcid_map( IntTab( cluster_iob0, MNI0_LOCAL_SRCID ), |
|---|
| 710 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
|---|
| 711 | maptab_ram.srcid_map( IntTab( cluster_iob1, MNI0_LOCAL_SRCID ), |
|---|
| 712 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
|---|
| 713 | |
|---|
| 714 | maptab_ram.srcid_map( IntTab( cluster_iob0, MNI1_LOCAL_SRCID ), |
|---|
| 715 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
|---|
| 716 | maptab_ram.srcid_map( IntTab( cluster_iob1, MNI1_LOCAL_SRCID ), |
|---|
| 717 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
|---|
| 718 | |
|---|
| 719 | maptab_ram.srcid_map( IntTab( cluster_iob0, MNI2_LOCAL_SRCID ), |
|---|
| 720 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
|---|
| 721 | maptab_ram.srcid_map( IntTab( cluster_iob1, MNI2_LOCAL_SRCID ), |
|---|
| 722 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
|---|
| 723 | |
|---|
| 724 | maptab_ram.srcid_map( IntTab( cluster_iob0, MNI3_LOCAL_SRCID ), |
|---|
| 725 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
|---|
| 726 | maptab_ram.srcid_map( IntTab( cluster_iob1, MNI3_LOCAL_SRCID ), |
|---|
| 727 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
|---|
| 728 | |
|---|
| 729 | maptab_ram.srcid_map( IntTab( cluster_iob0, MNI4_LOCAL_SRCID ), |
|---|
| 730 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
|---|
| 731 | maptab_ram.srcid_map( IntTab( cluster_iob1, MNI4_LOCAL_SRCID ), |
|---|
| 732 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
|---|
| 733 | |
|---|
| 734 | maptab_ram.srcid_map( IntTab( cluster_iob0, MNI5_LOCAL_SRCID ), |
|---|
| 735 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
|---|
| 736 | maptab_ram.srcid_map( IntTab( cluster_iob1, MNI5_LOCAL_SRCID ), |
|---|
| 737 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
|---|
| 738 | |
|---|
| 739 | maptab_ram.srcid_map( IntTab( cluster_iob0, MNI6_LOCAL_SRCID ), |
|---|
| 740 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
|---|
| 741 | maptab_ram.srcid_map( IntTab( cluster_iob1, MNI6_LOCAL_SRCID ), |
|---|
| 742 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
|---|
| 743 | |
|---|
| 744 | maptab_ram.srcid_map( IntTab( cluster_iob0, MNI7_LOCAL_SRCID ), |
|---|
| 745 | IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); |
|---|
| 746 | maptab_ram.srcid_map( IntTab( cluster_iob1, MNI7_LOCAL_SRCID ), |
|---|
| 747 | IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); |
|---|
| 748 | |
|---|
| 749 | maptab_ram.srcid_map( IntTab( cluster_iob0, MEMC_LOCAL_SRCID ), |
|---|
| 750 | IntTab( cluster_iob0, RAM_MEMC_INI_ID ) ); |
|---|
| 751 | maptab_ram.srcid_map( IntTab( cluster_iob1, MEMC_LOCAL_SRCID ), |
|---|
| 752 | IntTab( cluster_iob1, RAM_MEMC_INI_ID ) ); |
|---|
| 753 | |
|---|
| 754 | std::cout << "RAM network " << maptab_ram << std::endl; |
|---|
| 755 | |
|---|
| 756 | /////////////////////////////////////////////////////////////////////// |
|---|
| 757 | // IOX network mapping table |
|---|
| 758 | // - two levels address decoding for commands |
|---|
| 759 | // - two levels srcid decoding for responses |
|---|
| 760 | // - 5 initiators (IOB0, IOB1, DISK, MNIC, IOPI) |
|---|
| 761 | // - 8 targets (IOB0, IOB1, DISK, MTTY, FBUF, BROM, MNIC, IOPI) |
|---|
| 762 | // |
|---|
| 763 | // Address bit 32 is used to determine if a command must be routed to |
|---|
| 764 | // IOB0 or IOB1. |
|---|
| 765 | /////////////////////////////////////////////////////////////////////// |
|---|
| 766 | MappingTable maptab_iox( |
|---|
| 767 | vci_address_width, |
|---|
| 768 | IntTab(x_width + y_width - 1, 16 - x_width - y_width + 1), |
|---|
| 769 | IntTab(x_width + y_width , vci_param_ext::S - x_width - y_width), |
|---|
| 770 | 0x00FF000000); |
|---|
| 771 | |
|---|
| 772 | // External peripherals segments |
|---|
| 773 | // When there is more than one cluster, external peripherals can be accessed |
|---|
| 774 | // through two segments, depending on the used IOB (IOB0 or IOB1). |
|---|
| 775 | |
|---|
| 776 | const uint64_t iob0_base = ((uint64_t)cluster_iob0) |
|---|
| 777 | << (vci_address_width - x_width - y_width); |
|---|
| 778 | |
|---|
| 779 | maptab_iox.add(Segment("iox_seg_mtty_0", SEG_TXT_BASE + iob0_base, SEG_TXT_SIZE, |
|---|
| 780 | IntTab(0, IOX_MTTY_TGT_ID), false)); |
|---|
| 781 | maptab_iox.add(Segment("iox_seg_fbuf_0", SEG_FBF_BASE + iob0_base, SEG_FBF_SIZE, |
|---|
| 782 | IntTab(0, IOX_FBUF_TGT_ID), false)); |
|---|
| 783 | maptab_iox.add(Segment("iox_seg_disk_0", SEG_IOC_BASE + iob0_base, SEG_IOC_SIZE, |
|---|
| 784 | IntTab(0, IOX_DISK_TGT_ID), false)); |
|---|
| 785 | maptab_iox.add(Segment("iox_seg_mnic_0", SEG_NIC_BASE + iob0_base, SEG_NIC_SIZE, |
|---|
| 786 | IntTab(0, IOX_MNIC_TGT_ID), false)); |
|---|
| 787 | maptab_iox.add(Segment("iox_seg_brom_0", SEG_ROM_BASE + iob0_base, SEG_ROM_SIZE, |
|---|
| 788 | IntTab(0, IOX_BROM_TGT_ID), false)); |
|---|
| 789 | maptab_iox.add(Segment("iox_seg_iopi_0", SEG_PIC_BASE + iob0_base, SEG_PIC_SIZE, |
|---|
| 790 | IntTab(0, IOX_IOPI_TGT_ID), false)); |
|---|
| 791 | |
|---|
| 792 | if ( cluster_iob0 != cluster_iob1 ) |
|---|
| 793 | { |
|---|
| 794 | const uint64_t iob1_base = ((uint64_t)cluster_iob1) |
|---|
| 795 | << (vci_address_width - x_width - y_width); |
|---|
| 796 | |
|---|
| 797 | maptab_iox.add(Segment("iox_seg_mtty_1", SEG_TXT_BASE + iob1_base, SEG_TXT_SIZE, |
|---|
| 798 | IntTab(0, IOX_MTTY_TGT_ID), false)); |
|---|
| 799 | maptab_iox.add(Segment("iox_seg_fbuf_1", SEG_FBF_BASE + iob1_base, SEG_FBF_SIZE, |
|---|
| 800 | IntTab(0, IOX_FBUF_TGT_ID), false)); |
|---|
| 801 | maptab_iox.add(Segment("iox_seg_disk_1", SEG_IOC_BASE + iob1_base, SEG_IOC_SIZE, |
|---|
| 802 | IntTab(0, IOX_DISK_TGT_ID), false)); |
|---|
| 803 | maptab_iox.add(Segment("iox_seg_mnic_1", SEG_NIC_BASE + iob1_base, SEG_NIC_SIZE, |
|---|
| 804 | IntTab(0, IOX_MNIC_TGT_ID), false)); |
|---|
| 805 | maptab_iox.add(Segment("iox_seg_brom_1", SEG_ROM_BASE + iob1_base, SEG_ROM_SIZE, |
|---|
| 806 | IntTab(0, IOX_BROM_TGT_ID), false)); |
|---|
| 807 | maptab_iox.add(Segment("iox_seg_iopi_1", SEG_PIC_BASE + iob1_base, SEG_PIC_SIZE, |
|---|
| 808 | IntTab(0, IOX_IOPI_TGT_ID), false)); |
|---|
| 809 | } |
|---|
| 810 | |
|---|
| 811 | // If there is more than one cluster, external peripherals |
|---|
| 812 | // can access RAM through two segments (IOB0 / IOB1). |
|---|
| 813 | // As IOMMU is not activated, addresses are 40 bits (physical addresses), |
|---|
| 814 | // and the choice depends on address bit A[32]. |
|---|
| 815 | for (size_t x = 0; x < XMAX; x++) |
|---|
| 816 | { |
|---|
| 817 | for (size_t y = 0; y < YMAX ; y++) |
|---|
| 818 | { |
|---|
| 819 | const bool wti = true; |
|---|
| 820 | const bool cacheable = true; |
|---|
| 821 | |
|---|
| 822 | const uint64_t offset = ((uint64_t)cluster(x,y)) |
|---|
| 823 | << (vci_address_width-x_width-y_width); |
|---|
| 824 | |
|---|
| 825 | const uint64_t xicu_base = SEG_ICU_BASE + offset; |
|---|
| 826 | |
|---|
| 827 | if ( (y & 0x1) == 0 ) // use IOB0 |
|---|
| 828 | { |
|---|
| 829 | std::ostringstream sxcu0; |
|---|
| 830 | sxcu0 << "iox_seg_xcu0_" << x << "_" << y; |
|---|
| 831 | maptab_iox.add(Segment(sxcu0.str(), xicu_base, SEG_ICU_SIZE, |
|---|
| 832 | IntTab(0, IOX_IOB0_TGT_ID), not cacheable, wti)); |
|---|
| 833 | |
|---|
| 834 | std::ostringstream siob0; |
|---|
| 835 | siob0 << "iox_seg_ram0_" << x << "_" << y; |
|---|
| 836 | maptab_iox.add(Segment(siob0.str(), offset, SEG_ICU_BASE, |
|---|
| 837 | IntTab(0, IOX_IOB0_TGT_ID), not cacheable, not wti)); |
|---|
| 838 | } |
|---|
| 839 | else // USE IOB1 |
|---|
| 840 | { |
|---|
| 841 | std::ostringstream sxcu1; |
|---|
| 842 | sxcu1 << "iox_seg_xcu1_" << x << "_" << y; |
|---|
| 843 | maptab_iox.add(Segment(sxcu1.str(), xicu_base, SEG_ICU_SIZE, |
|---|
| 844 | IntTab(0, IOX_IOB1_TGT_ID), not cacheable, wti)); |
|---|
| 845 | |
|---|
| 846 | std::ostringstream siob1; |
|---|
| 847 | siob1 << "iox_seg_ram1_" << x << "_" << y; |
|---|
| 848 | maptab_iox.add(Segment(siob1.str(), offset, SEG_ICU_BASE, |
|---|
| 849 | IntTab(0, IOX_IOB1_TGT_ID), not cacheable, not wti)); |
|---|
| 850 | } |
|---|
| 851 | } |
|---|
| 852 | } |
|---|
| 853 | |
|---|
| 854 | // This define the mapping between the external initiators (SRCID) |
|---|
| 855 | // and the initiator port index on the IOX local interconnect. |
|---|
| 856 | |
|---|
| 857 | maptab_iox.srcid_map( IntTab( 0, DISK_LOCAL_SRCID ) , |
|---|
| 858 | IntTab( 0, IOX_DISK_INI_ID ) ); |
|---|
| 859 | |
|---|
| 860 | maptab_iox.srcid_map( IntTab( 0, IOPI_LOCAL_SRCID ) , |
|---|
| 861 | IntTab( 0, IOX_IOPI_INI_ID ) ); |
|---|
| 862 | |
|---|
| 863 | maptab_iox.srcid_map( IntTab( 0, IOX_IOB0_INI_ID ) , |
|---|
| 864 | IntTab( 0, IOX_IOB0_INI_ID ) ); |
|---|
| 865 | |
|---|
| 866 | maptab_iox.srcid_map( IntTab( 0, MNI0_LOCAL_SRCID ) , |
|---|
| 867 | IntTab( 0, IOX_MNIC_INI_ID ) ); |
|---|
| 868 | maptab_iox.srcid_map( IntTab( 0, MNI1_LOCAL_SRCID ) , |
|---|
| 869 | IntTab( 0, IOX_MNIC_INI_ID ) ); |
|---|
| 870 | maptab_iox.srcid_map( IntTab( 0, MNI2_LOCAL_SRCID ) , |
|---|
| 871 | IntTab( 0, IOX_MNIC_INI_ID ) ); |
|---|
| 872 | maptab_iox.srcid_map( IntTab( 0, MNI3_LOCAL_SRCID ) , |
|---|
| 873 | IntTab( 0, IOX_MNIC_INI_ID ) ); |
|---|
| 874 | maptab_iox.srcid_map( IntTab( 0, MNI4_LOCAL_SRCID ) , |
|---|
| 875 | IntTab( 0, IOX_MNIC_INI_ID ) ); |
|---|
| 876 | maptab_iox.srcid_map( IntTab( 0, MNI5_LOCAL_SRCID ) , |
|---|
| 877 | IntTab( 0, IOX_MNIC_INI_ID ) ); |
|---|
| 878 | maptab_iox.srcid_map( IntTab( 0, MNI6_LOCAL_SRCID ) , |
|---|
| 879 | IntTab( 0, IOX_MNIC_INI_ID ) ); |
|---|
| 880 | maptab_iox.srcid_map( IntTab( 0, MNI7_LOCAL_SRCID ) , |
|---|
| 881 | IntTab( 0, IOX_MNIC_INI_ID ) ); |
|---|
| 882 | |
|---|
| 883 | if ( cluster_iob0 != cluster_iob1 ) |
|---|
| 884 | { |
|---|
| 885 | maptab_iox.srcid_map( IntTab( 0, IOX_IOB1_INI_ID ) , |
|---|
| 886 | IntTab( 0, IOX_IOB1_INI_ID ) ); |
|---|
| 887 | } |
|---|
| 888 | |
|---|
| 889 | std::cout << "IOX network " << maptab_iox << std::endl; |
|---|
| 890 | |
|---|
| 891 | //////////////////// |
|---|
| 892 | // Signals |
|---|
| 893 | /////////////////// |
|---|
| 894 | |
|---|
| 895 | sc_clock signal_clk("clk"); |
|---|
| 896 | sc_signal<bool> signal_resetn("resetn"); |
|---|
| 897 | |
|---|
| 898 | sc_signal<bool> signal_irq_false; |
|---|
| 899 | sc_signal<bool> signal_irq_disk; |
|---|
| 900 | sc_signal<bool> signal_irq_mtty_rx[NB_TXT_CHANNELS]; |
|---|
| 901 | sc_signal<bool> signal_irq_mtty_tx[NB_TXT_CHANNELS]; |
|---|
| 902 | sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS]; |
|---|
| 903 | sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS]; |
|---|
| 904 | |
|---|
| 905 | // VCI signals for IOX network |
|---|
| 906 | VciSignals<vci_param_ext> signal_vci_ini_iob0("signal_vci_ini_iob0"); |
|---|
| 907 | VciSignals<vci_param_ext> signal_vci_ini_iob1("signal_vci_ini_iob1"); |
|---|
| 908 | VciSignals<vci_param_ext> signal_vci_ini_disk("signal_vci_ini_disk"); |
|---|
| 909 | VciSignals<vci_param_ext> signal_vci_ini_iopi("signal_vci_ini_iopi"); |
|---|
| 910 | VciSignals<vci_param_ext> signal_vci_ini_mnic("signal_vci_ini_mnic"); |
|---|
| 911 | |
|---|
| 912 | VciSignals<vci_param_ext> signal_vci_tgt_iob0("signal_vci_tgt_iob0"); |
|---|
| 913 | VciSignals<vci_param_ext> signal_vci_tgt_iob1("signal_vci_tgt_iob1"); |
|---|
| 914 | VciSignals<vci_param_ext> signal_vci_tgt_mtty("signal_vci_tgt_mtty"); |
|---|
| 915 | VciSignals<vci_param_ext> signal_vci_tgt_fbuf("signal_vci_tgt_fbuf"); |
|---|
| 916 | VciSignals<vci_param_ext> signal_vci_tgt_mnic("signal_vci_tgt_mnic"); |
|---|
| 917 | VciSignals<vci_param_ext> signal_vci_tgt_brom("signal_vci_tgt_brom"); |
|---|
| 918 | VciSignals<vci_param_ext> signal_vci_tgt_disk("signal_vci_tgt_disk"); |
|---|
| 919 | VciSignals<vci_param_ext> signal_vci_tgt_iopi("signal_vci_tgt_iopi"); |
|---|
| 920 | |
|---|
| 921 | // Horizontal inter-clusters INT_CMD DSPIN |
|---|
| 922 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_cmd_h_inc = |
|---|
| 923 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_h_inc", XMAX-1, YMAX); |
|---|
| 924 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_cmd_h_dec = |
|---|
| 925 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_h_dec", XMAX-1, YMAX); |
|---|
| 926 | |
|---|
| 927 | // Horizontal inter-clusters INT_RSP DSPIN |
|---|
| 928 | DspinSignals<dspin_int_rsp_width>** signal_dspin_int_rsp_h_inc = |
|---|
| 929 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_h_inc", XMAX-1, YMAX); |
|---|
| 930 | DspinSignals<dspin_int_rsp_width>** signal_dspin_int_rsp_h_dec = |
|---|
| 931 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_h_dec", XMAX-1, YMAX); |
|---|
| 932 | |
|---|
| 933 | // Horizontal inter-clusters INT_M2P DSPIN |
|---|
| 934 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_m2p_h_inc = |
|---|
| 935 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_m2p_h_inc", XMAX-1, YMAX); |
|---|
| 936 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_m2p_h_dec = |
|---|
| 937 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_m2p_h_dec", XMAX-1, YMAX); |
|---|
| 938 | |
|---|
| 939 | // Horizontal inter-clusters INT_P2M DSPIN |
|---|
| 940 | DspinSignals<dspin_int_rsp_width>** signal_dspin_int_p2m_h_inc = |
|---|
| 941 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_p2m_h_inc", XMAX-1, YMAX); |
|---|
| 942 | DspinSignals<dspin_int_rsp_width>** signal_dspin_int_p2m_h_dec = |
|---|
| 943 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_p2m_h_dec", XMAX-1, YMAX); |
|---|
| 944 | |
|---|
| 945 | // Horizontal inter-clusters INT_CLA DSPIN |
|---|
| 946 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_cla_h_inc = |
|---|
| 947 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cla_h_inc", XMAX-1, YMAX); |
|---|
| 948 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_cla_h_dec = |
|---|
| 949 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cla_h_dec", XMAX-1, YMAX); |
|---|
| 950 | |
|---|
| 951 | |
|---|
| 952 | // Vertical inter-clusters INT_CMD DSPIN |
|---|
| 953 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_cmd_v_inc = |
|---|
| 954 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_v_inc", XMAX, YMAX-1); |
|---|
| 955 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_cmd_v_dec = |
|---|
| 956 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_v_dec", XMAX, YMAX-1); |
|---|
| 957 | |
|---|
| 958 | // Vertical inter-clusters INT_RSP DSPIN |
|---|
| 959 | DspinSignals<dspin_int_rsp_width>** signal_dspin_int_rsp_v_inc = |
|---|
| 960 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_v_inc", XMAX, YMAX-1); |
|---|
| 961 | DspinSignals<dspin_int_rsp_width>** signal_dspin_int_rsp_v_dec = |
|---|
| 962 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_v_dec", XMAX, YMAX-1); |
|---|
| 963 | |
|---|
| 964 | // Vertical inter-clusters INT_M2P DSPIN |
|---|
| 965 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_m2p_v_inc = |
|---|
| 966 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_m2p_v_inc", XMAX, YMAX-1); |
|---|
| 967 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_m2p_v_dec = |
|---|
| 968 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_m2p_v_dec", XMAX, YMAX-1); |
|---|
| 969 | |
|---|
| 970 | // Vertical inter-clusters INT_P2M DSPIN |
|---|
| 971 | DspinSignals<dspin_int_rsp_width>** signal_dspin_int_p2m_v_inc = |
|---|
| 972 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_p2m_v_inc", XMAX, YMAX-1); |
|---|
| 973 | DspinSignals<dspin_int_rsp_width>** signal_dspin_int_p2m_v_dec = |
|---|
| 974 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_p2m_v_dec", XMAX, YMAX-1); |
|---|
| 975 | |
|---|
| 976 | // Vertical inter-clusters INT_CLA DSPIN |
|---|
| 977 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_cla_v_inc = |
|---|
| 978 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cla_v_inc", XMAX, YMAX-1); |
|---|
| 979 | DspinSignals<dspin_int_cmd_width>** signal_dspin_int_cla_v_dec = |
|---|
| 980 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cla_v_dec", XMAX, YMAX-1); |
|---|
| 981 | |
|---|
| 982 | |
|---|
| 983 | // Mesh boundaries INT_CMD DSPIN |
|---|
| 984 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_false_int_cmd_in = |
|---|
| 985 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cmd_in", XMAX, YMAX, 4); |
|---|
| 986 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_false_int_cmd_out = |
|---|
| 987 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cmd_out", XMAX, YMAX, 4); |
|---|
| 988 | |
|---|
| 989 | // Mesh boundaries INT_RSP DSPIN |
|---|
| 990 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_false_int_rsp_in = |
|---|
| 991 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_rsp_in", XMAX, YMAX, 4); |
|---|
| 992 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_false_int_rsp_out = |
|---|
| 993 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_rsp_out", XMAX, YMAX, 4); |
|---|
| 994 | |
|---|
| 995 | // Mesh boundaries INT_M2P DSPIN |
|---|
| 996 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_false_int_m2p_in = |
|---|
| 997 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_m2p_in", XMAX, YMAX, 4); |
|---|
| 998 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_false_int_m2p_out = |
|---|
| 999 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_m2P_out", XMAX, YMAX, 4); |
|---|
| 1000 | |
|---|
| 1001 | // Mesh boundaries INT_P2M DSPIN |
|---|
| 1002 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_false_int_p2m_in = |
|---|
| 1003 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_p2m_in", XMAX, YMAX, 4); |
|---|
| 1004 | DspinSignals<dspin_int_rsp_width>*** signal_dspin_false_int_p2m_out = |
|---|
| 1005 | alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_p2m_out", XMAX, YMAX, 4); |
|---|
| 1006 | |
|---|
| 1007 | // Mesh boundaries INT_CLA DSPIN |
|---|
| 1008 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_false_int_cla_in = |
|---|
| 1009 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cla_in", XMAX, YMAX, 4); |
|---|
| 1010 | DspinSignals<dspin_int_cmd_width>*** signal_dspin_false_int_cla_out = |
|---|
| 1011 | alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cla_out", XMAX, YMAX, 4); |
|---|
| 1012 | |
|---|
| 1013 | |
|---|
| 1014 | // Horizontal inter-clusters RAM_CMD DSPIN |
|---|
| 1015 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_inc = |
|---|
| 1016 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_h_inc", XMAX-1, YMAX); |
|---|
| 1017 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_dec = |
|---|
| 1018 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_h_dec", XMAX-1, YMAX); |
|---|
| 1019 | |
|---|
| 1020 | // Horizontal inter-clusters RAM_RSP DSPIN |
|---|
| 1021 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_inc = |
|---|
| 1022 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_h_inc", XMAX-1, YMAX); |
|---|
| 1023 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_dec = |
|---|
| 1024 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_h_dec", XMAX-1, YMAX); |
|---|
| 1025 | |
|---|
| 1026 | // Vertical inter-clusters RAM_CMD DSPIN |
|---|
| 1027 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_inc = |
|---|
| 1028 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_v_inc", XMAX, YMAX-1); |
|---|
| 1029 | DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_dec = |
|---|
| 1030 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_v_dec", XMAX, YMAX-1); |
|---|
| 1031 | |
|---|
| 1032 | // Vertical inter-clusters RAM_RSP DSPIN |
|---|
| 1033 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_inc = |
|---|
| 1034 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_v_inc", XMAX, YMAX-1); |
|---|
| 1035 | DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_dec = |
|---|
| 1036 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_v_dec", XMAX, YMAX-1); |
|---|
| 1037 | |
|---|
| 1038 | // Mesh boundaries RAM_CMD DSPIN |
|---|
| 1039 | DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_in = |
|---|
| 1040 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_false_ram_cmd_in", XMAX, YMAX, 4); |
|---|
| 1041 | DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_out = |
|---|
| 1042 | alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_false_ram_cmd_out", XMAX, YMAX, 4); |
|---|
| 1043 | |
|---|
| 1044 | // Mesh boundaries RAM_RSP DSPIN |
|---|
| 1045 | DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_in = |
|---|
| 1046 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_false_ram_rsp_in", XMAX, YMAX, 4); |
|---|
| 1047 | DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_out = |
|---|
| 1048 | alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_false_ram_rsp_out", XMAX, YMAX, 4); |
|---|
| 1049 | |
|---|
| 1050 | // SD card signals |
|---|
| 1051 | sc_signal<bool> signal_sdc_clk; |
|---|
| 1052 | sc_signal<bool> signal_sdc_cmd_enable_to_card; |
|---|
| 1053 | sc_signal<bool> signal_sdc_cmd_value_to_card; |
|---|
| 1054 | sc_signal<bool> signal_sdc_dat_enable_to_card; |
|---|
| 1055 | sc_signal<bool> signal_sdc_dat_value_to_card[4]; |
|---|
| 1056 | sc_signal<bool> signal_sdc_cmd_enable_from_card; |
|---|
| 1057 | sc_signal<bool> signal_sdc_cmd_value_from_card; |
|---|
| 1058 | sc_signal<bool> signal_sdc_dat_enable_from_card; |
|---|
| 1059 | sc_signal<bool> signal_sdc_dat_value_from_card[4]; |
|---|
| 1060 | |
|---|
| 1061 | //////////////////////////////////////////////// |
|---|
| 1062 | // Load the preloader code in the ROM |
|---|
| 1063 | //////////////////////////////////////////////// |
|---|
| 1064 | |
|---|
| 1065 | soclib::common::Loader loader(soft_name); |
|---|
| 1066 | |
|---|
| 1067 | typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss; |
|---|
| 1068 | proc_iss::set_loader(loader); |
|---|
| 1069 | |
|---|
| 1070 | //////////////////////////////////////// |
|---|
| 1071 | // Instanciated Hardware Components |
|---|
| 1072 | //////////////////////////////////////// |
|---|
| 1073 | |
|---|
| 1074 | std::cout << std::endl << "External Bus and Peripherals" << std::endl << std::endl; |
|---|
| 1075 | |
|---|
| 1076 | const size_t nb_iox_initiators = (cluster_iob0 != cluster_iob1) ? 5 : 4; |
|---|
| 1077 | const size_t nb_iox_targets = (cluster_iob0 != cluster_iob1) ? 8 : 7; |
|---|
| 1078 | |
|---|
| 1079 | // IOX network |
|---|
| 1080 | VciIoxNetwork<vci_param_ext>* iox_network; |
|---|
| 1081 | iox_network = new VciIoxNetwork<vci_param_ext>( "iox_network", |
|---|
| 1082 | maptab_iox, |
|---|
| 1083 | nb_iox_targets, |
|---|
| 1084 | nb_iox_initiators ); |
|---|
| 1085 | // boot ROM |
|---|
| 1086 | VciSimpleRom<vci_param_ext>* brom; |
|---|
| 1087 | brom = new VciSimpleRom<vci_param_ext>( "brom", |
|---|
| 1088 | IntTab(0, IOX_BROM_TGT_ID), |
|---|
| 1089 | maptab_iox, |
|---|
| 1090 | loader ); |
|---|
| 1091 | // Ethernet Controller |
|---|
| 1092 | VciMasterNic<vci_param_ext>* mnic; |
|---|
| 1093 | mnic = new VciMasterNic<vci_param_ext>( "mnic", |
|---|
| 1094 | maptab_iox, |
|---|
| 1095 | IntTab(0, MNI0_LOCAL_SRCID), |
|---|
| 1096 | IntTab(0, IOX_MNIC_TGT_ID), |
|---|
| 1097 | NB_NIC_CHANNELS, |
|---|
| 1098 | 6, // burst order |
|---|
| 1099 | 1, // NIC_MODE_SYNTHESIS |
|---|
| 1100 | 12); // INTER_FRAME_GAP |
|---|
| 1101 | |
|---|
| 1102 | // Frame Buffer |
|---|
| 1103 | VciFrameBuffer<vci_param_ext>* fbuf; |
|---|
| 1104 | fbuf = new VciFrameBuffer<vci_param_ext>( "fbuf", |
|---|
| 1105 | IntTab(0, IOX_FBUF_TGT_ID), |
|---|
| 1106 | maptab_iox, |
|---|
| 1107 | FBUF_X_SIZE, FBUF_Y_SIZE ); |
|---|
| 1108 | |
|---|
| 1109 | // Disk |
|---|
| 1110 | std::vector<std::string> filenames; |
|---|
| 1111 | filenames.push_back(disk_name); // one single disk |
|---|
| 1112 | |
|---|
| 1113 | #if ( USE_IOC_HBA ) |
|---|
| 1114 | |
|---|
| 1115 | VciMultiAhci<vci_param_ext>* disk; |
|---|
| 1116 | disk = new VciMultiAhci<vci_param_ext>( "disk", |
|---|
| 1117 | maptab_iox, |
|---|
| 1118 | IntTab(0, DISK_LOCAL_SRCID), |
|---|
| 1119 | IntTab(0, IOX_DISK_TGT_ID), |
|---|
| 1120 | filenames, |
|---|
| 1121 | 512, // block size |
|---|
| 1122 | 64, // burst size (bytes) |
|---|
| 1123 | 0 ); // disk latency |
|---|
| 1124 | #elif ( USE_IOC_BDV ) |
|---|
| 1125 | |
|---|
| 1126 | VciBlockDeviceTsar<vci_param_ext>* disk; |
|---|
| 1127 | disk = new VciBlockDeviceTsar<vci_param_ext>( "disk", |
|---|
| 1128 | maptab_iox, |
|---|
| 1129 | IntTab(0, DISK_LOCAL_SRCID), |
|---|
| 1130 | IntTab(0, IOX_DISK_TGT_ID), |
|---|
| 1131 | disk_name, |
|---|
| 1132 | 512, // block size |
|---|
| 1133 | 64, // burst size (bytes) |
|---|
| 1134 | 0 ); // disk latency |
|---|
| 1135 | #elif ( USE_IOC_SDC ) |
|---|
| 1136 | |
|---|
| 1137 | VciAhciSdc<vci_param_ext>* disk; |
|---|
| 1138 | disk = new VciAhciSdc<vci_param_ext>( "disk", |
|---|
| 1139 | maptab_iox, |
|---|
| 1140 | IntTab(0, DISK_LOCAL_SRCID), |
|---|
| 1141 | IntTab(0, IOX_DISK_TGT_ID), |
|---|
| 1142 | 64 ); // burst size (bytes) |
|---|
| 1143 | SdCard* card; |
|---|
| 1144 | card = new SdCard( "card", |
|---|
| 1145 | disk_name, |
|---|
| 1146 | 10, // RX one block latency |
|---|
| 1147 | 10 ); // TX one block latency |
|---|
| 1148 | #endif |
|---|
| 1149 | |
|---|
| 1150 | // TTY controller |
|---|
| 1151 | std::vector<std::string> vect_names; |
|---|
| 1152 | for( size_t tid = 0 ; tid < NB_TXT_CHANNELS ; tid++ ) |
|---|
| 1153 | { |
|---|
| 1154 | std::ostringstream term_name; |
|---|
| 1155 | term_name << "term" << tid; |
|---|
| 1156 | |
|---|
| 1157 | vect_names.push_back(term_name.str().c_str()); |
|---|
| 1158 | } |
|---|
| 1159 | VciTtyTsar<vci_param_ext>* mtty; |
|---|
| 1160 | mtty = new VciTtyTsar<vci_param_ext>( "mtty", |
|---|
| 1161 | IntTab(0, IOX_MTTY_TGT_ID), |
|---|
| 1162 | maptab_iox, |
|---|
| 1163 | vect_names); |
|---|
| 1164 | |
|---|
| 1165 | // IOPIC |
|---|
| 1166 | VciIopic<vci_param_ext>* iopi; |
|---|
| 1167 | iopi = new VciIopic<vci_param_ext>( "iopi", |
|---|
| 1168 | maptab_iox, |
|---|
| 1169 | IntTab(0, IOPI_LOCAL_SRCID), |
|---|
| 1170 | IntTab(0, IOX_IOPI_TGT_ID), |
|---|
| 1171 | 32 ); // number of input HWI |
|---|
| 1172 | // Clusters |
|---|
| 1173 | TsarIobCluster<vci_param_int, |
|---|
| 1174 | vci_param_ext, |
|---|
| 1175 | dspin_int_cmd_width, |
|---|
| 1176 | dspin_int_rsp_width, |
|---|
| 1177 | dspin_ram_cmd_width, |
|---|
| 1178 | dspin_ram_rsp_width>* clusters[XMAX][YMAX]; |
|---|
| 1179 | |
|---|
| 1180 | unsigned int coproc_type = 0; |
|---|
| 1181 | |
|---|
| 1182 | #if USE_OPENMP |
|---|
| 1183 | #pragma omp parallel |
|---|
| 1184 | { |
|---|
| 1185 | #pragma omp for |
|---|
| 1186 | #endif |
|---|
| 1187 | for(size_t i = 0; i < (XMAX * YMAX); i++) |
|---|
| 1188 | { |
|---|
| 1189 | size_t x = i / YMAX; |
|---|
| 1190 | size_t y = i % YMAX; |
|---|
| 1191 | |
|---|
| 1192 | #if USE_OPENMP |
|---|
| 1193 | #pragma omp critical |
|---|
| 1194 | { |
|---|
| 1195 | #endif |
|---|
| 1196 | std::cout << std::endl; |
|---|
| 1197 | std::cout << "Cluster_" << std::dec << x << "_" << y << std::endl; |
|---|
| 1198 | std::cout << std::endl; |
|---|
| 1199 | |
|---|
| 1200 | const bool is_iob0 = (cluster(x,y) == cluster_iob0); |
|---|
| 1201 | const bool is_iob1 = (cluster(x,y) == cluster_iob1); |
|---|
| 1202 | const bool is_io_cluster = is_iob0 || is_iob1; |
|---|
| 1203 | |
|---|
| 1204 | const int iox_iob_ini_id = is_iob0 ? |
|---|
| 1205 | IOX_IOB0_INI_ID : |
|---|
| 1206 | IOX_IOB1_INI_ID ; |
|---|
| 1207 | const int iox_iob_tgt_id = is_iob0 ? |
|---|
| 1208 | IOX_IOB0_TGT_ID : |
|---|
| 1209 | IOX_IOB1_TGT_ID ; |
|---|
| 1210 | |
|---|
| 1211 | |
|---|
| 1212 | std::ostringstream sc; |
|---|
| 1213 | sc << "cluster_" << x << "_" << y; |
|---|
| 1214 | clusters[x][y] = new TsarIobCluster<vci_param_int, |
|---|
| 1215 | vci_param_ext, |
|---|
| 1216 | dspin_int_cmd_width, |
|---|
| 1217 | dspin_int_rsp_width, |
|---|
| 1218 | dspin_ram_cmd_width, |
|---|
| 1219 | dspin_ram_rsp_width> |
|---|
| 1220 | ( |
|---|
| 1221 | sc.str().c_str(), |
|---|
| 1222 | NB_PROCS_MAX, |
|---|
| 1223 | x, |
|---|
| 1224 | y, |
|---|
| 1225 | XMAX, |
|---|
| 1226 | YMAX, |
|---|
| 1227 | |
|---|
| 1228 | maptab_int, |
|---|
| 1229 | maptab_ram, |
|---|
| 1230 | maptab_iox, |
|---|
| 1231 | |
|---|
| 1232 | x_width, |
|---|
| 1233 | y_width, |
|---|
| 1234 | vci_srcid_width - x_width - y_width, // l_id width, |
|---|
| 1235 | p_width, |
|---|
| 1236 | |
|---|
| 1237 | INT_MEMC_TGT_ID, |
|---|
| 1238 | INT_XICU_TGT_ID, |
|---|
| 1239 | INT_MDMA_TGT_ID, |
|---|
| 1240 | INT_IOBX_TGT_ID, |
|---|
| 1241 | |
|---|
| 1242 | INT_PROC_INI_ID, |
|---|
| 1243 | INT_MDMA_INI_ID, |
|---|
| 1244 | INT_IOBX_INI_ID, |
|---|
| 1245 | |
|---|
| 1246 | RAM_XRAM_TGT_ID, |
|---|
| 1247 | |
|---|
| 1248 | RAM_MEMC_INI_ID, |
|---|
| 1249 | RAM_IOBX_INI_ID, |
|---|
| 1250 | |
|---|
| 1251 | is_io_cluster, |
|---|
| 1252 | iox_iob_tgt_id, |
|---|
| 1253 | iox_iob_ini_id, |
|---|
| 1254 | |
|---|
| 1255 | MEMC_WAYS, |
|---|
| 1256 | MEMC_SETS, |
|---|
| 1257 | L1_IWAYS, |
|---|
| 1258 | L1_ISETS, |
|---|
| 1259 | L1_DWAYS, |
|---|
| 1260 | L1_DSETS, |
|---|
| 1261 | XRAM_LATENCY, |
|---|
| 1262 | ICU_NB_HWI, |
|---|
| 1263 | ICU_NB_PTI, |
|---|
| 1264 | ICU_NB_WTI, |
|---|
| 1265 | ICU_NB_OUT, |
|---|
| 1266 | |
|---|
| 1267 | coproc_type, |
|---|
| 1268 | |
|---|
| 1269 | loader, |
|---|
| 1270 | |
|---|
| 1271 | frozen_cycles, |
|---|
| 1272 | debug_ok, |
|---|
| 1273 | debug_from, |
|---|
| 1274 | debug_proc_id, |
|---|
| 1275 | debug_memc_id, |
|---|
| 1276 | debug_iob |
|---|
| 1277 | ); |
|---|
| 1278 | |
|---|
| 1279 | #if USE_OPENMP |
|---|
| 1280 | } // end critical |
|---|
| 1281 | #endif |
|---|
| 1282 | } // end for |
|---|
| 1283 | #if USE_OPENMP |
|---|
| 1284 | } |
|---|
| 1285 | #endif |
|---|
| 1286 | |
|---|
| 1287 | std::cout << std::endl; |
|---|
| 1288 | |
|---|
| 1289 | /////////////////////////////////////////////////////////////////////////////// |
|---|
| 1290 | // Net-list |
|---|
| 1291 | /////////////////////////////////////////////////////////////////////////////// |
|---|
| 1292 | |
|---|
| 1293 | // IOX network connexion |
|---|
| 1294 | iox_network->p_clk (signal_clk); |
|---|
| 1295 | iox_network->p_resetn (signal_resetn); |
|---|
| 1296 | iox_network->p_to_ini[IOX_IOB0_INI_ID] (signal_vci_ini_iob0); |
|---|
| 1297 | iox_network->p_to_ini[IOX_DISK_INI_ID] (signal_vci_ini_disk); |
|---|
| 1298 | iox_network->p_to_ini[IOX_IOPI_INI_ID] (signal_vci_ini_iopi); |
|---|
| 1299 | iox_network->p_to_ini[IOX_MNIC_INI_ID] (signal_vci_ini_mnic); |
|---|
| 1300 | |
|---|
| 1301 | iox_network->p_to_tgt[IOX_IOB0_TGT_ID] (signal_vci_tgt_iob0); |
|---|
| 1302 | iox_network->p_to_tgt[IOX_MTTY_TGT_ID] (signal_vci_tgt_mtty); |
|---|
| 1303 | iox_network->p_to_tgt[IOX_FBUF_TGT_ID] (signal_vci_tgt_fbuf); |
|---|
| 1304 | iox_network->p_to_tgt[IOX_MNIC_TGT_ID] (signal_vci_tgt_mnic); |
|---|
| 1305 | iox_network->p_to_tgt[IOX_BROM_TGT_ID] (signal_vci_tgt_brom); |
|---|
| 1306 | iox_network->p_to_tgt[IOX_DISK_TGT_ID] (signal_vci_tgt_disk); |
|---|
| 1307 | iox_network->p_to_tgt[IOX_IOPI_TGT_ID] (signal_vci_tgt_iopi); |
|---|
| 1308 | |
|---|
| 1309 | if (cluster_iob0 != cluster_iob1) |
|---|
| 1310 | { |
|---|
| 1311 | iox_network->p_to_ini[IOX_IOB1_INI_ID] (signal_vci_ini_iob1); |
|---|
| 1312 | iox_network->p_to_tgt[IOX_IOB1_TGT_ID] (signal_vci_tgt_iob1); |
|---|
| 1313 | } |
|---|
| 1314 | |
|---|
| 1315 | // DISK connexion |
|---|
| 1316 | |
|---|
| 1317 | #if ( USE_IOC_HBA ) |
|---|
| 1318 | |
|---|
| 1319 | disk->p_clk (signal_clk); |
|---|
| 1320 | disk->p_resetn (signal_resetn); |
|---|
| 1321 | disk->p_vci_target (signal_vci_tgt_disk); |
|---|
| 1322 | disk->p_vci_initiator (signal_vci_ini_disk); |
|---|
| 1323 | disk->p_channel_irq[0] (signal_irq_disk); |
|---|
| 1324 | |
|---|
| 1325 | #elif ( USE_IOC_BDV ) |
|---|
| 1326 | |
|---|
| 1327 | disk->p_clk (signal_clk); |
|---|
| 1328 | disk->p_resetn (signal_resetn); |
|---|
| 1329 | disk->p_vci_target (signal_vci_tgt_disk); |
|---|
| 1330 | disk->p_vci_initiator (signal_vci_ini_disk); |
|---|
| 1331 | disk->p_irq (signal_irq_disk); |
|---|
| 1332 | |
|---|
| 1333 | #elif ( USE_IOC_SDC ) |
|---|
| 1334 | |
|---|
| 1335 | disk->p_clk (signal_clk); |
|---|
| 1336 | disk->p_resetn (signal_resetn); |
|---|
| 1337 | disk->p_vci_target (signal_vci_tgt_disk); |
|---|
| 1338 | disk->p_vci_initiator (signal_vci_ini_disk); |
|---|
| 1339 | disk->p_irq (signal_irq_disk); |
|---|
| 1340 | |
|---|
| 1341 | disk->p_sdc_clk (signal_sdc_clk); |
|---|
| 1342 | disk->p_sdc_cmd_enable_out (signal_sdc_cmd_enable_to_card); |
|---|
| 1343 | disk->p_sdc_cmd_value_out (signal_sdc_cmd_value_to_card); |
|---|
| 1344 | disk->p_sdc_cmd_enable_in (signal_sdc_cmd_enable_from_card); |
|---|
| 1345 | disk->p_sdc_cmd_value_in (signal_sdc_cmd_value_from_card); |
|---|
| 1346 | disk->p_sdc_dat_enable_out (signal_sdc_dat_enable_to_card); |
|---|
| 1347 | disk->p_sdc_dat_value_out[0] (signal_sdc_dat_value_to_card[0]); |
|---|
| 1348 | disk->p_sdc_dat_value_out[1] (signal_sdc_dat_value_to_card[1]); |
|---|
| 1349 | disk->p_sdc_dat_value_out[2] (signal_sdc_dat_value_to_card[2]); |
|---|
| 1350 | disk->p_sdc_dat_value_out[3] (signal_sdc_dat_value_to_card[3]); |
|---|
| 1351 | disk->p_sdc_dat_enable_in (signal_sdc_dat_enable_from_card); |
|---|
| 1352 | disk->p_sdc_dat_value_in[0] (signal_sdc_dat_value_from_card[0]); |
|---|
| 1353 | disk->p_sdc_dat_value_in[1] (signal_sdc_dat_value_from_card[1]); |
|---|
| 1354 | disk->p_sdc_dat_value_in[2] (signal_sdc_dat_value_from_card[2]); |
|---|
| 1355 | disk->p_sdc_dat_value_in[3] (signal_sdc_dat_value_from_card[3]); |
|---|
| 1356 | |
|---|
| 1357 | card->p_clk (signal_clk); |
|---|
| 1358 | card->p_resetn (signal_resetn); |
|---|
| 1359 | |
|---|
| 1360 | card->p_sdc_clk (signal_sdc_clk); |
|---|
| 1361 | card->p_sdc_cmd_enable_out (signal_sdc_cmd_enable_from_card); |
|---|
| 1362 | card->p_sdc_cmd_value_out (signal_sdc_cmd_value_from_card); |
|---|
| 1363 | card->p_sdc_cmd_enable_in (signal_sdc_cmd_enable_to_card); |
|---|
| 1364 | card->p_sdc_cmd_value_in (signal_sdc_cmd_value_to_card); |
|---|
| 1365 | card->p_sdc_dat_enable_out (signal_sdc_dat_enable_from_card); |
|---|
| 1366 | card->p_sdc_dat_value_out[0] (signal_sdc_dat_value_from_card[0]); |
|---|
| 1367 | card->p_sdc_dat_value_out[1] (signal_sdc_dat_value_from_card[1]); |
|---|
| 1368 | card->p_sdc_dat_value_out[2] (signal_sdc_dat_value_from_card[2]); |
|---|
| 1369 | card->p_sdc_dat_value_out[3] (signal_sdc_dat_value_from_card[3]); |
|---|
| 1370 | card->p_sdc_dat_enable_in (signal_sdc_dat_enable_to_card); |
|---|
| 1371 | card->p_sdc_dat_value_in[0] (signal_sdc_dat_value_to_card[0]); |
|---|
| 1372 | card->p_sdc_dat_value_in[1] (signal_sdc_dat_value_to_card[1]); |
|---|
| 1373 | card->p_sdc_dat_value_in[2] (signal_sdc_dat_value_to_card[2]); |
|---|
| 1374 | card->p_sdc_dat_value_in[3] (signal_sdc_dat_value_to_card[3]); |
|---|
| 1375 | |
|---|
| 1376 | #endif |
|---|
| 1377 | |
|---|
| 1378 | std::cout << " - DISK connected" << std::endl; |
|---|
| 1379 | |
|---|
| 1380 | // FBUF connexion |
|---|
| 1381 | fbuf->p_clk (signal_clk); |
|---|
| 1382 | fbuf->p_resetn (signal_resetn); |
|---|
| 1383 | fbuf->p_vci (signal_vci_tgt_fbuf); |
|---|
| 1384 | |
|---|
| 1385 | std::cout << " - FBUF connected" << std::endl; |
|---|
| 1386 | |
|---|
| 1387 | // MNIC connexion |
|---|
| 1388 | mnic->p_clk (signal_clk); |
|---|
| 1389 | mnic->p_resetn (signal_resetn); |
|---|
| 1390 | mnic->p_vci_tgt (signal_vci_tgt_mnic); |
|---|
| 1391 | mnic->p_vci_ini (signal_vci_ini_mnic); |
|---|
| 1392 | for ( size_t i=0 ; i<NB_NIC_CHANNELS ; i++ ) |
|---|
| 1393 | { |
|---|
| 1394 | mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]); |
|---|
| 1395 | mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]); |
|---|
| 1396 | } |
|---|
| 1397 | |
|---|
| 1398 | std::cout << " - MNIC connected" << std::endl; |
|---|
| 1399 | |
|---|
| 1400 | // BROM connexion |
|---|
| 1401 | brom->p_clk (signal_clk); |
|---|
| 1402 | brom->p_resetn (signal_resetn); |
|---|
| 1403 | brom->p_vci (signal_vci_tgt_brom); |
|---|
| 1404 | |
|---|
| 1405 | std::cout << " - BROM connected" << std::endl; |
|---|
| 1406 | |
|---|
| 1407 | // MTTY connexion |
|---|
| 1408 | mtty->p_clk (signal_clk); |
|---|
| 1409 | mtty->p_resetn (signal_resetn); |
|---|
| 1410 | mtty->p_vci (signal_vci_tgt_mtty); |
|---|
| 1411 | for ( size_t i=0 ; i<NB_TXT_CHANNELS ; i++ ) |
|---|
| 1412 | { |
|---|
| 1413 | mtty->p_irq_rx[i] (signal_irq_mtty_rx[i]); |
|---|
| 1414 | mtty->p_irq_tx[i] (signal_irq_mtty_tx[i]); |
|---|
| 1415 | } |
|---|
| 1416 | std::cout << " - MTTY connected" << std::endl; |
|---|
| 1417 | |
|---|
| 1418 | // IOPI connexion |
|---|
| 1419 | iopi->p_clk (signal_clk); |
|---|
| 1420 | iopi->p_resetn (signal_resetn); |
|---|
| 1421 | iopi->p_vci_target (signal_vci_tgt_iopi); |
|---|
| 1422 | iopi->p_vci_initiator (signal_vci_ini_iopi); |
|---|
| 1423 | for ( size_t i=0 ; i<32 ; i++) |
|---|
| 1424 | { |
|---|
| 1425 | if (i < NB_NIC_CHANNELS) iopi->p_hwi[i] (signal_irq_mnic_rx[i]); |
|---|
| 1426 | else if(i < 4 ) iopi->p_hwi[i] (signal_irq_false); |
|---|
| 1427 | else if(i < 4+NB_NIC_CHANNELS) iopi->p_hwi[i] (signal_irq_mnic_tx[i-4]); |
|---|
| 1428 | else if(i < 12) iopi->p_hwi[i] (signal_irq_false); |
|---|
| 1429 | else if(i < 13) iopi->p_hwi[i] (signal_irq_disk); |
|---|
| 1430 | else if(i < 16) iopi->p_hwi[i] (signal_irq_false); |
|---|
| 1431 | else if(i < 16+NB_TXT_CHANNELS) iopi->p_hwi[i] (signal_irq_mtty_rx[i-16]); |
|---|
| 1432 | else if(i < 24) iopi->p_hwi[i] (signal_irq_false); |
|---|
| 1433 | else if(i < 24+NB_TXT_CHANNELS) iopi->p_hwi[i] (signal_irq_mtty_tx[i-24]); |
|---|
| 1434 | else iopi->p_hwi[i] (signal_irq_false); |
|---|
| 1435 | } |
|---|
| 1436 | |
|---|
| 1437 | std::cout << " - IOPIC connected" << std::endl; |
|---|
| 1438 | |
|---|
| 1439 | |
|---|
| 1440 | // IOB0 cluster connexion to IOX network |
|---|
| 1441 | (*clusters[0][0]->p_vci_iob_iox_ini) (signal_vci_ini_iob0); |
|---|
| 1442 | (*clusters[0][0]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob0); |
|---|
| 1443 | |
|---|
| 1444 | // IOB1 cluster connexion to IOX network |
|---|
| 1445 | // (only when there is more than 1 cluster) |
|---|
| 1446 | if ( cluster_iob0 != cluster_iob1 ) |
|---|
| 1447 | { |
|---|
| 1448 | (*clusters[XMAX-1][YMAX-1]->p_vci_iob_iox_ini) (signal_vci_ini_iob1); |
|---|
| 1449 | (*clusters[XMAX-1][YMAX-1]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob1); |
|---|
| 1450 | } |
|---|
| 1451 | |
|---|
| 1452 | // All clusters Clock & RESET connexions |
|---|
| 1453 | for ( size_t x = 0; x < (XMAX); x++ ) |
|---|
| 1454 | { |
|---|
| 1455 | for (size_t y = 0; y < YMAX; y++) |
|---|
| 1456 | { |
|---|
| 1457 | clusters[x][y]->p_clk (signal_clk); |
|---|
| 1458 | clusters[x][y]->p_resetn (signal_resetn); |
|---|
| 1459 | } |
|---|
| 1460 | } |
|---|
| 1461 | |
|---|
| 1462 | // Inter Clusters horizontal connections |
|---|
| 1463 | if (XMAX > 1) |
|---|
| 1464 | { |
|---|
| 1465 | for (size_t x = 0; x < (XMAX-1); x++) |
|---|
| 1466 | { |
|---|
| 1467 | for (size_t y = 0; y < YMAX; y++) |
|---|
| 1468 | { |
|---|
| 1469 | clusters[x][y]->p_dspin_int_cmd_out[EAST] (signal_dspin_int_cmd_h_inc[x][y]); |
|---|
| 1470 | clusters[x+1][y]->p_dspin_int_cmd_in[WEST] (signal_dspin_int_cmd_h_inc[x][y]); |
|---|
| 1471 | clusters[x][y]->p_dspin_int_cmd_in[EAST] (signal_dspin_int_cmd_h_dec[x][y]); |
|---|
| 1472 | clusters[x+1][y]->p_dspin_int_cmd_out[WEST] (signal_dspin_int_cmd_h_dec[x][y]); |
|---|
| 1473 | |
|---|
| 1474 | clusters[x][y]->p_dspin_int_rsp_out[EAST] (signal_dspin_int_rsp_h_inc[x][y]); |
|---|
| 1475 | clusters[x+1][y]->p_dspin_int_rsp_in[WEST] (signal_dspin_int_rsp_h_inc[x][y]); |
|---|
| 1476 | clusters[x][y]->p_dspin_int_rsp_in[EAST] (signal_dspin_int_rsp_h_dec[x][y]); |
|---|
| 1477 | clusters[x+1][y]->p_dspin_int_rsp_out[WEST] (signal_dspin_int_rsp_h_dec[x][y]); |
|---|
| 1478 | |
|---|
| 1479 | clusters[x][y]->p_dspin_int_m2p_out[EAST] (signal_dspin_int_m2p_h_inc[x][y]); |
|---|
| 1480 | clusters[x+1][y]->p_dspin_int_m2p_in[WEST] (signal_dspin_int_m2p_h_inc[x][y]); |
|---|
| 1481 | clusters[x][y]->p_dspin_int_m2p_in[EAST] (signal_dspin_int_m2p_h_dec[x][y]); |
|---|
| 1482 | clusters[x+1][y]->p_dspin_int_m2p_out[WEST] (signal_dspin_int_m2p_h_dec[x][y]); |
|---|
| 1483 | |
|---|
| 1484 | clusters[x][y]->p_dspin_int_p2m_out[EAST] (signal_dspin_int_p2m_h_inc[x][y]); |
|---|
| 1485 | clusters[x+1][y]->p_dspin_int_p2m_in[WEST] (signal_dspin_int_p2m_h_inc[x][y]); |
|---|
| 1486 | clusters[x][y]->p_dspin_int_p2m_in[EAST] (signal_dspin_int_p2m_h_dec[x][y]); |
|---|
| 1487 | clusters[x+1][y]->p_dspin_int_p2m_out[WEST] (signal_dspin_int_p2m_h_dec[x][y]); |
|---|
| 1488 | |
|---|
| 1489 | clusters[x][y]->p_dspin_int_cla_out[EAST] (signal_dspin_int_cla_h_inc[x][y]); |
|---|
| 1490 | clusters[x+1][y]->p_dspin_int_cla_in[WEST] (signal_dspin_int_cla_h_inc[x][y]); |
|---|
| 1491 | clusters[x][y]->p_dspin_int_cla_in[EAST] (signal_dspin_int_cla_h_dec[x][y]); |
|---|
| 1492 | clusters[x+1][y]->p_dspin_int_cla_out[WEST] (signal_dspin_int_cla_h_dec[x][y]); |
|---|
| 1493 | |
|---|
| 1494 | clusters[x][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_ram_cmd_h_inc[x][y]); |
|---|
| 1495 | clusters[x+1][y]->p_dspin_ram_cmd_in[WEST] (signal_dspin_ram_cmd_h_inc[x][y]); |
|---|
| 1496 | clusters[x][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_ram_cmd_h_dec[x][y]); |
|---|
| 1497 | clusters[x+1][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_ram_cmd_h_dec[x][y]); |
|---|
| 1498 | |
|---|
| 1499 | clusters[x][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_ram_rsp_h_inc[x][y]); |
|---|
| 1500 | clusters[x+1][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_ram_rsp_h_inc[x][y]); |
|---|
| 1501 | clusters[x][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_ram_rsp_h_dec[x][y]); |
|---|
| 1502 | clusters[x+1][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_ram_rsp_h_dec[x][y]); |
|---|
| 1503 | } |
|---|
| 1504 | } |
|---|
| 1505 | } |
|---|
| 1506 | |
|---|
| 1507 | std::cout << std::endl << "Horizontal connections established" << std::endl; |
|---|
| 1508 | |
|---|
| 1509 | // Inter Clusters vertical connections |
|---|
| 1510 | if (YMAX > 1) |
|---|
| 1511 | { |
|---|
| 1512 | for (size_t y = 0; y < (YMAX-1); y++) |
|---|
| 1513 | { |
|---|
| 1514 | for (size_t x = 0; x < XMAX; x++) |
|---|
| 1515 | { |
|---|
| 1516 | clusters[x][y]->p_dspin_int_cmd_out[NORTH] (signal_dspin_int_cmd_v_inc[x][y]); |
|---|
| 1517 | clusters[x][y+1]->p_dspin_int_cmd_in[SOUTH] (signal_dspin_int_cmd_v_inc[x][y]); |
|---|
| 1518 | clusters[x][y]->p_dspin_int_cmd_in[NORTH] (signal_dspin_int_cmd_v_dec[x][y]); |
|---|
| 1519 | clusters[x][y+1]->p_dspin_int_cmd_out[SOUTH] (signal_dspin_int_cmd_v_dec[x][y]); |
|---|
| 1520 | |
|---|
| 1521 | clusters[x][y]->p_dspin_int_rsp_out[NORTH] (signal_dspin_int_rsp_v_inc[x][y]); |
|---|
| 1522 | clusters[x][y+1]->p_dspin_int_rsp_in[SOUTH] (signal_dspin_int_rsp_v_inc[x][y]); |
|---|
| 1523 | clusters[x][y]->p_dspin_int_rsp_in[NORTH] (signal_dspin_int_rsp_v_dec[x][y]); |
|---|
| 1524 | clusters[x][y+1]->p_dspin_int_rsp_out[SOUTH] (signal_dspin_int_rsp_v_dec[x][y]); |
|---|
| 1525 | |
|---|
| 1526 | clusters[x][y]->p_dspin_int_m2p_out[NORTH] (signal_dspin_int_m2p_v_inc[x][y]); |
|---|
| 1527 | clusters[x][y+1]->p_dspin_int_m2p_in[SOUTH] (signal_dspin_int_m2p_v_inc[x][y]); |
|---|
| 1528 | clusters[x][y]->p_dspin_int_m2p_in[NORTH] (signal_dspin_int_m2p_v_dec[x][y]); |
|---|
| 1529 | clusters[x][y+1]->p_dspin_int_m2p_out[SOUTH] (signal_dspin_int_m2p_v_dec[x][y]); |
|---|
| 1530 | |
|---|
| 1531 | clusters[x][y]->p_dspin_int_p2m_out[NORTH] (signal_dspin_int_p2m_v_inc[x][y]); |
|---|
| 1532 | clusters[x][y+1]->p_dspin_int_p2m_in[SOUTH] (signal_dspin_int_p2m_v_inc[x][y]); |
|---|
| 1533 | clusters[x][y]->p_dspin_int_p2m_in[NORTH] (signal_dspin_int_p2m_v_dec[x][y]); |
|---|
| 1534 | clusters[x][y+1]->p_dspin_int_p2m_out[SOUTH] (signal_dspin_int_p2m_v_dec[x][y]); |
|---|
| 1535 | |
|---|
| 1536 | clusters[x][y]->p_dspin_int_cla_out[NORTH] (signal_dspin_int_cla_v_inc[x][y]); |
|---|
| 1537 | clusters[x][y+1]->p_dspin_int_cla_in[SOUTH] (signal_dspin_int_cla_v_inc[x][y]); |
|---|
| 1538 | clusters[x][y]->p_dspin_int_cla_in[NORTH] (signal_dspin_int_cla_v_dec[x][y]); |
|---|
| 1539 | clusters[x][y+1]->p_dspin_int_cla_out[SOUTH] (signal_dspin_int_cla_v_dec[x][y]); |
|---|
| 1540 | |
|---|
| 1541 | clusters[x][y]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_ram_cmd_v_inc[x][y]); |
|---|
| 1542 | clusters[x][y+1]->p_dspin_ram_cmd_in[SOUTH] (signal_dspin_ram_cmd_v_inc[x][y]); |
|---|
| 1543 | clusters[x][y]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_ram_cmd_v_dec[x][y]); |
|---|
| 1544 | clusters[x][y+1]->p_dspin_ram_cmd_out[SOUTH] (signal_dspin_ram_cmd_v_dec[x][y]); |
|---|
| 1545 | |
|---|
| 1546 | clusters[x][y]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_ram_rsp_v_inc[x][y]); |
|---|
| 1547 | clusters[x][y+1]->p_dspin_ram_rsp_in[SOUTH] (signal_dspin_ram_rsp_v_inc[x][y]); |
|---|
| 1548 | clusters[x][y]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_ram_rsp_v_dec[x][y]); |
|---|
| 1549 | clusters[x][y+1]->p_dspin_ram_rsp_out[SOUTH] (signal_dspin_ram_rsp_v_dec[x][y]); |
|---|
| 1550 | } |
|---|
| 1551 | } |
|---|
| 1552 | } |
|---|
| 1553 | |
|---|
| 1554 | std::cout << "Vertical connections established" << std::endl; |
|---|
| 1555 | |
|---|
| 1556 | // East & West boundary cluster connections |
|---|
| 1557 | for (size_t y = 0; y < YMAX; y++) |
|---|
| 1558 | { |
|---|
| 1559 | clusters[0][y]->p_dspin_int_cmd_in[WEST] (signal_dspin_false_int_cmd_in[0][y][WEST]); |
|---|
| 1560 | clusters[0][y]->p_dspin_int_cmd_out[WEST] (signal_dspin_false_int_cmd_out[0][y][WEST]); |
|---|
| 1561 | clusters[XMAX-1][y]->p_dspin_int_cmd_in[EAST] (signal_dspin_false_int_cmd_in[XMAX-1][y][EAST]); |
|---|
| 1562 | clusters[XMAX-1][y]->p_dspin_int_cmd_out[EAST] (signal_dspin_false_int_cmd_out[XMAX-1][y][EAST]); |
|---|
| 1563 | |
|---|
| 1564 | clusters[0][y]->p_dspin_int_rsp_in[WEST] (signal_dspin_false_int_rsp_in[0][y][WEST]); |
|---|
| 1565 | clusters[0][y]->p_dspin_int_rsp_out[WEST] (signal_dspin_false_int_rsp_out[0][y][WEST]); |
|---|
| 1566 | clusters[XMAX-1][y]->p_dspin_int_rsp_in[EAST] (signal_dspin_false_int_rsp_in[XMAX-1][y][EAST]); |
|---|
| 1567 | clusters[XMAX-1][y]->p_dspin_int_rsp_out[EAST] (signal_dspin_false_int_rsp_out[XMAX-1][y][EAST]); |
|---|
| 1568 | |
|---|
| 1569 | clusters[0][y]->p_dspin_int_m2p_in[WEST] (signal_dspin_false_int_m2p_in[0][y][WEST]); |
|---|
| 1570 | clusters[0][y]->p_dspin_int_m2p_out[WEST] (signal_dspin_false_int_m2p_out[0][y][WEST]); |
|---|
| 1571 | clusters[XMAX-1][y]->p_dspin_int_m2p_in[EAST] (signal_dspin_false_int_m2p_in[XMAX-1][y][EAST]); |
|---|
| 1572 | clusters[XMAX-1][y]->p_dspin_int_m2p_out[EAST] (signal_dspin_false_int_m2p_out[XMAX-1][y][EAST]); |
|---|
| 1573 | |
|---|
| 1574 | clusters[0][y]->p_dspin_int_p2m_in[WEST] (signal_dspin_false_int_p2m_in[0][y][WEST]); |
|---|
| 1575 | clusters[0][y]->p_dspin_int_p2m_out[WEST] (signal_dspin_false_int_p2m_out[0][y][WEST]); |
|---|
| 1576 | clusters[XMAX-1][y]->p_dspin_int_p2m_in[EAST] (signal_dspin_false_int_p2m_in[XMAX-1][y][EAST]); |
|---|
| 1577 | clusters[XMAX-1][y]->p_dspin_int_p2m_out[EAST] (signal_dspin_false_int_p2m_out[XMAX-1][y][EAST]); |
|---|
| 1578 | |
|---|
| 1579 | clusters[0][y]->p_dspin_int_cla_in[WEST] (signal_dspin_false_int_cla_in[0][y][WEST]); |
|---|
| 1580 | clusters[0][y]->p_dspin_int_cla_out[WEST] (signal_dspin_false_int_cla_out[0][y][WEST]); |
|---|
| 1581 | clusters[XMAX-1][y]->p_dspin_int_cla_in[EAST] (signal_dspin_false_int_cla_in[XMAX-1][y][EAST]); |
|---|
| 1582 | clusters[XMAX-1][y]->p_dspin_int_cla_out[EAST] (signal_dspin_false_int_cla_out[XMAX-1][y][EAST]); |
|---|
| 1583 | |
|---|
| 1584 | clusters[0][y]->p_dspin_ram_cmd_in[WEST] (signal_dspin_false_ram_cmd_in[0][y][WEST]); |
|---|
| 1585 | clusters[0][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_false_ram_cmd_out[0][y][WEST]); |
|---|
| 1586 | clusters[XMAX-1][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_false_ram_cmd_in[XMAX-1][y][EAST]); |
|---|
| 1587 | clusters[XMAX-1][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_false_ram_cmd_out[XMAX-1][y][EAST]); |
|---|
| 1588 | |
|---|
| 1589 | clusters[0][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_false_ram_rsp_in[0][y][WEST]); |
|---|
| 1590 | clusters[0][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_false_ram_rsp_out[0][y][WEST]); |
|---|
| 1591 | clusters[XMAX-1][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_false_ram_rsp_in[XMAX-1][y][EAST]); |
|---|
| 1592 | clusters[XMAX-1][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_false_ram_rsp_out[XMAX-1][y][EAST]); |
|---|
| 1593 | } |
|---|
| 1594 | |
|---|
| 1595 | std::cout << "East & West boundaries established" << std::endl; |
|---|
| 1596 | |
|---|
| 1597 | // North & South boundary clusters connections |
|---|
| 1598 | for (size_t x = 0; x < XMAX; x++) |
|---|
| 1599 | { |
|---|
| 1600 | clusters[x][0]->p_dspin_int_cmd_in[SOUTH] (signal_dspin_false_int_cmd_in[x][0][SOUTH]); |
|---|
| 1601 | clusters[x][0]->p_dspin_int_cmd_out[SOUTH] (signal_dspin_false_int_cmd_out[x][0][SOUTH]); |
|---|
| 1602 | clusters[x][YMAX-1]->p_dspin_int_cmd_in[NORTH] (signal_dspin_false_int_cmd_in[x][YMAX-1][NORTH]); |
|---|
| 1603 | clusters[x][YMAX-1]->p_dspin_int_cmd_out[NORTH] (signal_dspin_false_int_cmd_out[x][YMAX-1][NORTH]); |
|---|
| 1604 | |
|---|
| 1605 | clusters[x][0]->p_dspin_int_rsp_in[SOUTH] (signal_dspin_false_int_rsp_in[x][0][SOUTH]); |
|---|
| 1606 | clusters[x][0]->p_dspin_int_rsp_out[SOUTH] (signal_dspin_false_int_rsp_out[x][0][SOUTH]); |
|---|
| 1607 | clusters[x][YMAX-1]->p_dspin_int_rsp_in[NORTH] (signal_dspin_false_int_rsp_in[x][YMAX-1][NORTH]); |
|---|
| 1608 | clusters[x][YMAX-1]->p_dspin_int_rsp_out[NORTH] (signal_dspin_false_int_rsp_out[x][YMAX-1][NORTH]); |
|---|
| 1609 | |
|---|
| 1610 | clusters[x][0]->p_dspin_int_m2p_in[SOUTH] (signal_dspin_false_int_m2p_in[x][0][SOUTH]); |
|---|
| 1611 | clusters[x][0]->p_dspin_int_m2p_out[SOUTH] (signal_dspin_false_int_m2p_out[x][0][SOUTH]); |
|---|
| 1612 | clusters[x][YMAX-1]->p_dspin_int_m2p_in[NORTH] (signal_dspin_false_int_m2p_in[x][YMAX-1][NORTH]); |
|---|
| 1613 | clusters[x][YMAX-1]->p_dspin_int_m2p_out[NORTH] (signal_dspin_false_int_m2p_out[x][YMAX-1][NORTH]); |
|---|
| 1614 | |
|---|
| 1615 | clusters[x][0]->p_dspin_int_p2m_in[SOUTH] (signal_dspin_false_int_p2m_in[x][0][SOUTH]); |
|---|
| 1616 | clusters[x][0]->p_dspin_int_p2m_out[SOUTH] (signal_dspin_false_int_p2m_out[x][0][SOUTH]); |
|---|
| 1617 | clusters[x][YMAX-1]->p_dspin_int_p2m_in[NORTH] (signal_dspin_false_int_p2m_in[x][YMAX-1][NORTH]); |
|---|
| 1618 | clusters[x][YMAX-1]->p_dspin_int_p2m_out[NORTH] (signal_dspin_false_int_p2m_out[x][YMAX-1][NORTH]); |
|---|
| 1619 | |
|---|
| 1620 | clusters[x][0]->p_dspin_int_cla_in[SOUTH] (signal_dspin_false_int_cla_in[x][0][SOUTH]); |
|---|
| 1621 | clusters[x][0]->p_dspin_int_cla_out[SOUTH] (signal_dspin_false_int_cla_out[x][0][SOUTH]); |
|---|
| 1622 | clusters[x][YMAX-1]->p_dspin_int_cla_in[NORTH] (signal_dspin_false_int_cla_in[x][YMAX-1][NORTH]); |
|---|
| 1623 | clusters[x][YMAX-1]->p_dspin_int_cla_out[NORTH] (signal_dspin_false_int_cla_out[x][YMAX-1][NORTH]); |
|---|
| 1624 | |
|---|
| 1625 | clusters[x][0]->p_dspin_ram_cmd_in[SOUTH] (signal_dspin_false_ram_cmd_in[x][0][SOUTH]); |
|---|
| 1626 | clusters[x][0]->p_dspin_ram_cmd_out[SOUTH] (signal_dspin_false_ram_cmd_out[x][0][SOUTH]); |
|---|
| 1627 | clusters[x][YMAX-1]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_false_ram_cmd_in[x][YMAX-1][NORTH]); |
|---|
| 1628 | clusters[x][YMAX-1]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_false_ram_cmd_out[x][YMAX-1][NORTH]); |
|---|
| 1629 | |
|---|
| 1630 | clusters[x][0]->p_dspin_ram_rsp_in[SOUTH] (signal_dspin_false_ram_rsp_in[x][0][SOUTH]); |
|---|
| 1631 | clusters[x][0]->p_dspin_ram_rsp_out[SOUTH] (signal_dspin_false_ram_rsp_out[x][0][SOUTH]); |
|---|
| 1632 | clusters[x][YMAX-1]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_false_ram_rsp_in[x][YMAX-1][NORTH]); |
|---|
| 1633 | clusters[x][YMAX-1]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_false_ram_rsp_out[x][YMAX-1][NORTH]); |
|---|
| 1634 | } |
|---|
| 1635 | |
|---|
| 1636 | std::cout << "North & South boundaries established" << std::endl << std::endl; |
|---|
| 1637 | |
|---|
| 1638 | //////////////////////////////////////////////////////// |
|---|
| 1639 | // Simulation |
|---|
| 1640 | /////////////////////////////////////////////////////// |
|---|
| 1641 | |
|---|
| 1642 | sc_start(sc_core::sc_time(0, SC_NS)); |
|---|
| 1643 | |
|---|
| 1644 | signal_resetn = false; |
|---|
| 1645 | signal_irq_false = false; |
|---|
| 1646 | |
|---|
| 1647 | // network boundaries signals |
|---|
| 1648 | for (size_t x = 0; x < XMAX ; x++) |
|---|
| 1649 | { |
|---|
| 1650 | for (size_t y = 0; y < YMAX ; y++) |
|---|
| 1651 | { |
|---|
| 1652 | for (size_t a = 0; a < 4; a++) |
|---|
| 1653 | { |
|---|
| 1654 | signal_dspin_false_int_cmd_in[x][y][a].write = false; |
|---|
| 1655 | signal_dspin_false_int_cmd_in[x][y][a].read = true; |
|---|
| 1656 | signal_dspin_false_int_cmd_out[x][y][a].write = false; |
|---|
| 1657 | signal_dspin_false_int_cmd_out[x][y][a].read = true; |
|---|
| 1658 | |
|---|
| 1659 | signal_dspin_false_int_rsp_in[x][y][a].write = false; |
|---|
| 1660 | signal_dspin_false_int_rsp_in[x][y][a].read = true; |
|---|
| 1661 | signal_dspin_false_int_rsp_out[x][y][a].write = false; |
|---|
| 1662 | signal_dspin_false_int_rsp_out[x][y][a].read = true; |
|---|
| 1663 | |
|---|
| 1664 | signal_dspin_false_int_m2p_in[x][y][a].write = false; |
|---|
| 1665 | signal_dspin_false_int_m2p_in[x][y][a].read = true; |
|---|
| 1666 | signal_dspin_false_int_m2p_out[x][y][a].write = false; |
|---|
| 1667 | signal_dspin_false_int_m2p_out[x][y][a].read = true; |
|---|
| 1668 | |
|---|
| 1669 | signal_dspin_false_int_p2m_in[x][y][a].write = false; |
|---|
| 1670 | signal_dspin_false_int_p2m_in[x][y][a].read = true; |
|---|
| 1671 | signal_dspin_false_int_p2m_out[x][y][a].write = false; |
|---|
| 1672 | signal_dspin_false_int_p2m_out[x][y][a].read = true; |
|---|
| 1673 | |
|---|
| 1674 | signal_dspin_false_int_cla_in[x][y][a].write = false; |
|---|
| 1675 | signal_dspin_false_int_cla_in[x][y][a].read = true; |
|---|
| 1676 | signal_dspin_false_int_cla_out[x][y][a].write = false; |
|---|
| 1677 | signal_dspin_false_int_cla_out[x][y][a].read = true; |
|---|
| 1678 | |
|---|
| 1679 | signal_dspin_false_ram_cmd_in[x][y][a].write = false; |
|---|
| 1680 | signal_dspin_false_ram_cmd_in[x][y][a].read = true; |
|---|
| 1681 | signal_dspin_false_ram_cmd_out[x][y][a].write = false; |
|---|
| 1682 | signal_dspin_false_ram_cmd_out[x][y][a].read = true; |
|---|
| 1683 | |
|---|
| 1684 | signal_dspin_false_ram_rsp_in[x][y][a].write = false; |
|---|
| 1685 | signal_dspin_false_ram_rsp_in[x][y][a].read = true; |
|---|
| 1686 | signal_dspin_false_ram_rsp_out[x][y][a].write = false; |
|---|
| 1687 | signal_dspin_false_ram_rsp_out[x][y][a].read = true; |
|---|
| 1688 | } |
|---|
| 1689 | } |
|---|
| 1690 | } |
|---|
| 1691 | |
|---|
| 1692 | sc_start(sc_core::sc_time(1, SC_NS)); |
|---|
| 1693 | signal_resetn = true; |
|---|
| 1694 | |
|---|
| 1695 | |
|---|
| 1696 | // simulation loop |
|---|
| 1697 | struct timeval t1,t2; |
|---|
| 1698 | gettimeofday(&t1, NULL); |
|---|
| 1699 | |
|---|
| 1700 | |
|---|
| 1701 | for ( size_t n = 0; n < ncycles ; n += simul_period ) |
|---|
| 1702 | { |
|---|
| 1703 | // stats display |
|---|
| 1704 | if( (n % 1000000) == 0) |
|---|
| 1705 | { |
|---|
| 1706 | gettimeofday(&t2, NULL); |
|---|
| 1707 | uint64_t ms1 = (uint64_t) t1.tv_sec * 1000ULL + |
|---|
| 1708 | (uint64_t) t1.tv_usec / 1000; |
|---|
| 1709 | uint64_t ms2 = (uint64_t) t2.tv_sec * 1000ULL + |
|---|
| 1710 | (uint64_t) t2.tv_usec / 1000; |
|---|
| 1711 | std::cerr << "### cycle = " << std::dec << n |
|---|
| 1712 | << " / frequency = " |
|---|
| 1713 | << (double) 1000000 / (double) (ms2 - ms1) << "Khz" |
|---|
| 1714 | << std::endl; |
|---|
| 1715 | |
|---|
| 1716 | gettimeofday(&t1, NULL); |
|---|
| 1717 | |
|---|
| 1718 | // loop on all processors to display FROZEN stats |
|---|
| 1719 | for ( size_t x = 0 ; x < XMAX ; x++ ) |
|---|
| 1720 | { |
|---|
| 1721 | for ( size_t y = 0 ; y < YMAX ; y++ ) |
|---|
| 1722 | { |
|---|
| 1723 | for ( size_t l = 0 ; l < NB_PROCS_MAX ; l++ ) |
|---|
| 1724 | { |
|---|
| 1725 | clusters[x][y]->proc[l]->print_frozen_stats(); |
|---|
| 1726 | } |
|---|
| 1727 | } |
|---|
| 1728 | } |
|---|
| 1729 | } |
|---|
| 1730 | |
|---|
| 1731 | // Monitor a specific address for one L1 data cache |
|---|
| 1732 | // clusters[0][0]->proc[0]->cache_monitor( 0x100055574ULL ); |
|---|
| 1733 | |
|---|
| 1734 | // Monitor a specific address for L2 cache (single word if second argument true) |
|---|
| 1735 | clusters[0][0]->memc->cache_monitor( 0x001EE87CULL , true ); |
|---|
| 1736 | |
|---|
| 1737 | // Monitor a specific address for one XRAM |
|---|
| 1738 | clusters[0][0]->xram->start_monitor( 0x001EE87CULL , 4 ); |
|---|
| 1739 | |
|---|
| 1740 | // Monitor the MMU for one L1 cache |
|---|
| 1741 | // clusters[0][0]->proc[0]->mmu_monitor(); |
|---|
| 1742 | |
|---|
| 1743 | if ( debug_ok and (n >= debug_from) and ((n & debug_mask) == 0) ) |
|---|
| 1744 | { |
|---|
| 1745 | std::cout << "****************** cycle " << std::dec << n ; |
|---|
| 1746 | std::cout << " ************************************************" << std::endl; |
|---|
| 1747 | // |
|---|
| 1748 | // trace proc[debug_proc_id] |
|---|
| 1749 | if ( debug_proc_id != 0xFFFFFFFF ) |
|---|
| 1750 | { |
|---|
| 1751 | // processor debug modes |
|---|
| 1752 | // 0x01 : write buffer trace |
|---|
| 1753 | // 0x02 : dump processor registers |
|---|
| 1754 | // 0x04 : dcache trace |
|---|
| 1755 | // 0x08 : icache trace |
|---|
| 1756 | // 0x10 : dtlb trace |
|---|
| 1757 | // 0x20 : itlb trace |
|---|
| 1758 | // 0x40 : SR |
|---|
| 1759 | |
|---|
| 1760 | size_t l = debug_proc_id & ((1<<P_WIDTH)-1) ; |
|---|
| 1761 | size_t cluster_xy = debug_proc_id >> P_WIDTH ; |
|---|
| 1762 | size_t x = cluster_xy >> 4; |
|---|
| 1763 | size_t y = cluster_xy & 0xF; |
|---|
| 1764 | /* |
|---|
| 1765 | size_t l; |
|---|
| 1766 | size_t x = 0; |
|---|
| 1767 | size_t y = 0; |
|---|
| 1768 | |
|---|
| 1769 | for( l = 0 ; l < 2 ; l++ ) |
|---|
| 1770 | { |
|---|
| 1771 | */ |
|---|
| 1772 | clusters[x][y]->proc[l]->print_trace(0x42); |
|---|
| 1773 | std::ostringstream proc_signame; |
|---|
| 1774 | proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; |
|---|
| 1775 | clusters[x][y]->signal_int_vci_ini_proc[l].print_trace(proc_signame.str()); |
|---|
| 1776 | |
|---|
| 1777 | // XICU |
|---|
| 1778 | clusters[x][y]->xicu->print_trace(1); |
|---|
| 1779 | std::ostringstream xicu_signame; |
|---|
| 1780 | xicu_signame << "[SIG]XICU_" << x << "_" << y; |
|---|
| 1781 | clusters[x][y]->signal_int_vci_tgt_xicu.print_trace(xicu_signame.str()); |
|---|
| 1782 | |
|---|
| 1783 | // MDMA |
|---|
| 1784 | // clusters[x][y]->mdma->print_trace(); |
|---|
| 1785 | // std::ostringstream mdma_tgt_signame; |
|---|
| 1786 | // mdma_tgt_signame << "[SIG]MDMA_TGT_" << x << "_" << y; |
|---|
| 1787 | // clusters[x][y]->signal_int_vci_tgt_mdma.print_trace(mdma_tgt_signame.str()); |
|---|
| 1788 | // std::ostringstream mdma_ini_signame; |
|---|
| 1789 | // mdma_ini_signame << "[SIG]MDMA_INI_" << x << "_" << y; |
|---|
| 1790 | // clusters[x][y]->signal_int_vci_ini_mdma.print_trace(mdma_ini_signame.str()); |
|---|
| 1791 | |
|---|
| 1792 | // local interrupts in cluster(x,y) |
|---|
| 1793 | if( clusters[x][y]->signal_irq_memc.read() ) |
|---|
| 1794 | std::cout << "### IRQ_MMC_" << std::dec << x << "_" << y |
|---|
| 1795 | << " ACTIVE" << std::endl; |
|---|
| 1796 | |
|---|
| 1797 | for( size_t i = 0 ; i < NB_PROCS_MAX ; i++ ) |
|---|
| 1798 | { |
|---|
| 1799 | if( clusters[x][y]->signal_irq_mdma[i].read() ) |
|---|
| 1800 | std::cout << "### IRQ_DMA_" << std::dec << x << "_" << y << "_" << i |
|---|
| 1801 | << " ACTIVE" << std::endl; |
|---|
| 1802 | |
|---|
| 1803 | if( clusters[x][y]->signal_proc_it[i<<2].read() ) |
|---|
| 1804 | std::cout << "### IRQ_PROC_" << std::dec << x << "_" << y << "_" << i |
|---|
| 1805 | << " ACTIVE" << std::endl; |
|---|
| 1806 | } |
|---|
| 1807 | } |
|---|
| 1808 | |
|---|
| 1809 | // trace memc[debug_memc_id] |
|---|
| 1810 | if ( debug_memc_id != 0xFFFFFFFF ) |
|---|
| 1811 | { |
|---|
| 1812 | size_t x = debug_memc_id >> 4; |
|---|
| 1813 | size_t y = debug_memc_id & 0xF; |
|---|
| 1814 | |
|---|
| 1815 | clusters[x][y]->memc->print_trace(0); |
|---|
| 1816 | std::ostringstream smemc_tgt; |
|---|
| 1817 | smemc_tgt << "[SIG]MEMC_TGT_" << x << "_" << y; |
|---|
| 1818 | clusters[x][y]->signal_int_vci_tgt_memc.print_trace(smemc_tgt.str()); |
|---|
| 1819 | std::ostringstream smemc_ini; |
|---|
| 1820 | smemc_ini << "[SIG]MEMC_INI_" << x << "_" << y; |
|---|
| 1821 | clusters[x][y]->signal_ram_vci_ini_memc.print_trace(smemc_ini.str()); |
|---|
| 1822 | |
|---|
| 1823 | clusters[x][y]->xram->print_trace(); |
|---|
| 1824 | std::ostringstream sxram_tgt; |
|---|
| 1825 | sxram_tgt << "[SIG]XRAM_TGT_" << x << "_" << y; |
|---|
| 1826 | clusters[x][y]->signal_ram_vci_tgt_xram.print_trace(sxram_tgt.str()); |
|---|
| 1827 | |
|---|
| 1828 | // clusters[x][y]->ram_router_cmd->print_trace(); |
|---|
| 1829 | // clusters[x][y]->ram_router_rsp->print_trace(); |
|---|
| 1830 | |
|---|
| 1831 | // clusters[x][y]->ram_xbar_cmd->print_trace(); |
|---|
| 1832 | // clusters[x][y]->ram_xbar_rsp->print_trace(); |
|---|
| 1833 | } |
|---|
| 1834 | |
|---|
| 1835 | // trace iob, iox and external peripherals |
|---|
| 1836 | if ( debug_iob ) |
|---|
| 1837 | { |
|---|
| 1838 | clusters[0][0]->iob->print_trace(); |
|---|
| 1839 | clusters[0][0]->signal_int_vci_tgt_iobx.print_trace( "[SIG]IOB0_INT_TGT"); |
|---|
| 1840 | clusters[0][0]->signal_int_vci_ini_iobx.print_trace( "[SIG]IOB0_INT_INI"); |
|---|
| 1841 | clusters[0][0]->signal_ram_vci_ini_iobx.print_trace( "[SIG]IOB0_RAM_INI"); |
|---|
| 1842 | signal_vci_ini_iob0.print_trace("[SIG]IOB0_IOX_INI"); |
|---|
| 1843 | signal_vci_tgt_iob0.print_trace("[SIG]IOB0_IOX_TGT"); |
|---|
| 1844 | |
|---|
| 1845 | iox_network->print_trace(); |
|---|
| 1846 | } |
|---|
| 1847 | |
|---|
| 1848 | if ( debug_txt ) |
|---|
| 1849 | { |
|---|
| 1850 | mtty->print_trace( 1 ); |
|---|
| 1851 | signal_vci_tgt_mtty.print_trace("[SIG]MTTY_TGT"); |
|---|
| 1852 | |
|---|
| 1853 | for( size_t k = 0 ; k < NB_TXT_CHANNELS ; k++ ) |
|---|
| 1854 | { |
|---|
| 1855 | if ( signal_irq_mtty_rx[k].read() ) |
|---|
| 1856 | std::cout << "### IRQ_MTTY_RX[" << k << "] ACTIVE" << std::endl; |
|---|
| 1857 | |
|---|
| 1858 | if ( signal_irq_mtty_tx[k].read() ) |
|---|
| 1859 | std::cout << "### IRQ_MTTY_TX[" << k << "] ACTIVE" << std::endl; |
|---|
| 1860 | } |
|---|
| 1861 | } |
|---|
| 1862 | |
|---|
| 1863 | if ( debug_ioc ) |
|---|
| 1864 | { |
|---|
| 1865 | disk->print_trace(); |
|---|
| 1866 | signal_vci_tgt_disk.print_trace("[SIG]DISK_TGT"); |
|---|
| 1867 | signal_vci_ini_disk.print_trace("[SIG]DISK_INI"); |
|---|
| 1868 | |
|---|
| 1869 | #if ( USE_IOC_SDC ) |
|---|
| 1870 | card->print_trace(); |
|---|
| 1871 | #endif |
|---|
| 1872 | if ( signal_irq_disk.read() ) |
|---|
| 1873 | std::cout << "### IRQ_DISK ACTIVE" << std::endl; |
|---|
| 1874 | } |
|---|
| 1875 | |
|---|
| 1876 | if ( debug_nic ) |
|---|
| 1877 | { |
|---|
| 1878 | mnic->print_trace( |
|---|
| 1879 | NIC_MODE_TX_DMA | |
|---|
| 1880 | NIC_MODE_RX_DMA | |
|---|
| 1881 | NIC_MODE_RX_CHBUF | |
|---|
| 1882 | NIC_MODE_TX_CHBUF | |
|---|
| 1883 | NIC_MODE_VCI_CMD | |
|---|
| 1884 | NIC_MODE_VCI_RSP |
|---|
| 1885 | ); |
|---|
| 1886 | |
|---|
| 1887 | signal_vci_tgt_mnic.print_trace("[SIG]MNIC_TGT"); |
|---|
| 1888 | signal_vci_ini_mnic.print_trace("[SIG]MNIC_INI"); |
|---|
| 1889 | |
|---|
| 1890 | for( size_t k = 0 ; k < NB_TXT_CHANNELS ; k++ ) |
|---|
| 1891 | { |
|---|
| 1892 | if ( signal_irq_mtty_rx[k].read() ) |
|---|
| 1893 | std::cout << "### IRQ_MTTY_RX[" << k << "] ACTIVE" << std::endl; |
|---|
| 1894 | |
|---|
| 1895 | if ( signal_irq_mtty_tx[k].read() ) |
|---|
| 1896 | std::cout << "### IRQ_MTTY_TX[" << k << "] ACTIVE" << std::endl; |
|---|
| 1897 | } |
|---|
| 1898 | } |
|---|
| 1899 | |
|---|
| 1900 | if ( debug_fbf ) |
|---|
| 1901 | { |
|---|
| 1902 | fbuf->print_trace(); |
|---|
| 1903 | signal_vci_tgt_fbuf.print_trace("[SIG]FBUF_TGT"); |
|---|
| 1904 | |
|---|
| 1905 | iopi->print_trace(); |
|---|
| 1906 | signal_vci_ini_iopi.print_trace("[SIG]IOPI_INI"); |
|---|
| 1907 | signal_vci_tgt_iopi.print_trace("[SIG]IOPI_TGT"); |
|---|
| 1908 | } |
|---|
| 1909 | } // end if debug |
|---|
| 1910 | |
|---|
| 1911 | sc_start(sc_core::sc_time(simul_period, SC_NS)); |
|---|
| 1912 | } |
|---|
| 1913 | return EXIT_SUCCESS; |
|---|
| 1914 | } |
|---|
| 1915 | |
|---|
| 1916 | int sc_main (int argc, char *argv[]) |
|---|
| 1917 | { |
|---|
| 1918 | try { |
|---|
| 1919 | return _main(argc, argv); |
|---|
| 1920 | } catch (std::exception &e) { |
|---|
| 1921 | std::cout << e.what() << std::endl; |
|---|
| 1922 | } catch (...) { |
|---|
| 1923 | std::cout << "Unknown exception occured" << std::endl; |
|---|
| 1924 | throw; |
|---|
| 1925 | } |
|---|
| 1926 | return 1; |
|---|
| 1927 | } |
|---|
| 1928 | |
|---|
| 1929 | |
|---|
| 1930 | // Local Variables: |
|---|
| 1931 | // tab-width: 3 |
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| 1932 | // c-basic-offset: 3 |
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| 1933 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
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| 1934 | // indent-tabs-mode: nil |
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| 1935 | // End: |
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| 1936 | |
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| 1937 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
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| 1938 | |
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| 1939 | |
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| 1940 | |
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