source: trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd @ 468

Last change on this file since 468 was 468, checked in by cfuguet, 11 years ago


Merging vci_mem_cache from branches/v5 to trunk [441-467]

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r441 | cfuguet | 2013-07-17 10:54:07 +0200 (Wed, 17 Jul 2013) | 14 lines

Modifications in branches/v5/vci_mem_cache:

  • Changing name of CC DSPIN ports: + p_dspin_in => p_dspin_p2m + p_dspin_out => p_dspin_m2p
  • Splitting the Update Table in two tables: + UPT (Update Table): Stores the MULTI-UPDATE transactions + IVT (Invalidate Table): Stores the MULTI/BROADCAST INVALIDATE

transactions

Each table has its own allocator FSM: r_alloc_upt and r_alloc_ivt

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r442 | cfuguet | 2013-07-17 12:13:51 +0200 (Wed, 17 Jul 2013) | 13 lines

Modifications in branches/v5/modules/vci_mem_cache:

  • Introducing third port for the CLACK network.
  • CLEANUP FSM is no more a CC_SEND FSM client.
  • CLEANUP FSM controls directly the p_dspin_clack port

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r445 | cfuguet | 2013-07-18 10:49:36 +0200 (Thu, 18 Jul 2013) | 7 lines

Bugfix in vci_mem_cache:

  • Adding missing "strings" for print_trace() function
  • Adding alloc_ivt fsm (Invalidate Table) in the

print_trace() function

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r455 | cfuguet | 2013-07-19 10:16:17 +0200 (Fri, 19 Jul 2013) | 8 lines

Merged

/trunk/modules/vci_mem_cache:449 with
/branches/v5/modules/vci_mem_cache:446.

This merge introduces into the branch the last modifications concerning
the VCI memory cache configuration interface


Merging vci_cc_vcache_wrapper from branches/v5 to trunk [444-467]

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r444 | cfuguet | 2013-07-17 14:46:46 +0200 (Wed, 17 Jul 2013) | 7 lines

Modifications in branches/v5/modules/vci_cc_vcache_wrapper:

  • Renaming FROM_MC DSPIN flits fields in M2P
  • Renaming FROM_L1 DSPIN flits fields in P2M
  • Renaming CLEANUP_ACK DSPIN flits fields in CLACK

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r446 | cfuguet | 2013-07-18 11:37:47 +0200 (Thu, 18 Jul 2013) | 13 lines

Modifications in vci_cc_vcache_wrapper:

  • Merging the states DCACHE/ICACHE_CC_BROADCAST and DCACHE/ICACHE_CC_INVAL. This is because, the BROADCAST INVALIDATE and the MULTICAST INVALIDATE are both acknowledged by a CLEANUP.
  • Adding third port for the clack coherence network.
  • Renaming the port dspin_in to dspin_m2p and the port dspin_out to dspin_p2m

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r454 | haoliu | 2013-07-19 10:15:13 +0200 (Fri, 19 Jul 2013) | 2 lines

modified CC_RECEIVE FSM and CC_CHECK FSM (icache and dcache) for new
version V5

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r461 | cfuguet | 2013-07-19 15:49:43 +0200 (Fri, 19 Jul 2013) | 9 lines

Bugfix in vci_cc_vcache_wrapper:

  • In the states DCACHE/ICACHE CC_UPDT the FSM returns to the state CC_CHECK only when the cc_send_req is occupied.

We must not return to the CC_CHECK state if not ROK of the
DATA FIFO because the counter word counter will be reset.

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r462 | cfuguet | 2013-07-19 16:26:26 +0200 (Fri, 19 Jul 2013) | 8 lines

Modification in vci_cc_vcache_wrapper:

  • Optimization in DCACHE/ICACHE CC_CHECK state. We can handle a CLACK and a CC request if the latter does a MISS match. This is because the CC request doing MISS match does not need to access the directory

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r463 | cfuguet | 2013-07-19 16:52:06 +0200 (Fri, 19 Jul 2013) | 12 lines

Modification in vci_cc_vcache_wrapper:

  • Optimization in DCACHE/ICACHE CC_CHECK state. If pending request to CC_SEND, we wait in the CC_CHECK state. Doing this, during the wait, we can handle incoming CLACK avoiding any deadlock situation.

The states CC_UPDT and CC_INVAL do not need to test anymore if
there is a pending request to CC_SEND.


Merging tsar_generic_xbar from branches/v5 to trunk [447-467]

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r447 | cfuguet | 2013-07-18 16:12:05 +0200 (Thu, 18 Jul 2013) | 8 lines

Adding tsar_generic_xbar platform in branches/v5/platforms:

  • This platform contains a third local crossbar interconnect for the CLACK network.
  • It works only in a monocluster topology

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r448 | cfuguet | 2013-07-18 17:51:18 +0200 (Thu, 18 Jul 2013) | 9 lines

Modification in branches/v5/platforms/tsar_generic_xbar:

  • Adding a DSPIN router to the platform to allow the inter-cluster communication for the CLACK commands.

With this modification, the tsar_generic_xbar platform can be used
for multi-cluster simulations

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r466 | cfuguet | 2013-07-23 17:01:49 +0200 (Tue, 23 Jul 2013) | 9 lines

Modifications in branches/v5 vci_mem_cache:

  • Replacing the third router CLACK by a third virtual channel in the new virtual_dspin_router supporting several virtual channels.

The third channel has been added in the COMMAND router.

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r467 | cfuguet | 2013-07-23 17:23:13 +0200 (Tue, 23 Jul 2013) | 5 lines

Modifications in branches/v5 tsar_generic_xbar:

  • Adding preprocessor conditional statements for ALMOS support


Merging dspin_dhccp_param from branches/v5 to trunk [377-467]

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r442 | cfuguet | 2013-07-17 12:13:51 +0200 (Wed, 17 Jul 2013) | 13 lines

Modifications in branches/v5/communication/dspin_dhccp_param:

  • Renaming FROM_MC fields in M2P
  • Renaming FROM_L1 fields in P2M
  • Renaming CLEANUP_ACK fields in CLACK
File size: 5.4 KB
Line 
1
2# -*- python -*-
3
4Module('caba:tsar_iob_cluster',
5        classname = 'soclib::caba::TsarIobCluster',
6
7        tmpl_parameters = [
8                parameter.Module('vci_param_int', default = 'caba:vci_param', 
9                          cell_size = parameter.Reference('vci_data_width_int')),
10                parameter.Module('vci_param_ext', default = 'caba:vci_param', 
11                          cell_size = parameter.Reference('vci_data_width_ext')),
12                parameter.Int('dspin_int_cmd_width'),
13                parameter.Int('dspin_int_rsp_width'),
14                parameter.Int('dspin_ram_cmd_width'),
15                parameter.Int('dspin_ram_rsp_width'),
16        ],
17
18        header_files = [ 
19        '../source/include/tsar_iob_cluster.h', 
20    ],
21
22        implementation_files = [ 
23        '../source/src/tsar_iob_cluster.cpp', 
24    ],
25
26        uses = [
27                Uses('caba:base_module'),
28                Uses('common:mapping_table'),
29                Uses('common:iss2'),
30                Uses('common:elf_file_loader'),
31
32        # internal network components
33                Uses('caba:vci_cc_vcache_wrapper', 
34              cell_size          = parameter.Reference('vci_data_width_int'),
35              dspin_in_width     = parameter.Reference('dspin_int_cmd_width'),
36              dspin_out_width    = parameter.Reference('dspin_int_rsp_width'),
37              iss_t              = 'common:gdb_iss', 
38              gdb_iss_t          = 'common:mips32el'),
39
40                Uses('caba:vci_mem_cache',
41              memc_cell_size_int = parameter.Reference('vci_data_width_int'),
42              memc_cell_size_ext = parameter.Reference('vci_data_width_ext'),
43              dspin_in_width     = parameter.Reference('dspin_int_rsp_width'),
44              dspin_out_width    = parameter.Reference('dspin_int_cmd_width')),
45
46        Uses('caba:vci_xicu',
47              cell_size          = parameter.Reference('vci_data_width_int')),
48
49                Uses('caba:vci_multi_dma',
50              cell_size          = parameter.Reference('vci_data_width_int')),
51
52        Uses('caba:dspin_local_crossbar', 
53              flit_width         = parameter.Reference('dspin_int_cmd_width')),
54
55        Uses('caba:dspin_local_crossbar', 
56              flit_width         = parameter.Reference('dspin_int_rsp_width')),
57
58        Uses('caba:vci_dspin_initiator_wrapper', 
59              cell_size          = parameter.Reference('vci_data_width_int'),
60              dspin_cmd_width    = parameter.Reference('dspin_int_cmd_width'),
61              dspin_rsp_width    = parameter.Reference('dspin_int_rsp_width')),
62
63        Uses('caba:vci_dspin_target_wrapper',
64              cell_size          = parameter.Reference('vci_data_width_int'),
65              dspin_cmd_width    = parameter.Reference('dspin_int_cmd_width'),
66              dspin_rsp_width    = parameter.Reference('dspin_int_rsp_width')),
67
68        Uses('caba:virtual_dspin_router', 
69              flit_width         = parameter.Reference('dspin_int_cmd_width')),
70
71        Uses('caba:virtual_dspin_router', 
72              flit_width         = parameter.Reference('dspin_int_rsp_width')),
73
74        # RAM network components
75        Uses('caba:vci_dspin_initiator_wrapper', 
76              cell_size          = parameter.Reference('vci_data_width_ext'),
77              dspin_cmd_width    = parameter.Reference('dspin_ram_cmd_width'),
78              dspin_rsp_width    = parameter.Reference('dspin_ram_rsp_width')),
79
80        Uses('caba:vci_dspin_target_wrapper',
81              cell_size          = parameter.Reference('vci_data_width_ext'),
82              dspin_cmd_width    = parameter.Reference('dspin_ram_cmd_width'),
83              dspin_rsp_width    = parameter.Reference('dspin_ram_rsp_width')),
84
85        Uses('caba:dspin_local_crossbar', 
86              flit_width         = parameter.Reference('dspin_ram_cmd_width')),
87
88        Uses('caba:dspin_local_crossbar', 
89              flit_width         = parameter.Reference('dspin_ram_rsp_width')),
90
91        Uses('caba:dspin_router', 
92              flit_width         = parameter.Reference('dspin_ram_cmd_width')),
93
94        Uses('caba:dspin_router', 
95              flit_width         = parameter.Reference('dspin_ram_rsp_width')),
96
97                Uses('caba:vci_simple_ram',
98              cell_size          = parameter.Reference('vci_data_width_ext')),
99
100        # IOX network components
101        Uses('caba:vci_io_bridge', 
102              iob_cell_size_int  = parameter.Reference('vci_data_width_int'),
103              iob_cell_size_ext  = parameter.Reference('vci_data_width_ext')),
104                ],
105
106        ports = [
107                Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
108                Port('caba:clock_in', 'p_clk', auto = 'clock'),
109
110                Port('caba:dspin_output', 'p_int_cmd_out', [4, 3], 
111              dspin_data_size = parameter.Reference('dspin_int_cmd_width')),
112                Port('caba:dspin_input', 'p_int_cmd_in', [4, 3], 
113              dspin_data_size = parameter.Reference('dspin_int_cmd_width')),
114                Port('caba:dspin_output', 'p_int_rsp_out', [4, 2], 
115              dspin_data_size = parameter.Reference('dspin_int_rsp_width')), 
116                Port('caba:dspin_input', 'p_int_rsp_in', [4, 2], 
117              dspin_data_size = parameter.Reference('dspin_int_rsp_width')),
118
119                Port('caba:dspin_output', 'p_ram_cmd_out', [4], 
120              dspin_data_size = parameter.Reference('dspin_ram_cmd_width')),
121                Port('caba:dspin_input', 'p_ram_cmd_in', [4], 
122              dspin_data_size = parameter.Reference('dspin_ram_cmd_width')),
123                Port('caba:dspin_output', 'p_ram_rsp_out', [4], 
124              dspin_data_size = parameter.Reference('dspin_ram_rsp_width')), 
125                Port('caba:dspin_input', 'p_ram_rsp_in', [4], 
126              dspin_data_size = parameter.Reference('dspin_ram_rsp_width')),
127                ],
128)
129
130
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