source: trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h @ 468

Last change on this file since 468 was 468, checked in by cfuguet, 11 years ago


Merging vci_mem_cache from branches/v5 to trunk [441-467]

=-----------------------------------------------------------------------
r441 | cfuguet | 2013-07-17 10:54:07 +0200 (Wed, 17 Jul 2013) | 14 lines

Modifications in branches/v5/vci_mem_cache:

  • Changing name of CC DSPIN ports: + p_dspin_in => p_dspin_p2m + p_dspin_out => p_dspin_m2p
  • Splitting the Update Table in two tables: + UPT (Update Table): Stores the MULTI-UPDATE transactions + IVT (Invalidate Table): Stores the MULTI/BROADCAST INVALIDATE

transactions

Each table has its own allocator FSM: r_alloc_upt and r_alloc_ivt

=-----------------------------------------------------------------------
r442 | cfuguet | 2013-07-17 12:13:51 +0200 (Wed, 17 Jul 2013) | 13 lines

Modifications in branches/v5/modules/vci_mem_cache:

  • Introducing third port for the CLACK network.
  • CLEANUP FSM is no more a CC_SEND FSM client.
  • CLEANUP FSM controls directly the p_dspin_clack port

=-----------------------------------------------------------------------
r445 | cfuguet | 2013-07-18 10:49:36 +0200 (Thu, 18 Jul 2013) | 7 lines

Bugfix in vci_mem_cache:

  • Adding missing "strings" for print_trace() function
  • Adding alloc_ivt fsm (Invalidate Table) in the

print_trace() function

=-----------------------------------------------------------------------
r455 | cfuguet | 2013-07-19 10:16:17 +0200 (Fri, 19 Jul 2013) | 8 lines

Merged

/trunk/modules/vci_mem_cache:449 with
/branches/v5/modules/vci_mem_cache:446.

This merge introduces into the branch the last modifications concerning
the VCI memory cache configuration interface


Merging vci_cc_vcache_wrapper from branches/v5 to trunk [444-467]

=-----------------------------------------------------------------------
r444 | cfuguet | 2013-07-17 14:46:46 +0200 (Wed, 17 Jul 2013) | 7 lines

Modifications in branches/v5/modules/vci_cc_vcache_wrapper:

  • Renaming FROM_MC DSPIN flits fields in M2P
  • Renaming FROM_L1 DSPIN flits fields in P2M
  • Renaming CLEANUP_ACK DSPIN flits fields in CLACK

=-----------------------------------------------------------------------
r446 | cfuguet | 2013-07-18 11:37:47 +0200 (Thu, 18 Jul 2013) | 13 lines

Modifications in vci_cc_vcache_wrapper:

  • Merging the states DCACHE/ICACHE_CC_BROADCAST and DCACHE/ICACHE_CC_INVAL. This is because, the BROADCAST INVALIDATE and the MULTICAST INVALIDATE are both acknowledged by a CLEANUP.
  • Adding third port for the clack coherence network.
  • Renaming the port dspin_in to dspin_m2p and the port dspin_out to dspin_p2m

=-----------------------------------------------------------------------
r454 | haoliu | 2013-07-19 10:15:13 +0200 (Fri, 19 Jul 2013) | 2 lines

modified CC_RECEIVE FSM and CC_CHECK FSM (icache and dcache) for new
version V5

=-----------------------------------------------------------------------
r461 | cfuguet | 2013-07-19 15:49:43 +0200 (Fri, 19 Jul 2013) | 9 lines

Bugfix in vci_cc_vcache_wrapper:

  • In the states DCACHE/ICACHE CC_UPDT the FSM returns to the state CC_CHECK only when the cc_send_req is occupied.

We must not return to the CC_CHECK state if not ROK of the
DATA FIFO because the counter word counter will be reset.

=-----------------------------------------------------------------------
r462 | cfuguet | 2013-07-19 16:26:26 +0200 (Fri, 19 Jul 2013) | 8 lines

Modification in vci_cc_vcache_wrapper:

  • Optimization in DCACHE/ICACHE CC_CHECK state. We can handle a CLACK and a CC request if the latter does a MISS match. This is because the CC request doing MISS match does not need to access the directory

=-----------------------------------------------------------------------
r463 | cfuguet | 2013-07-19 16:52:06 +0200 (Fri, 19 Jul 2013) | 12 lines

Modification in vci_cc_vcache_wrapper:

  • Optimization in DCACHE/ICACHE CC_CHECK state. If pending request to CC_SEND, we wait in the CC_CHECK state. Doing this, during the wait, we can handle incoming CLACK avoiding any deadlock situation.

The states CC_UPDT and CC_INVAL do not need to test anymore if
there is a pending request to CC_SEND.


Merging tsar_generic_xbar from branches/v5 to trunk [447-467]

=-----------------------------------------------------------------------
r447 | cfuguet | 2013-07-18 16:12:05 +0200 (Thu, 18 Jul 2013) | 8 lines

Adding tsar_generic_xbar platform in branches/v5/platforms:

  • This platform contains a third local crossbar interconnect for the CLACK network.
  • It works only in a monocluster topology

=-----------------------------------------------------------------------
r448 | cfuguet | 2013-07-18 17:51:18 +0200 (Thu, 18 Jul 2013) | 9 lines

Modification in branches/v5/platforms/tsar_generic_xbar:

  • Adding a DSPIN router to the platform to allow the inter-cluster communication for the CLACK commands.

With this modification, the tsar_generic_xbar platform can be used
for multi-cluster simulations

=-----------------------------------------------------------------------
r466 | cfuguet | 2013-07-23 17:01:49 +0200 (Tue, 23 Jul 2013) | 9 lines

Modifications in branches/v5 vci_mem_cache:

  • Replacing the third router CLACK by a third virtual channel in the new virtual_dspin_router supporting several virtual channels.

The third channel has been added in the COMMAND router.

=-----------------------------------------------------------------------
r467 | cfuguet | 2013-07-23 17:23:13 +0200 (Tue, 23 Jul 2013) | 5 lines

Modifications in branches/v5 tsar_generic_xbar:

  • Adding preprocessor conditional statements for ALMOS support


Merging dspin_dhccp_param from branches/v5 to trunk [377-467]

=-----------------------------------------------------------------------
r442 | cfuguet | 2013-07-17 12:13:51 +0200 (Wed, 17 Jul 2013) | 13 lines

Modifications in branches/v5/communication/dspin_dhccp_param:

  • Renaming FROM_MC fields in M2P
  • Renaming FROM_L1 fields in P2M
  • Renaming CLEANUP_ACK fields in CLACK
File size: 12.0 KB
Line 
1//////////////////////////////////////////////////////////////////////////////
2// File: tsar_iob_cluster.h
3// Author: Alain Greiner
4// Copyright: UPMC/LIP6
5// Date : april 2013
6// This program is released under the GNU public license
7//////////////////////////////////////////////////////////////////////////////
8
9#ifndef SOCLIB_CABA_TSAR_IOB_CLUSTER_H
10#define SOCLIB_CABA_TSAR_IOB_CLUSTER_H
11
12#include <systemc>
13#include <sys/time.h>
14#include <iostream>
15#include <sstream>
16#include <cstdlib>
17#include <cstdarg>
18
19#include "gdbserver.h"
20#include "mapping_table.h"
21#include "mips32.h"
22#include "vci_simple_ram.h"
23#include "vci_xicu.h"
24#include "dspin_local_crossbar.h"
25#include "vci_dspin_initiator_wrapper.h"
26#include "vci_dspin_target_wrapper.h"
27#include "dspin_router.h"
28#include "virtual_dspin_router.h"
29#include "vci_multi_dma.h"
30#include "vci_mem_cache.h"
31#include "vci_cc_vcache_wrapper.h"
32#include "vci_io_bridge.h"
33
34namespace soclib { namespace caba       {
35
36///////////////////////////////////////////////////////////////////////////
37template<typename vci_param_int, 
38         typename vci_param_ext,
39         size_t   dspin_int_cmd_width, 
40         size_t   dspin_int_rsp_width,
41         size_t   dspin_ram_cmd_width,
42         size_t   dspin_ram_rsp_width>
43class TsarIobCluster
44///////////////////////////////////////////////////////////////////////////
45    : public soclib::caba::BaseModule
46{
47
48  public:
49
50        // Ports
51    sc_in<bool>                                            p_clk;
52    sc_in<bool>                                            p_resetn;
53
54    soclib::caba::VciInitiator<vci_param_ext>*         p_vci_iox_ini;
55    soclib::caba::VciTarget<vci_param_ext>*            p_vci_iox_tgt;
56
57    sc_in<bool>*                                       p_irq[32];  // not always used
58
59        soclib::caba::DspinOutput<dspin_int_cmd_width>**   p_dspin_int_cmd_out;
60        soclib::caba::DspinInput<dspin_int_cmd_width>**    p_dspin_int_cmd_in;
61    soclib::caba::DspinOutput<dspin_int_rsp_width>**   p_dspin_int_rsp_out;
62    soclib::caba::DspinInput<dspin_int_rsp_width>**    p_dspin_int_rsp_in;
63
64        soclib::caba::DspinOutput<dspin_ram_cmd_width>*    p_dspin_ram_cmd_out;
65        soclib::caba::DspinInput<dspin_ram_cmd_width>*     p_dspin_ram_cmd_in;
66    soclib::caba::DspinOutput<dspin_ram_rsp_width>*    p_dspin_ram_rsp_out;
67    soclib::caba::DspinInput<dspin_ram_rsp_width>*     p_dspin_ram_rsp_in;
68
69    // interrupt signals
70        sc_signal<bool>                       signal_false;
71        sc_signal<bool>                               signal_proc_it[8];
72        sc_signal<bool>                               signal_irq_mdma[8];
73       
74        // INT network DSPIN signals between DSPIN routers and DSPIN local_crossbars
75        DspinSignals<dspin_int_cmd_width>     signal_int_dspin_cmd_l2g_d; 
76        DspinSignals<dspin_int_cmd_width>     signal_int_dspin_cmd_g2l_d; 
77        DspinSignals<dspin_int_cmd_width>     signal_int_dspin_m2p_l2g_c;
78        DspinSignals<dspin_int_cmd_width>     signal_int_dspin_m2p_g2l_c; 
79        DspinSignals<dspin_int_cmd_width>     signal_int_dspin_clack_l2g_c;
80        DspinSignals<dspin_int_cmd_width>     signal_int_dspin_clack_g2l_c;
81        DspinSignals<dspin_int_rsp_width>     signal_int_dspin_rsp_l2g_d; 
82        DspinSignals<dspin_int_rsp_width>     signal_int_dspin_rsp_g2l_d; 
83        DspinSignals<dspin_int_rsp_width>     signal_int_dspin_p2m_l2g_c;
84        DspinSignals<dspin_int_rsp_width>     signal_int_dspin_p2m_g2l_c;
85
86        // INT network VCI signals between VCI components and VCI/DSPIN wrappers
87        VciSignals<vci_param_int>                 signal_int_vci_ini_proc[8]; 
88        VciSignals<vci_param_int>                 signal_int_vci_ini_mdma; 
89        VciSignals<vci_param_int>                 signal_int_vci_ini_iobx; 
90
91        VciSignals<vci_param_int>                 signal_int_vci_tgt_memc;
92        VciSignals<vci_param_int>                 signal_int_vci_tgt_xicu;
93        VciSignals<vci_param_int>             signal_int_vci_tgt_mdma;
94        VciSignals<vci_param_int>             signal_int_vci_tgt_iobx;
95
96        // INT network DSPIN signals between DSPIN local crossbars and VCI/DSPIN wrappers
97        DspinSignals<dspin_int_cmd_width>     signal_int_dspin_cmd_proc_i[8];
98        DspinSignals<dspin_int_rsp_width>     signal_int_dspin_rsp_proc_i[8];
99        DspinSignals<dspin_int_cmd_width>     signal_int_dspin_cmd_mdma_i;
100        DspinSignals<dspin_int_rsp_width>     signal_int_dspin_rsp_mdma_i;
101        DspinSignals<dspin_int_cmd_width>     signal_int_dspin_cmd_iobx_i;
102        DspinSignals<dspin_int_rsp_width>     signal_int_dspin_rsp_iobx_i;
103
104        DspinSignals<dspin_int_cmd_width>     signal_int_dspin_cmd_memc_t;
105        DspinSignals<dspin_int_rsp_width>     signal_int_dspin_rsp_memc_t;
106        DspinSignals<dspin_int_cmd_width>     signal_int_dspin_cmd_xicu_t;
107        DspinSignals<dspin_int_rsp_width>     signal_int_dspin_rsp_xicu_t;
108        DspinSignals<dspin_int_cmd_width>     signal_int_dspin_cmd_mdma_t;
109        DspinSignals<dspin_int_rsp_width>     signal_int_dspin_rsp_mdma_t;
110        DspinSignals<dspin_int_cmd_width>     signal_int_dspin_cmd_iobx_t;
111        DspinSignals<dspin_int_rsp_width>     signal_int_dspin_rsp_iobx_t;
112
113        // Coherence DSPIN signals between DSPIN local crossbars and CC components
114        DspinSignals<dspin_int_cmd_width>     signal_int_dspin_m2p_memc;
115        DspinSignals<dspin_int_cmd_width>     signal_int_dspin_clack_memc;
116        DspinSignals<dspin_int_rsp_width>     signal_int_dspin_p2m_memc;
117        DspinSignals<dspin_int_cmd_width>     signal_int_dspin_m2p_proc[8];
118        DspinSignals<dspin_int_cmd_width>     signal_int_dspin_clack_proc[8];
119        DspinSignals<dspin_int_rsp_width>     signal_int_dspin_p2m_proc[8];
120
121        // RAM network VCI signals between VCI components and VCI/DSPIN wrappers
122        VciSignals<vci_param_ext>             signal_ram_vci_ini_memc;
123        VciSignals<vci_param_ext>             signal_ram_vci_ini_iobx;
124        VciSignals<vci_param_ext>             signal_ram_vci_tgt_xram;
125
126    // RAM network DSPIN signals between VCI/DSPIN wrappers and crossbars or routers
127        DspinSignals<dspin_ram_cmd_width>     signal_ram_dspin_cmd_xram_t;
128        DspinSignals<dspin_ram_rsp_width>     signal_ram_dspin_rsp_xram_t;
129        DspinSignals<dspin_ram_cmd_width>     signal_ram_dspin_cmd_memc_i;
130        DspinSignals<dspin_ram_rsp_width>     signal_ram_dspin_rsp_memc_i;
131        DspinSignals<dspin_ram_cmd_width>     signal_ram_dspin_cmd_iobx_i;
132        DspinSignals<dspin_ram_rsp_width>     signal_ram_dspin_rsp_iobx_i;
133 
134    // RAM network DSPIN signals between DSPIN routers and DSPIN local crossbars
135        DspinSignals<dspin_ram_cmd_width>     signal_ram_dspin_cmd_l2g; 
136        DspinSignals<dspin_ram_cmd_width>     signal_ram_dspin_cmd_g2l; 
137        DspinSignals<dspin_ram_rsp_width>     signal_ram_dspin_rsp_l2g; 
138        DspinSignals<dspin_ram_rsp_width>     signal_ram_dspin_rsp_g2l; 
139       
140    //////////////////////////////////////
141    // Hardwate Components (pointers)
142    //////////////////////////////////////
143    VciCcVCacheWrapper<vci_param_int, 
144                       dspin_int_cmd_width,
145                       dspin_int_rsp_width,
146                       GdbServer<Mips32ElIss> >*      proc[8];
147
148    VciDspinInitiatorWrapper<vci_param_int,
149                             dspin_int_cmd_width,
150                             dspin_int_rsp_width>*    proc_wi[8];
151
152    VciMemCache<vci_param_int,
153                vci_param_ext, 
154                dspin_int_rsp_width, 
155                dspin_int_cmd_width>*                 memc;
156
157    VciDspinTargetWrapper<vci_param_int,
158                          dspin_int_cmd_width,
159                          dspin_int_rsp_width>*       memc_int_wt;
160
161    VciDspinInitiatorWrapper<vci_param_ext,
162                             dspin_ram_cmd_width,
163                             dspin_ram_rsp_width>*    memc_ram_wi;
164
165    VciXicu<vci_param_int>*                           xicu;
166
167    VciDspinTargetWrapper<vci_param_int,
168                          dspin_int_cmd_width,
169                          dspin_int_rsp_width>*       xicu_int_wt;
170
171    VciMultiDma<vci_param_int>*                       mdma;
172
173    VciDspinInitiatorWrapper<vci_param_int,
174                             dspin_int_cmd_width,
175                             dspin_int_rsp_width>*    mdma_int_wi;
176
177    VciDspinTargetWrapper<vci_param_int,
178                          dspin_int_cmd_width,
179                          dspin_int_rsp_width>*       mdma_int_wt;
180
181    DspinLocalCrossbar<dspin_int_cmd_width>*          int_xbar_cmd_d;
182    DspinLocalCrossbar<dspin_int_rsp_width>*          int_xbar_rsp_d;
183    DspinLocalCrossbar<dspin_int_cmd_width>*          int_xbar_m2p_c;
184    DspinLocalCrossbar<dspin_int_rsp_width>*          int_xbar_p2m_c;
185    DspinLocalCrossbar<dspin_int_cmd_width>*          int_xbar_clack_c;
186
187    VirtualDspinRouter<dspin_int_cmd_width>*          int_router_cmd;
188    VirtualDspinRouter<dspin_int_rsp_width>*          int_router_rsp;
189
190    VciSimpleRam<vci_param_ext>*                      xram;
191
192    VciDspinTargetWrapper<vci_param_ext,
193                          dspin_ram_cmd_width,
194                          dspin_ram_rsp_width>*       xram_ram_wt;
195       
196    DspinRouter<dspin_ram_cmd_width>*                 ram_router_cmd;
197    DspinRouter<dspin_ram_rsp_width>*                 ram_router_rsp;
198
199        // IO Network Components (not instanciated in all clusters)
200
201    VciIoBridge<vci_param_int,
202                vci_param_ext>*                       iob;
203
204    VciDspinInitiatorWrapper<vci_param_int,
205                             dspin_int_cmd_width,
206                             dspin_int_rsp_width>*    iob_int_wi;
207
208    VciDspinTargetWrapper<vci_param_int,
209                          dspin_int_cmd_width,
210                          dspin_int_rsp_width>*       iob_int_wt;
211
212    VciDspinInitiatorWrapper<vci_param_ext,
213                             dspin_ram_cmd_width,
214                             dspin_ram_rsp_width>*    iob_ram_wi;
215       
216    DspinLocalCrossbar<dspin_ram_cmd_width>*          ram_xbar_cmd; 
217    DspinLocalCrossbar<dspin_ram_rsp_width>*          ram_xbar_rsp; 
218
219    // cluster constructor
220        TsarIobCluster( sc_module_name                     insname,
221                    size_t                             nb_procs,   
222                    size_t                             nb_dmas, 
223                    size_t                             x,             // x coordinate
224                    size_t                             y,             // y coordinate
225                    size_t                             xmax,
226                    size_t                             ymax,
227
228                    const soclib::common::MappingTable &mt_int,
229                    const soclib::common::MappingTable &mt_ext,
230                    const soclib::common::MappingTable &mt_iox,
231
232                    size_t                                 x_width,       // x field  bits
233                    size_t                                 y_width,       // y field  bits
234                    size_t                                 l_width,       // l field  bits
235
236                    size_t                                 int_memc_tgtid,
237                    size_t                                 int_xicu_tgtid,
238                    size_t                                 int_mdma_tgtid,
239                    size_t                                 int_iobx_tgtid,
240
241                    size_t                             int_proc_srcid,
242                    size_t                             int_mdma_srcid,
243                    size_t                             int_iobx_srcid,
244
245                    size_t                             ext_xram_tgtid,
246
247                    size_t                             ext_memc_srcid,
248                    size_t                             ext_iobx_srcid,
249
250                    size_t                             memc_ways,
251                    size_t                             memc_sets,
252                    size_t                             l1_i_ways,
253                    size_t                             l1_i_sets, 
254                    size_t                             l1_d_ways,
255                    size_t                             l1_d_sets,       
256                    size_t                             xram_latency, 
257
258                    const Loader                       &loader,       // loader for XRAM
259
260                    uint32_t                           frozen_cycles, 
261                    uint32_t                           start_debug_cycle,
262                    bool                               memc_debug_ok, 
263                    bool                               proc_debug_ok, 
264                    bool                               iob0_debug_ok ); 
265
266};
267
268}}
269
270#endif
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