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tsar_iob_cluster.cpp

Last change on this file was 1051, checked in by alain, 7 years ago
Replace the vci_mwmr_dma hardware component by the vci_multi_dma component.
File size: 37.3 KB

Line
1	//////////////////////////////////////////////////////////////////////////////
2	// File: tsar_iob_cluster.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : april 2013
6	// This program is released under the GNU public license
7	//////////////////////////////////////////////////////////////////////////////
8	// Cluster(0,0) & Cluster(xmax-1,ymax-1) contains the IOB0 & IOB1 components.
9	// These two clusters contain 6 extra components:
10	// - 1 vci_io_bridge (connected to the 3 networks.
11	// - 3 vci_dspin_wrapper for the IOB.
12	// - 2 dspin_local_crossbar for commands and responses.
13	//////////////////////////////////////////////////////////////////////////////
14
15	#include "../include/tsar_iob_cluster.h"
16
17	#define tmpl(x) \
18	template<typename vci_param_int , typename vci_param_ext,\
19	size_t dspin_int_cmd_width, size_t dspin_int_rsp_width,\
20	size_t dspin_ram_cmd_width, size_t dspin_ram_rsp_width>\
21	x TsarIobCluster<\
22	vci_param_int , vci_param_ext,\
23	dspin_int_cmd_width, dspin_int_rsp_width,\
24	dspin_ram_cmd_width, dspin_ram_rsp_width>
25
26	namespace soclib { namespace caba {
27
28	/////////////////////////////////////////////////////////////////////////////
29	tmpl(/**/)::TsarIobCluster(
30	/////////////////////////////////////////////////////////////////////////////
31	sc_module_name insname,
32	size_t nb_procs,
33	size_t x_id,
34	size_t y_id,
35	size_t xmax,
36	size_t ymax,
37
38	const soclib::common::MappingTable &mt_int,
39	const soclib::common::MappingTable &mt_ram,
40	const soclib::common::MappingTable &mt_iox,
41
42	size_t x_width,
43	size_t y_width,
44	size_t l_width,
45	size_t p_width,
46
47	size_t int_memc_tgt_id, // local index
48	size_t int_xicu_tgt_id, // local index
49	size_t int_mdma_tgt_id, // local index
50	size_t int_iobx_tgt_id, // local index
51
52	size_t int_proc_ini_id, // local index
53	size_t int_mdma_ini_id, // local index
54	size_t int_iobx_ini_id, // local index
55
56	size_t ram_xram_tgt_id, // local index
57	size_t ram_memc_ini_id, // local index
58	size_t ram_iobx_ini_id, // local index
59
60	bool is_io, // is IO cluster (
61	size_t iox_iobx_tgt_id, // local_index
62	size_t iox_iobx_ini_id, // local index
63
64	size_t memc_ways,
65	size_t memc_sets,
66	size_t l1_i_ways,
67	size_t l1_i_sets,
68	size_t l1_d_ways,
69	size_t l1_d_sets,
70	size_t xram_latency,
71	size_t xcu_nb_hwi,
72	size_t xcu_nb_pti,
73	size_t xcu_nb_wti,
74	size_t xcu_nb_out,
75
76	size_t coproc_type,
77
78	const Loader &loader,
79
80	uint32_t frozen_cycles,
81	bool debug_ok,
82	uint32_t debug_start_cycle,
83	uint32_t debug_proc_id,
84	uint32_t debug_memc_id,
85	bool debug_iob )
86	: soclib::caba::BaseModule(insname),
87	p_clk("clk"),
88	p_resetn("resetn")
89	{
90	assert( (x_id < xmax) and (y_id < ymax) and
91	"Error in tsar_iob_cluster : Illegal cluster coordinates");
92
93	size_t cluster_id = (x_id<<4) + y_id;
94
95	// Vectors of DSPIN ports for inter-cluster communications
96	p_dspin_int_cmd_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4);
97	p_dspin_int_cmd_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4);
98
99	p_dspin_int_rsp_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4);
100	p_dspin_int_rsp_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4);
101
102	p_dspin_int_m2p_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_m2p_in", 4);
103	p_dspin_int_m2p_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_m2p_out", 4);
104
105	p_dspin_int_p2m_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_p2m_in", 4);
106	p_dspin_int_p2m_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_p2m_out", 4);
107
108	p_dspin_int_cla_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cla_in", 4);
109	p_dspin_int_cla_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cla_out", 4);
110
111	p_dspin_ram_cmd_in = alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4);
112	p_dspin_ram_cmd_out = alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4);
113
114	p_dspin_ram_rsp_in = alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4);
115	p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4);
116
117	// VCI ports from IOB to IOX network (only in IO clusters)
118	if ( is_io )
119	{
120	p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>;
121	p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>;
122	}
123
124	//////////////////////////////////////////////////////////////////////////////////
125	// Hardware components
126	//////////////////////////////////////////////////////////////////////////////////
127
128	size_t x_debug;
129	size_t y_debug;
130	size_t p_debug;
131
132	//////////// PROCS /////////////////////////////////////////////////////////////
133	for (size_t p = 0; p < nb_procs; p++)
134	{
135	std::ostringstream s_proc;
136	x_debug = (debug_proc_id >> (y_width + p_width)) & ((1<<x_width)-1);
137	y_debug = (debug_proc_id >> p_width ) & ((1<<y_width)-1);
138	p_debug = (debug_proc_id ) & ((1<<p_width)-1);
139
140
141	s_proc << "proc_" << x_id << "_" << y_id << "_" << p;
142	proc[p] = new VciCcVCacheWrapper<vci_param_int,
143	dspin_int_cmd_width,
144	dspin_int_rsp_width,
145	GdbServer<Mips32ElIss> >(
146	s_proc.str().c_str(),
147	(cluster_id << p_width) + p, // GLOBAL PROC_ID
148	mt_int, // Mapping Table INT network
149	IntTab(cluster_id,p), // SRCID
150	(cluster_id << l_width) + p, // CC_GLOBAL_ID
151	8, // ITLB ways
152	8, // ITLB sets
153	8, // DTLB ways
154	8, // DTLB sets
155	l1_i_ways, l1_i_sets, 16, // ICACHE size
156	l1_d_ways, l1_d_sets, 16, // DCACHE size
157	4, // WBUF nlines
158	4, // WBUF nwords
159	x_width,
160	y_width,
161	frozen_cycles, // max frozen cycles
162	debug_start_cycle,
163	debug_ok and (x_id == x_debug) and (y_id == y_debug) and (p_debug == p) );
164	}
165
166	//////////// MEMC /////////////////////////////////////////////////////////////
167	std::ostringstream s_memc;
168	s_memc << "memc_" << x_id << "_" << y_id;
169	x_debug = (debug_memc_id >> y_width) & ((1<<x_width)-1);
170	y_debug = (debug_memc_id ) & ((1<<y_width)-1);
171	memc = new VciMemCache<vci_param_int,
172	vci_param_ext,
173	dspin_int_rsp_width,
174	dspin_int_cmd_width>(
175	s_memc.str().c_str(),
176	mt_int, // Mapping Table INT network
177	mt_ram, // Mapping Table RAM network
178	IntTab(cluster_id, ram_memc_ini_id), // SRCID RAM network
179	IntTab(cluster_id, int_memc_tgt_id), // TGTID INT network
180	x_width, // number of bits for x coordinate
181	y_width, // number of bits for y coordinate
182	memc_ways, memc_sets, 16, // CACHE SIZE
183	3, // MAX NUMBER OF COPIES
184	4096, // HEAP SIZE
185	8, // TRANSACTION TABLE DEPTH
186	8, // UPDATE TABLE DEPTH
187	8, // INVALIDATE TABLE DEPTH
188	debug_start_cycle,
189	debug_ok and (x_id == x_debug) and (y_id == y_debug) );
190
191	std::ostringstream s_wi_memc;
192	s_wi_memc << "memc_wi_" << x_id << "_" << y_id;
193	memc_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
194	dspin_ram_cmd_width,
195	dspin_ram_rsp_width>(
196	s_wi_memc.str().c_str(),
197	x_width + y_width + l_width);
198
199	/////////// XICU //////////////////////////////////////////////////////////////
200	std::ostringstream s_xicu;
201	s_xicu << "xicu_" << x_id << "_" << y_id;
202	xicu = new VciXicu<vci_param_int>(
203	s_xicu.str().c_str(),
204	mt_int, // mapping table INT network
205	IntTab(cluster_id, int_xicu_tgt_id), // TGTID direct space
206	xcu_nb_pti, // number of timer IRQs
207	xcu_nb_hwi, // number of hard IRQs
208	xcu_nb_wti, // number of soft IRQs
209	xcu_nb_out); // number of output IRQs
210
211	//////////// MDMA //////////////////////////////////////////////////////////////
212	std::ostringstream s_mdma;
213	s_mdma << "mdma_" << x_id << "_" << y_id;
214	mdma = new VciMultiDma<vci_param_int>(
215	s_mdma.str().c_str(),
216	mt_int,
217	IntTab(cluster_id, int_mdma_ini_id), // SRCID
218	IntTab(cluster_id, int_mdma_tgt_id), // TGTID
219	64, // burst size
220	nb_procs ); // number of channels
221
222	/////////// VCI INT_CMD/RSP LOCAL_XBAR //////////////////////////////////////
223	size_t nb_direct_initiators = is_io ? nb_procs + 2 : nb_procs + 1;
224	size_t nb_direct_targets = is_io ? 4 : 3;
225
226	std::ostringstream s_int_xbar_d;
227	s_int_xbar_d << "int_xbar_cmd_d_" << x_id << "_" << y_id;
228	int_xbar_d = new VciLocalCrossbar<vci_param_int>(
229	s_int_xbar_d.str().c_str(),
230	mt_int, // mapping table
231	cluster_id, // cluster id
232	nb_direct_initiators, // number of local initiators
233	nb_direct_targets, // number of local targets
234	0 ); // default target
235
236	std::ostringstream s_int_dspin_ini_wrapper_gate_d;
237	s_int_dspin_ini_wrapper_gate_d << "int_dspin_ini_wrapper_gate_d_"
238	<< x_id << "_" << y_id;
239	int_wi_gate_d = new VciDspinInitiatorWrapper<vci_param_int,
240	dspin_int_cmd_width,
241	dspin_int_rsp_width>(
242	s_int_dspin_ini_wrapper_gate_d.str().c_str(),
243	x_width + y_width + l_width);
244
245	std::ostringstream s_int_dspin_tgt_wrapper_gate_d;
246	s_int_dspin_tgt_wrapper_gate_d << "int_dspin_tgt_wrapper_gate_d_"
247	<< x_id << "_" << y_id;
248	int_wt_gate_d = new VciDspinTargetWrapper<vci_param_int,
249	dspin_int_cmd_width,
250	dspin_int_rsp_width>(
251	s_int_dspin_tgt_wrapper_gate_d.str().c_str(),
252	x_width + y_width + l_width);
253
254	//////////// DSPIN INT_M2P LOCAL_XBAR ////////////////////////////////////////
255	std::ostringstream s_int_xbar_m2p_c;
256	s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id;
257	int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
258	s_int_xbar_m2p_c.str().c_str(),
259	mt_int, // mapping table
260	x_id, y_id, // cluster coordinates
261	x_width, y_width, l_width, // several dests
262	1, // number of local sources
263	nb_procs, // number of local dests
264	2, 2, // fifo depths
265	true, // pseudo CMD
266	false, // no routing table
267	true ); // broacast
268
269	//////////// DSPIN INT_P2M LOCAL_XBAR ////////////////////////////////////////
270	std::ostringstream s_int_xbar_p2m_c;
271	s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id;
272	int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>(
273	s_int_xbar_p2m_c.str().c_str(),
274	mt_int, // mapping table
275	x_id, y_id, // cluster coordinates
276	x_width, y_width, 0, // only one dest
277	nb_procs, // number of local sources
278	1, // number of local dests
279	2, 2, // fifo depths
280	false, // pseudo RSP
281	false, // no routing table
282	false ); // no broacast
283
284	//////////// DSPIN INT_CLA LOCAL_XBAR ////////////////////////////////////////
285	std::ostringstream s_int_xbar_clack_c;
286	s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id;
287	int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
288	s_int_xbar_clack_c.str().c_str(),
289	mt_int, // mapping table
290	x_id, y_id, // cluster coordinates
291	x_width, y_width, l_width,
292	1, // number of local sources
293	nb_procs, // number of local targets
294	1, 1, // fifo depths
295	true, // pseudo CMD
296	false, // no routing table
297	false); // no broadcast
298
299	//////////// DSPIN INT_CMD ROUTER ////////////////////////////////////////////
300	std::ostringstream s_int_router_cmd;
301	s_int_router_cmd << "int_router_cmd_" << x_id << "_" << y_id;
302	int_router_cmd = new DspinRouter<dspin_int_cmd_width>(
303	s_int_router_cmd.str().c_str(),
304	x_id,y_id, // coordinate in the mesh
305	x_width, y_width, // x & y fields width
306	4,4); // input & output fifo depths
307
308	//////////// DSPIN INT_RSP ROUTER ////////////////////////////////////////////
309	std::ostringstream s_int_router_rsp;
310	s_int_router_rsp << "int_router_rsp_" << x_id << "_" << y_id;
311	int_router_rsp = new DspinRouter<dspin_int_rsp_width>(
312	s_int_router_rsp.str().c_str(),
313	x_id,y_id, // coordinates in mesh
314	x_width, y_width, // x & y fields width
315	4,4); // input & output fifo depths
316
317	//////////// DSPIN INT_M2P ROUTER ////////////////////////////////////////////
318	std::ostringstream s_int_router_m2p;
319	s_int_router_m2p << "int_router_m2p_" << x_id << "_" << y_id;
320	int_router_m2p = new DspinRouter<dspin_int_cmd_width>(
321	s_int_router_m2p.str().c_str(),
322	x_id,y_id, // coordinate in the mesh
323	x_width, y_width, // x & y fields width
324	4,4, // input & output fifo depths
325	true); // broadcast supported
326
327	//////////// DSPIN INT_P2M ROUTER ////////////////////////////////////////////
328	std::ostringstream s_int_router_p2m;
329	s_int_router_p2m << "int_router_p2m_" << x_id << "_" << y_id;
330	int_router_p2m = new DspinRouter<dspin_int_rsp_width>(
331	s_int_router_p2m.str().c_str(),
332	x_id,y_id, // coordinates in mesh
333	x_width, y_width, // x & y fields width
334	4,4); // input & output fifo depths
335
336	//////////// DSPIN INT_CLA ROUTER ////////////////////////////////////////////
337	std::ostringstream s_int_router_cla;
338	s_int_router_cla << "int_router_cla_" << x_id << "_" << y_id;
339	int_router_cla = new DspinRouter<dspin_int_cmd_width>(
340	s_int_router_cla.str().c_str(),
341	x_id,y_id, // coordinate in the mesh
342	x_width, y_width, // x & y fields width
343	4,4); // input & output fifo depths
344
345	////////////// XRAM /////////////////////////////////////////////////////////
346	std::ostringstream s_xram;
347	s_xram << "xram_" << x_id << "_" << y_id;
348	xram = new VciSimpleRam<vci_param_ext>(
349	s_xram.str().c_str(),
350	IntTab(cluster_id, ram_xram_tgt_id),
351	mt_ram,
352	loader,
353	xram_latency);
354
355	std::ostringstream s_wt_xram;
356	s_wt_xram << "xram_wt_" << x_id << "_" << y_id;
357	xram_ram_wt = new VciDspinTargetWrapper<vci_param_ext,
358	dspin_ram_cmd_width,
359	dspin_ram_rsp_width>(
360	s_wt_xram.str().c_str(),
361	x_width + y_width + l_width);
362
363	//////////// DSPIN RAM_CMD ROUTER ///////////////////////////////////////////
364	std::ostringstream s_ram_router_cmd;
365	s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id;
366	ram_router_cmd = new DspinRouter<dspin_ram_cmd_width>(
367	s_ram_router_cmd.str().c_str(),
368	x_id, y_id, // router coordinates in mesh
369	x_width, // x field width in first flit
370	y_width, // y field width in first flit
371	4, 4); // input & output fifo depths
372
373	//////////// DSPIN RAM_RSP ROUTER ///////////////////////////////////////////
374	std::ostringstream s_ram_router_rsp;
375	s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id;
376	ram_router_rsp = new DspinRouter<dspin_ram_rsp_width>(
377	s_ram_router_rsp.str().c_str(),
378	x_id, y_id, // coordinates in mesh
379	x_width, // x field width in first flit
380	y_width, // y field width in first flit
381	4, 4); // input & output fifo depths
382
383
384	////////////////////// I/O CLUSTER ONLY ///////////////////////////////////
385	if ( is_io )
386	{
387	/////////// IO_BRIDGE ////////////////////////////////////////////////////
388	std::ostringstream s_iob;
389	s_iob << "iob_" << x_id << "_" << y_id;
390	iob = new VciIoBridge<vci_param_int,
391	vci_param_ext>(
392	s_iob.str().c_str(),
393	mt_ram, // EXT network maptab
394	mt_int, // INT network maptab
395	mt_iox, // IOX network maptab
396	IntTab( cluster_id, int_iobx_tgt_id ), // INT TGTID
397	IntTab( cluster_id, int_iobx_ini_id ), // INT SRCID
398	IntTab( 0 , iox_iobx_tgt_id ), // IOX TGTID
399	IntTab( 0 , iox_iobx_ini_id ), // IOX SRCID
400	16, // cache line words
401	8, // IOTLB ways
402	8, // IOTLB sets
403	debug_start_cycle,
404	debug_iob );
405
406	std::ostringstream s_iob_ram_wi;
407	s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id;
408	iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
409	dspin_ram_cmd_width,
410	dspin_ram_rsp_width>(
411	s_iob_ram_wi.str().c_str(),
412	vci_param_int::S);
413
414	//////////// DSPIN RAM_CMD LOCAL_XBAR ///////////////////////////////////
415	std::ostringstream s_ram_xbar_cmd;
416	s_ram_xbar_cmd << "s_ram_xbar_cmd_" << x_id << "_" << y_id;
417	ram_xbar_cmd = new DspinLocalCrossbar<dspin_ram_cmd_width>(
418	s_ram_xbar_cmd.str().c_str(), // name
419	mt_ram, // mapping table
420	x_id, y_id, // x, y
421	x_width, y_width, l_width, // x_width, y_width, l_width
422	2, 0, // local inputs, local outputs
423	2, 2, // in fifo, out fifo depths
424	true, // is cmd ?
425	false, // no routing table
426	false); // no broadcast
427
428	//////////// DSPIN RAM_RSP LOCAL_XBAR ///////////////////////////////////
429	std::ostringstream s_ram_xbar_rsp;
430	s_ram_xbar_rsp << "s_ram_xbar_rsp_" << x_id << "_" << y_id;
431	ram_xbar_rsp = new DspinLocalCrossbar<dspin_ram_rsp_width>(
432	s_ram_xbar_rsp.str().c_str(), // name
433	mt_ram, // mapping table
434	x_id, y_id, // x, y
435	x_width, y_width, l_width, // x_width, y_width, l_width
436	0, 2, // local inputs, local outputs
437	2, 2, // in fifo, out fifo depths
438	false, // is cmd ?
439	true, // use routing table
440	false); // no broadcast
441
442	} // end if IO
443
444	////////////////////////////////////
445	// Connections are defined here
446	////////////////////////////////////
447
448	// on coherence network : local srcid[proc] in [0...nb_procs-1]
449	// : local srcid[memc] = nb_procs
450
451	//////////////////////////////////// Processors
452	for (size_t p = 0; p < nb_procs; p++)
453	{
454	proc[p]->p_clk (this->p_clk);
455	proc[p]->p_resetn (this->p_resetn);
456
457	proc[p]->p_vci (signal_int_vci_ini_proc[p]);
458	proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]);
459	proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]);
460	proc[p]->p_dspin_clack (signal_int_dspin_cla_proc[p]);
461
462	for ( size_t j = 0 ; j < 6 ; j++)
463	{
464	if ( j < 4 ) proc[p]->p_irq[j] (signal_proc_it[4*p + j]);
465	else proc[p]->p_irq[j] (signal_false);
466	}
467	}
468
469	std::cout << " - processors connected" << std::endl;
470
471	///////////////////////////////////// XICU
472	xicu->p_clk (this->p_clk);
473	xicu->p_resetn (this->p_resetn);
474	xicu->p_vci (signal_int_vci_tgt_xicu);
475	for ( size_t i=0 ; i < xcu_nb_out ; i++)
476	{
477	xicu->p_irq[i] (signal_proc_it[i]);
478	}
479	for ( size_t i=0 ; i < xcu_nb_hwi ; i++)
480	{
481	if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc);
482	else if ( i < (nb_procs+1) ) xicu->p_hwi[i] (signal_irq_mdma[i-1]);
483	else xicu->p_hwi[i] (signal_false);
484	}
485
486	std::cout << " - xcu connected" << std::endl;
487
488	///////////////////////////////////// MEMC
489	memc->p_clk (this->p_clk);
490	memc->p_resetn (this->p_resetn);
491	memc->p_vci_ixr (signal_ram_vci_ini_memc);
492	memc->p_vci_tgt (signal_int_vci_tgt_memc);
493	memc->p_dspin_p2m (signal_int_dspin_p2m_memc);
494	memc->p_dspin_m2p (signal_int_dspin_m2p_memc);
495	memc->p_dspin_clack (signal_int_dspin_cla_memc);
496	memc->p_irq (signal_irq_memc);
497
498	// wrapper to RAM network
499	memc_ram_wi->p_clk (this->p_clk);
500	memc_ram_wi->p_resetn (this->p_resetn);
501	memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i);
502	memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i);
503	memc_ram_wi->p_vci (signal_ram_vci_ini_memc);
504
505	std::cout << " - memc connected" << std::endl;
506
507	//////////////////////////////////// XRAM
508	xram->p_clk (this->p_clk);
509	xram->p_resetn (this->p_resetn);
510	xram->p_vci (signal_ram_vci_tgt_xram);
511
512	// wrapper to RAM network
513	xram_ram_wt->p_clk (this->p_clk);
514	xram_ram_wt->p_resetn (this->p_resetn);
515	xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t);
516	xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t);
517	xram_ram_wt->p_vci (signal_ram_vci_tgt_xram);
518
519	std::cout << " - xram connected" << std::endl;
520
521	/////////////////////////////////// MDMA
522	mdma->p_clk (this->p_clk);
523	mdma->p_resetn (this->p_resetn);
524	mdma->p_vci_target (signal_int_vci_tgt_mdma);
525	mdma->p_vci_initiator (signal_int_vci_ini_mdma);
526	for( size_t i = 0 ; i < nb_procs ; i++ )
527	{
528	mdma->p_irq[i] (signal_irq_mdma[i]);
529	}
530
531	std::cout << " - mdma connected" << std::endl;
532
533	//////////////////////////// RAM NETWORK ROUTERS
534	ram_router_cmd->p_clk (this->p_clk);
535	ram_router_cmd->p_resetn (this->p_resetn);
536	ram_router_rsp->p_clk (this->p_clk);
537	ram_router_rsp->p_resetn (this->p_resetn);
538
539	for( size_t n=0 ; n<4 ; n++)
540	{
541	ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]);
542	ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]);
543	ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]);
544	ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]);
545	}
546
547	ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t);
548	ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t);
549
550	if ( is_io )
551	{
552	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_xbar);
553	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_xbar);
554	}
555	else
556	{
557	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i);
558	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i);
559	}
560
561	///////////////////////////// INT NETWORK ROUTERS
562	int_router_cmd->p_clk (this->p_clk);
563	int_router_cmd->p_resetn (this->p_resetn);
564	int_router_rsp->p_clk (this->p_clk);
565	int_router_rsp->p_resetn (this->p_resetn);
566	int_router_m2p->p_clk (this->p_clk);
567	int_router_m2p->p_resetn (this->p_resetn);
568	int_router_p2m->p_clk (this->p_clk);
569	int_router_p2m->p_resetn (this->p_resetn);
570	int_router_cla->p_clk (this->p_clk);
571	int_router_cla->p_resetn (this->p_resetn);
572
573	// loop on N/S/E/W ports
574	for (size_t i = 0; i < 4; i++)
575	{
576	int_router_cmd->p_out[i] (this->p_dspin_int_cmd_out[i]);
577	int_router_cmd->p_in[i] (this->p_dspin_int_cmd_in[i]);
578
579	int_router_rsp->p_out[i] (this->p_dspin_int_rsp_out[i]);
580	int_router_rsp->p_in[i] (this->p_dspin_int_rsp_in[i]);
581
582	int_router_m2p->p_out[i] (this->p_dspin_int_m2p_out[i]);
583	int_router_m2p->p_in[i] (this->p_dspin_int_m2p_in[i]);
584
585	int_router_p2m->p_out[i] (this->p_dspin_int_p2m_out[i]);
586	int_router_p2m->p_in[i] (this->p_dspin_int_p2m_in[i]);
587
588	int_router_cla->p_out[i] (this->p_dspin_int_cla_out[i]);
589	int_router_cla->p_in[i] (this->p_dspin_int_cla_in[i]);
590	}
591
592	int_router_cmd->p_out[4] (signal_int_dspin_cmd_g2l_d);
593	int_router_cmd->p_in[4] (signal_int_dspin_cmd_l2g_d);
594
595	int_router_rsp->p_out[4] (signal_int_dspin_rsp_g2l_d);
596	int_router_rsp->p_in[4] (signal_int_dspin_rsp_l2g_d);
597
598	int_router_m2p->p_out[4] (signal_int_dspin_m2p_g2l_c);
599	int_router_m2p->p_in[4] (signal_int_dspin_m2p_l2g_c);
600
601	int_router_p2m->p_out[4] (signal_int_dspin_p2m_g2l_c);
602	int_router_p2m->p_in[4] (signal_int_dspin_p2m_l2g_c);
603
604	int_router_cla->p_out[4] (signal_int_dspin_cla_g2l_c);
605	int_router_cla->p_in[4] (signal_int_dspin_cla_l2g_c);
606
607	std::cout << " - internal routers connected" << std::endl;
608
609
610	///////////////////// CMD DSPIN local crossbar direct
611	int_xbar_d->p_clk (this->p_clk);
612	int_xbar_d->p_resetn (this->p_resetn);
613	int_xbar_d->p_initiator_to_up (signal_int_vci_l2g);
614	int_xbar_d->p_target_to_up (signal_int_vci_g2l);
615
616	int_xbar_d->p_to_target[int_memc_tgt_id] (signal_int_vci_tgt_memc);
617	int_xbar_d->p_to_target[int_xicu_tgt_id] (signal_int_vci_tgt_xicu);
618	int_xbar_d->p_to_target[int_mdma_tgt_id] (signal_int_vci_tgt_mdma);
619	int_xbar_d->p_to_initiator[int_mdma_ini_id] (signal_int_vci_ini_mdma);
620	for (size_t p = 0; p < nb_procs; p++)
621	int_xbar_d->p_to_initiator[int_proc_ini_id + p] (signal_int_vci_ini_proc[p]);
622
623	if ( is_io )
624	{
625	int_xbar_d->p_to_target[int_iobx_tgt_id] (signal_int_vci_tgt_iobx);
626	int_xbar_d->p_to_initiator[int_iobx_ini_id] (signal_int_vci_ini_iobx);
627	}
628
629	int_wi_gate_d->p_clk (this->p_clk);
630	int_wi_gate_d->p_resetn (this->p_resetn);
631	int_wi_gate_d->p_vci (signal_int_vci_l2g);
632	int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d);
633	int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d);
634
635	int_wt_gate_d->p_clk (this->p_clk);
636	int_wt_gate_d->p_resetn (this->p_resetn);
637	int_wt_gate_d->p_vci (signal_int_vci_g2l);
638	int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d);
639	int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d);
640
641	////////////////////// M2P DSPIN local crossbar coherence
642	int_xbar_m2p_c->p_clk (this->p_clk);
643	int_xbar_m2p_c->p_resetn (this->p_resetn);
644	int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c);
645	int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c);
646	int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc);
647	for (size_t p = 0; p < nb_procs; p++)
648	int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]);
649
650	////////////////////////// P2M DSPIN local crossbar coherence
651	int_xbar_p2m_c->p_clk (this->p_clk);
652	int_xbar_p2m_c->p_resetn (this->p_resetn);
653	int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c);
654	int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c);
655	int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc);
656	for (size_t p = 0; p < nb_procs; p++)
657	int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]);
658
659	////////////////////// CLACK DSPIN local crossbar coherence
660	int_xbar_clack_c->p_clk (this->p_clk);
661	int_xbar_clack_c->p_resetn (this->p_resetn);
662	int_xbar_clack_c->p_global_out (signal_int_dspin_cla_l2g_c);
663	int_xbar_clack_c->p_global_in (signal_int_dspin_cla_g2l_c);
664	int_xbar_clack_c->p_local_in[0] (signal_int_dspin_cla_memc);
665	for (size_t p = 0; p < nb_procs; p++)
666	int_xbar_clack_c->p_local_out[p] (signal_int_dspin_cla_proc[p]);
667
668
669	///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1.
670	if ( is_io )
671	{
672	// IO bridge
673	iob->p_clk (this->p_clk);
674	iob->p_resetn (this->p_resetn);
675	iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini));
676	iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt));
677	iob->p_vci_tgt_int (signal_int_vci_tgt_iobx);
678	iob->p_vci_ini_int (signal_int_vci_ini_iobx);
679	iob->p_vci_ini_ram (signal_ram_vci_ini_iobx);
680
681	// initiator wrapper to RAM network
682	iob_ram_wi->p_clk (this->p_clk);
683	iob_ram_wi->p_resetn (this->p_resetn);
684	iob_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_iob_i);
685	iob_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_iob_i);
686	iob_ram_wi->p_vci (signal_ram_vci_ini_iobx);
687
688	// crossbar between MEMC and IOB to RAM network
689	ram_xbar_cmd->p_clk (this->p_clk);
690	ram_xbar_cmd->p_resetn (this->p_resetn);
691	ram_xbar_cmd->p_global_out (signal_ram_dspin_cmd_xbar);
692	ram_xbar_cmd->p_global_in (signal_ram_dspin_cmd_false);
693	ram_xbar_cmd->p_local_in[ram_memc_ini_id] (signal_ram_dspin_cmd_memc_i);
694	ram_xbar_cmd->p_local_in[ram_iobx_ini_id] (signal_ram_dspin_cmd_iob_i);
695
696	ram_xbar_rsp->p_clk (this->p_clk);
697	ram_xbar_rsp->p_resetn (this->p_resetn);
698	ram_xbar_rsp->p_global_out (signal_ram_dspin_rsp_false);
699	ram_xbar_rsp->p_global_in (signal_ram_dspin_rsp_xbar);
700	ram_xbar_rsp->p_local_out[ram_memc_ini_id] (signal_ram_dspin_rsp_memc_i);
701	ram_xbar_rsp->p_local_out[ram_iobx_ini_id] (signal_ram_dspin_rsp_iob_i);
702	}
703
704	SC_METHOD(init);
705	dont_initialize();
706
707	} // end constructor
708
709	tmpl(void)::init()
710	{
711	signal_ram_dspin_cmd_false.write = false;
712	signal_ram_dspin_rsp_false.read = true;
713	}
714
715	}}
716
717
718	// Local Variables:
719	// tab-width: 3
720	// c-basic-offset: 3
721	// c-file-offsets:((innamespace . 0)(inline-open . 0))
722	// indent-tabs-mode: nil
723	// End:
724
725	// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
726

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source: trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp

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