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source: trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp @ 693

Last change on this file since 693 was 693, checked in by cfuguet, 10 years ago

tsar_generic_iob:

Replacing tsar_iob_cluster dspin_local_crossbar by vci_local_crossbar (Direct Network)

Display real simulation clock frequency in top.cpp

File size: 31.6 KB

Line
1	//////////////////////////////////////////////////////////////////////////////
2	// File: tsar_iob_cluster.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : april 2013
6	// This program is released under the GNU public license
7	//////////////////////////////////////////////////////////////////////////////
8	// Cluster(0,0) & Cluster(xmax-1,ymax-1) contains the IOB0 & IOB1 components.
9	// These two clusters contain 6 extra components:
10	// - 1 vci_io_bridge (connected to the 3 networks.
11	// - 3 vci_dspin_wrapper for the IOB.
12	// - 2 dspin_local_crossbar for commands and responses.
13	//////////////////////////////////////////////////////////////////////////////
14
15	#include "../include/tsar_iob_cluster.h"
16
17	namespace soclib { namespace caba {
18
19	//////////////////////////////////////////////////////////////////////////
20	// Constructor
21	//////////////////////////////////////////////////////////////////////////
22	template<typename vci_param_int,
23	typename vci_param_ext,
24	size_t dspin_int_cmd_width,
25	size_t dspin_int_rsp_width,
26	size_t dspin_ram_cmd_width,
27	size_t dspin_ram_rsp_width>
28	TsarIobCluster<vci_param_int,
29	vci_param_ext,
30	dspin_int_cmd_width,
31	dspin_int_rsp_width,
32	dspin_ram_cmd_width,
33	dspin_ram_rsp_width>::TsarIobCluster(
34	//////////////////////////////////////////////////////////////////////////
35	sc_module_name insname,
36	size_t nb_procs,
37	size_t nb_dmas,
38	size_t x_id,
39	size_t y_id,
40	size_t xmax,
41	size_t ymax,
42
43	const soclib::common::MappingTable &mt_int,
44	const soclib::common::MappingTable &mt_ram,
45	const soclib::common::MappingTable &mt_iox,
46
47	size_t x_width,
48	size_t y_width,
49	size_t l_width,
50
51	size_t memc_int_tgtid, // local index
52	size_t xicu_int_tgtid, // local index
53	size_t mdma_int_tgtid, // local index
54	size_t iobx_int_tgtid, // local index
55
56	size_t proc_int_srcid, // local index
57	size_t mdma_int_srcid, // local index
58	size_t iobx_int_srcid, // local index
59
60	size_t xram_ram_tgtid, // local index
61
62	size_t memc_ram_srcid, // local index
63	size_t iobx_ram_srcid, // local index
64
65	size_t memc_ways,
66	size_t memc_sets,
67	size_t l1_i_ways,
68	size_t l1_i_sets,
69	size_t l1_d_ways,
70	size_t l1_d_sets,
71	size_t xram_latency,
72
73	const Loader &loader,
74
75	uint32_t frozen_cycles,
76	uint32_t debug_start_cycle,
77	bool memc_debug_ok,
78	bool proc_debug_ok,
79	bool iob_debug_ok )
80	: soclib::caba::BaseModule(insname),
81	p_clk("clk"),
82	p_resetn("resetn")
83	{
84	assert( (x_id < xmax) and (y_id < ymax) and "Illegal cluster coordinates");
85
86	size_t cluster_id = (x_id<<4) + y_id;
87
88	size_t cluster_iob0 = 0; // South-West cluster
89	size_t cluster_iob1 = ((xmax-1)<<4) + ymax-1; // North-East cluster
90
91	// Vectors of DSPIN ports for inter-cluster communications
92	p_dspin_int_cmd_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4, 3);
93	p_dspin_int_cmd_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4, 3);
94	p_dspin_int_rsp_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4, 2);
95	p_dspin_int_rsp_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4, 2);
96
97	p_dspin_ram_cmd_in = alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4);
98	p_dspin_ram_cmd_out = alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4);
99	p_dspin_ram_rsp_in = alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4);
100	p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4);
101
102	// ports in cluster_iob0 and cluster_iob1 only
103	if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) )
104	{
105	// VCI ports from IOB to IOX network
106	p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>;
107	p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>;
108
109	// DSPIN ports from IOB to RAM network
110	p_dspin_iob_cmd_out = new soclib::caba::DspinOutput<dspin_ram_cmd_width>;
111	p_dspin_iob_rsp_in = new soclib::caba::DspinInput<dspin_ram_rsp_width>;
112	}
113
114	// IRQ ports in cluster_iob0 only
115	if ( cluster_id == cluster_iob0 )
116	{
117	for ( size_t n=0 ; n<32 ; n++ ) p_irq[n] = new sc_in<bool>;
118	}
119
120	/////////////////////////////////////////////////////////////////////////////
121	// Hardware components
122	/////////////////////////////////////////////////////////////////////////////
123
124	//////////// PROCS
125	for (size_t p = 0; p < nb_procs; p++)
126	{
127	std::ostringstream s_proc;
128	s_proc << "proc_" << x_id << "_" << y_id << "_" << p;
129	proc[p] = new VciCcVCacheWrapper<vci_param_int,
130	dspin_int_cmd_width,
131	dspin_int_rsp_width,
132	GdbServer<Mips32ElIss> >(
133	s_proc.str().c_str(),
134	cluster_id*nb_procs + p, // GLOBAL PROC_ID
135	mt_int, // Mapping Table INT network
136	IntTab(cluster_id,p), // SRCID
137	(cluster_id << l_width) + p, // CC_GLOBAL_ID
138	8, // ITLB ways
139	8, // ITLB sets
140	8, // DTLB ways
141	8, // DTLB sets
142	l1_i_ways,l1_i_sets,16, // ICACHE size
143	l1_d_ways,l1_d_sets,16, // DCACHE size
144	4, // WBUF nlines
145	4, // WBUF nwords
146	x_width,
147	y_width,
148	frozen_cycles, // max frozen cycles
149	debug_start_cycle,
150	proc_debug_ok);
151	}
152
153	/////////// MEMC
154	std::ostringstream s_memc;
155	s_memc << "memc_" << x_id << "_" << y_id;
156	memc = new VciMemCache<vci_param_int,
157	vci_param_ext,
158	dspin_int_rsp_width,
159	dspin_int_cmd_width>(
160	s_memc.str().c_str(),
161	mt_int, // Mapping Table INT network
162	mt_ram, // Mapping Table RAM network
163	IntTab(cluster_id, memc_ram_srcid), // SRCID RAM network
164	IntTab(cluster_id, memc_int_tgtid), // TGTID INT network
165	x_width, // number of bits for x coordinate
166	y_width, // number of bits for y coordinate
167	memc_ways, memc_sets, 16, // CACHE SIZE
168	3, // MAX NUMBER OF COPIES
169	4096, // HEAP SIZE
170	8, // TRANSACTION TABLE DEPTH
171	8, // UPDATE TABLE DEPTH
172	8, // INVALIDATE TABLE DEPTH
173	debug_start_cycle,
174	memc_debug_ok );
175
176	std::ostringstream s_wi_memc;
177	s_wi_memc << "memc_wi_" << x_id << "_" << y_id;
178	memc_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
179	dspin_ram_cmd_width,
180	dspin_ram_rsp_width>(
181	s_wi_memc.str().c_str(),
182	x_width + y_width + l_width);
183
184	/////////// XICU
185	std::ostringstream s_xicu;
186	s_xicu << "xicu_" << x_id << "_" << y_id;
187	xicu = new VciXicu<vci_param_int>(
188	s_xicu.str().c_str(),
189	mt_int, // mapping table INT network
190	IntTab(cluster_id,xicu_int_tgtid), // TGTID direct space
191	32, // number of timer IRQs
192	32, // number of hard IRQs
193	32, // number of soft IRQs
194	nb_procs); // number of output IRQs
195
196	//////////// MDMA
197	std::ostringstream s_mdma;
198	s_mdma << "mdma_" << x_id << "_" << y_id;
199	mdma = new VciMultiDma<vci_param_int>(
200	s_mdma.str().c_str(),
201	mt_int,
202	IntTab(cluster_id, nb_procs), // SRCID
203	IntTab(cluster_id, mdma_int_tgtid), // TGTID
204	64, // burst size
205	nb_dmas); // number of IRQs
206
207	/////////// Direct LOCAL_XBAR(S)
208	size_t nb_direct_initiators = nb_procs + 1;
209	size_t nb_direct_targets = 3;
210	if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) )
211	{
212	nb_direct_initiators = nb_procs + 2;
213	nb_direct_targets = 4;
214	}
215
216	std::ostringstream s_int_xbar_d;
217	s_int_xbar_d << "int_xbar_cmd_d_" << x_id << "_" << y_id;
218	int_xbar_d = new VciLocalCrossbar<vci_param_int>(
219	s_int_xbar_d.str().c_str(),
220	mt_int, // mapping table
221	cluster_id, // cluster id
222	nb_direct_initiators, // number of local initiators
223	nb_direct_targets, // number of local targets
224	0 ); // default target
225
226	std::ostringstream s_int_dspin_ini_wrapper_gate_d;
227	s_int_dspin_ini_wrapper_gate_d << "int_dspin_ini_wrapper_gate_d_"
228	<< x_id << "_" << y_id;
229	int_wi_gate_d = new VciDspinInitiatorWrapper<vci_param_int,
230	dspin_int_cmd_width,
231	dspin_int_rsp_width>(
232	s_int_dspin_ini_wrapper_gate_d.str().c_str(),
233	x_width + y_width + l_width);
234
235	std::ostringstream s_int_dspin_tgt_wrapper_gate_d;
236	s_int_dspin_tgt_wrapper_gate_d << "int_dspin_tgt_wrapper_gate_d_"
237	<< x_id << "_" << y_id;
238	int_wt_gate_d = new VciDspinTargetWrapper<vci_param_int,
239	dspin_int_cmd_width,
240	dspin_int_rsp_width>(
241	s_int_dspin_tgt_wrapper_gate_d.str().c_str(),
242	x_width + y_width + l_width);
243
244
245	//////////// Coherence LOCAL_XBAR(S)
246	std::ostringstream s_int_xbar_m2p_c;
247	s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id;
248	int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
249	s_int_xbar_m2p_c.str().c_str(),
250	mt_int, // mapping table
251	x_id, y_id, // cluster coordinates
252	x_width, y_width, l_width, // several dests
253	1, // number of local sources
254	nb_procs, // number of local dests
255	2, 2, // fifo depths
256	true, // pseudo CMD
257	false, // no routing table
258	true ); // broacast
259
260	std::ostringstream s_int_xbar_p2m_c;
261	s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id;
262	int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>(
263	s_int_xbar_p2m_c.str().c_str(),
264	mt_int, // mapping table
265	x_id, y_id, // cluster coordinates
266	x_width, y_width, 0, // only one dest
267	nb_procs, // number of local sources
268	1, // number of local dests
269	2, 2, // fifo depths
270	false, // pseudo RSP
271	false, // no routing table
272	false ); // no broacast
273
274	std::ostringstream s_int_xbar_clack_c;
275	s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id;
276	int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
277	s_int_xbar_clack_c.str().c_str(),
278	mt_int, // mapping table
279	x_id, y_id, // cluster coordinates
280	x_width, y_width, l_width,
281	1, // number of local sources
282	nb_procs, // number of local targets
283	1, 1, // fifo depths
284	true, // CMD
285	false, // don't use local routing table
286	false); // broadcast
287
288	////////////// INT ROUTER(S)
289	std::ostringstream s_int_router_cmd;
290	s_int_router_cmd << "router_cmd_" << x_id << "_" << y_id;
291	int_router_cmd = new VirtualDspinRouter<dspin_int_cmd_width>(
292	s_int_router_cmd.str().c_str(),
293	x_id,y_id, // coordinate in the mesh
294	x_width, y_width, // x & y fields width
295	3, // nb virtual channels
296	4,4); // input & output fifo depths
297
298	std::ostringstream s_int_router_rsp;
299	s_int_router_rsp << "router_rsp_" << x_id << "_" << y_id;
300	int_router_rsp = new VirtualDspinRouter<dspin_int_rsp_width>(
301	s_int_router_rsp.str().c_str(),
302	x_id,y_id, // router coordinates in mesh
303	x_width, y_width, // x & y fields width
304	2, // nb virtual channels
305	4,4); // input & output fifo depths
306
307	////////////// XRAM
308	std::ostringstream s_xram;
309	s_xram << "xram_" << x_id << "_" << y_id;
310	xram = new VciSimpleRam<vci_param_ext>(
311	s_xram.str().c_str(),
312	IntTab(cluster_id, xram_ram_tgtid ),
313	mt_ram,
314	loader,
315	xram_latency);
316
317	std::ostringstream s_wt_xram;
318	s_wt_xram << "xram_wt_" << x_id << "_" << y_id;
319	xram_ram_wt = new VciDspinTargetWrapper<vci_param_ext,
320	dspin_ram_cmd_width,
321	dspin_ram_rsp_width>(
322	s_wt_xram.str().c_str(),
323	x_width + y_width + l_width);
324
325	///////////// RAM ROUTER(S)
326	std::ostringstream s_ram_router_cmd;
327	s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id;
328	size_t is_iob0 = (x_id == 0) and (y_id == 0);
329	size_t is_iob1 = (x_id == (xmax-1)) and (y_id == (ymax-1));
330	ram_router_cmd = new DspinRouterTsar<dspin_ram_cmd_width>(
331	s_ram_router_cmd.str().c_str(),
332	x_id, y_id, // router coordinates in mesh
333	x_width, // x field width in first flit
334	y_width, // y field width in first flit
335	4, 4, // input & output fifo depths
336	is_iob0, // cluster contains IOB0
337	is_iob1, // cluster contains IOB1
338	false, // not a response router
339	l_width); // local field width in first flit
340
341	std::ostringstream s_ram_router_rsp;
342	s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id;
343	ram_router_rsp = new DspinRouterTsar<dspin_ram_rsp_width>(
344	s_ram_router_rsp.str().c_str(),
345	x_id, y_id, // coordinates in mesh
346	x_width, // x field width in first flit
347	y_width, // y field width in first flit
348	4, 4, // input & output fifo depths
349	is_iob0, // cluster contains IOB0
350	is_iob1, // cluster contains IOB1
351	true, // response router
352	l_width); // local field width in first flit
353
354
355	////////////////////// I/O CLUSTER ONLY ///////////////////////
356	if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) )
357	{
358	/////////// IO_BRIDGE
359	size_t iox_local_id;
360	size_t global_id;
361	bool has_irqs;
362	if ( cluster_id == cluster_iob0 )
363	{
364	iox_local_id = 0;
365	global_id = cluster_iob0;
366	has_irqs = true;
367	}
368	else
369	{
370	iox_local_id = 1;
371	global_id = cluster_iob1;
372	has_irqs = false;
373	}
374
375	std::ostringstream s_iob;
376	s_iob << "iob_" << x_id << "_" << y_id;
377	iob = new VciIoBridge<vci_param_int,
378	vci_param_ext>(
379	s_iob.str().c_str(),
380	mt_ram, // EXT network maptab
381	mt_int, // INT network maptab
382	mt_iox, // IOX network maptab
383	IntTab( global_id, iobx_int_tgtid ), // INT TGTID
384	IntTab( global_id, iobx_int_srcid ), // INT SRCID
385	IntTab( global_id, iox_local_id ), // IOX TGTID
386	has_irqs,
387	16, // cache line words
388	8, // IOTLB ways
389	8, // IOTLB sets
390	debug_start_cycle,
391	iob_debug_ok );
392
393	std::ostringstream s_iob_ram_wi;
394	s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id;
395	iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
396	dspin_ram_cmd_width,
397	dspin_ram_rsp_width>(
398	s_iob_ram_wi.str().c_str(),
399	x_width + y_width + l_width);
400	} // end if IO
401
402	////////////////////////////////////
403	// Connections are defined here
404	////////////////////////////////////
405
406	// on coherence network : local srcid[proc] in [0...nb_procs-1]
407	// : local srcid[memc] = nb_procs
408	// In cluster_iob0, 32 HWI interrupts from external peripherals
409	// are connected to the XICU ports p_hwi[0:31]
410	// In other clusters, no HWI interrupts are connected to XICU
411
412	//////////////////////// internal CMD & RSP routers
413	int_router_cmd->p_clk (this->p_clk);
414	int_router_cmd->p_resetn (this->p_resetn);
415	int_router_rsp->p_clk (this->p_clk);
416	int_router_rsp->p_resetn (this->p_resetn);
417
418	for (int i = 0; i < 4; i++)
419	{
420	for(int k = 0; k < 3; k++)
421	{
422	int_router_cmd->p_out[i][k] (this->p_dspin_int_cmd_out[i][k]);
423	int_router_cmd->p_in[i][k] (this->p_dspin_int_cmd_in[i][k]);
424	}
425
426	for(int k = 0; k < 2; k++)
427	{
428	int_router_rsp->p_out[i][k] (this->p_dspin_int_rsp_out[i][k]);
429	int_router_rsp->p_in[i][k] (this->p_dspin_int_rsp_in[i][k]);
430	}
431	}
432
433	// local ports
434	int_router_cmd->p_out[4][0] (signal_int_dspin_cmd_g2l_d);
435	int_router_cmd->p_out[4][1] (signal_int_dspin_m2p_g2l_c);
436	int_router_cmd->p_out[4][2] (signal_int_dspin_clack_g2l_c);
437	int_router_cmd->p_in[4][0] (signal_int_dspin_cmd_l2g_d);
438	int_router_cmd->p_in[4][1] (signal_int_dspin_m2p_l2g_c);
439	int_router_cmd->p_in[4][2] (signal_int_dspin_clack_l2g_c);
440
441	int_router_rsp->p_out[4][0] (signal_int_dspin_rsp_g2l_d);
442	int_router_rsp->p_out[4][1] (signal_int_dspin_p2m_g2l_c);
443	int_router_rsp->p_in[4][0] (signal_int_dspin_rsp_l2g_d);
444	int_router_rsp->p_in[4][1] (signal_int_dspin_p2m_l2g_c);
445
446	///////////////////// CMD DSPIN local crossbar direct
447	int_xbar_d->p_clk (this->p_clk);
448	int_xbar_d->p_resetn (this->p_resetn);
449	int_xbar_d->p_initiator_to_up (signal_int_vci_l2g);
450	int_xbar_d->p_target_to_up (signal_int_vci_g2l);
451
452	int_xbar_d->p_to_target[memc_int_tgtid] (signal_int_vci_tgt_memc);
453	int_xbar_d->p_to_target[xicu_int_tgtid] (signal_int_vci_tgt_xicu);
454	int_xbar_d->p_to_target[mdma_int_tgtid] (signal_int_vci_tgt_mdma);
455	int_xbar_d->p_to_initiator[mdma_int_srcid] (signal_int_vci_ini_mdma);
456	for (size_t p = 0; p < nb_procs; p++)
457	int_xbar_d->p_to_initiator[proc_int_srcid + p] (signal_int_vci_ini_proc[p]);
458
459	if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) )
460	{
461	int_xbar_d->p_to_target[iobx_int_tgtid] (signal_int_vci_tgt_iobx);
462	int_xbar_d->p_to_initiator[iobx_int_srcid] (signal_int_vci_ini_iobx);
463	}
464
465	int_wi_gate_d->p_clk (this->p_clk);
466	int_wi_gate_d->p_resetn (this->p_resetn);
467	int_wi_gate_d->p_vci (signal_int_vci_l2g);
468	int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d);
469	int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d);
470
471	int_wt_gate_d->p_clk (this->p_clk);
472	int_wt_gate_d->p_resetn (this->p_resetn);
473	int_wt_gate_d->p_vci (signal_int_vci_g2l);
474	int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d);
475	int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d);
476
477	////////////////////// M2P DSPIN local crossbar coherence
478	int_xbar_m2p_c->p_clk (this->p_clk);
479	int_xbar_m2p_c->p_resetn (this->p_resetn);
480	int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c);
481	int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c);
482	int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc);
483	for (size_t p = 0; p < nb_procs; p++)
484	int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]);
485
486	////////////////////////// P2M DSPIN local crossbar coherence
487	int_xbar_p2m_c->p_clk (this->p_clk);
488	int_xbar_p2m_c->p_resetn (this->p_resetn);
489	int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c);
490	int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c);
491	int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc);
492	for (size_t p = 0; p < nb_procs; p++)
493	int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]);
494
495	////////////////////// CLACK DSPIN local crossbar coherence
496	int_xbar_clack_c->p_clk (this->p_clk);
497	int_xbar_clack_c->p_resetn (this->p_resetn);
498	int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c);
499	int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c);
500	int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc);
501	for (size_t p = 0; p < nb_procs; p++)
502	int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]);
503
504	//////////////////////////////////// Processors
505	for (size_t p = 0; p < nb_procs; p++)
506	{
507	proc[p]->p_clk (this->p_clk);
508	proc[p]->p_resetn (this->p_resetn);
509	proc[p]->p_vci (signal_int_vci_ini_proc[p]);
510	proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]);
511	proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]);
512	proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]);
513	proc[p]->p_irq[0] (signal_proc_it[p]);
514	for ( size_t j = 1 ; j < 6 ; j++)
515	{
516	proc[p]->p_irq[j] (signal_false);
517	}
518	}
519
520	///////////////////////////////////// XICU
521	xicu->p_clk (this->p_clk);
522	xicu->p_resetn (this->p_resetn);
523	xicu->p_vci (signal_int_vci_tgt_xicu);
524	for ( size_t p=0 ; p<nb_procs ; p++)
525	{
526	xicu->p_irq[p] (signal_proc_it[p]);
527	}
528	for ( size_t i=0 ; i<32 ; i++)
529	{
530	if (cluster_id == cluster_iob0)
531	xicu->p_hwi[i] (*(this->p_irq[i]));
532	else
533	xicu->p_hwi[i] (signal_false);
534	}
535
536	///////////////////////////////////// MEMC
537	memc->p_clk (this->p_clk);
538	memc->p_resetn (this->p_resetn);
539	memc->p_vci_ixr (signal_ram_vci_ini_memc);
540	memc->p_vci_tgt (signal_int_vci_tgt_memc);
541	memc->p_dspin_p2m (signal_int_dspin_p2m_memc);
542	memc->p_dspin_m2p (signal_int_dspin_m2p_memc);
543	memc->p_dspin_clack (signal_int_dspin_clack_memc);
544	memc->p_irq (signal_irq_memc);
545
546	// wrapper to RAM network
547	memc_ram_wi->p_clk (this->p_clk);
548	memc_ram_wi->p_resetn (this->p_resetn);
549	memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i);
550	memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i);
551	memc_ram_wi->p_vci (signal_ram_vci_ini_memc);
552
553	//////////////////////////////////// XRAM
554	xram->p_clk (this->p_clk);
555	xram->p_resetn (this->p_resetn);
556	xram->p_vci (signal_ram_vci_tgt_xram);
557
558	// wrapper to RAM network
559	xram_ram_wt->p_clk (this->p_clk);
560	xram_ram_wt->p_resetn (this->p_resetn);
561	xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t);
562	xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t);
563	xram_ram_wt->p_vci (signal_ram_vci_tgt_xram);
564
565	/////////////////////////////////// MDMA
566	mdma->p_clk (this->p_clk);
567	mdma->p_resetn (this->p_resetn);
568	mdma->p_vci_target (signal_int_vci_tgt_mdma);
569	mdma->p_vci_initiator (signal_int_vci_ini_mdma);
570	for (size_t i=0 ; i<nb_dmas ; i++)
571	mdma->p_irq[i] (signal_irq_mdma[i]);
572
573	//////////////////////////// RAM network CMD & RSP routers
574	ram_router_cmd->p_clk (this->p_clk);
575	ram_router_cmd->p_resetn (this->p_resetn);
576	ram_router_rsp->p_clk (this->p_clk);
577	ram_router_rsp->p_resetn (this->p_resetn);
578	for( size_t n=0 ; n<4 ; n++)
579	{
580	ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]);
581	ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]);
582	ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]);
583	ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]);
584	}
585	ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t);
586	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i);
587	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i);
588	ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t);
589
590	///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1.
591	if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) )
592	{
593	// IO bridge
594	iob->p_clk (this->p_clk);
595	iob->p_resetn (this->p_resetn);
596	iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini));
597	iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt));
598	iob->p_vci_tgt_int (signal_int_vci_tgt_iobx);
599	iob->p_vci_ini_int (signal_int_vci_ini_iobx);
600	iob->p_vci_ini_ram (signal_ram_vci_ini_iobx);
601
602	if ( cluster_id == cluster_iob0 )
603	for ( size_t n=0 ; n<32 ; n++ )
604	(iob->p_irq[n]) ((this->p_irq[n]));
605
606	// initiator wrapper to RAM network
607	iob_ram_wi->p_clk (this->p_clk);
608	iob_ram_wi->p_resetn (this->p_resetn);
609	iob_ram_wi->p_dspin_cmd (*(this->p_dspin_iob_cmd_out));
610	iob_ram_wi->p_dspin_rsp (*(this->p_dspin_iob_rsp_in));
611	iob_ram_wi->p_vci (signal_ram_vci_ini_iobx);
612	}
613
614	} // end constructor
615
616	}}
617
618
619	// Local Variables:
620	// tab-width: 3
621	// c-basic-offset: 3
622	// c-file-offsets:((innamespace . 0)(inline-open . 0))
623	// indent-tabs-mode: nil
624	// End:
625
626	// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
627
628
629

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Project-Id-Version: Trac 0.12
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POT-Creation-Date: 2018-07-07 16:55+0000
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