[621] | 1 | ///////////////////////////////////////////////////////////////////////// |
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| 2 | // File: top.cpp |
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| 3 | // Author: Alain Greiner |
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| 4 | // Copyright: UPMC/LIP6 |
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[628] | 5 | // Date : february 2014 |
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[621] | 6 | // This program is released under the GNU public license |
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| 7 | ///////////////////////////////////////////////////////////////////////// |
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| 8 | // This file define a generic TSAR architecture. |
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| 9 | // The processor is a MIPS32 processor wrapped in a GDB server |
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| 10 | // (this is defined in the tsar_xbar_cluster). |
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| 11 | // |
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| 12 | // The seg_reset_base and seg_kcode_base addresses are not constrained |
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| 13 | // to be 0xBFC00000 and 0x80000000. |
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| 14 | // |
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[628] | 15 | // It does not use an external ROM, as the boot code must be (pre)loaded |
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[621] | 16 | // in cluster (0,0) memory. |
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| 17 | // |
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| 18 | // The physical address space is 40 bits. |
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| 19 | // The 8 address MSB bits define the cluster index. |
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| 20 | // |
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[628] | 21 | // The main hardware parameters are the mesh size (X_SIZE / Y_SIZE), |
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| 22 | // and the number of ptocessors per cluster (NB_PROCS_MAX). |
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[621] | 23 | // The number of clusters cannot be larger than 256. |
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| 24 | // The number of processors per cluster cannot be larger than 4. |
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| 25 | // |
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[628] | 26 | // Each cluster contains: |
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| 27 | // - 5 dspin_local_crossbar (local interconnect) |
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| 28 | // - 5 dspin_router (global interconnect) |
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| 29 | // - up to 4 vci_cc_vcache wrapping a MIPS32 processor |
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| 30 | // - 1 vci_mem_cache |
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| 31 | // - 1 vci_xicu |
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| 32 | // - 1 vci_simple_ram (to model the L3 cache). |
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[621] | 33 | // |
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[628] | 34 | // Each processor receive 4 consecutive IRQ lines from the local XICU. |
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| 35 | // In all clusters, the MEMC IRQ line (signaling a late write error) |
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| 36 | // is connected to XICU HWI[8] |
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[621] | 37 | // |
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[628] | 38 | // The cluster 0 contains two more peripherals: |
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| 39 | // - one block device controller, whose IRQ is connected to XICU HWI[9]. |
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| 40 | // - one single channel TTY controller, whose IRQ is connected to XICU HWI[10]. |
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[621] | 41 | // |
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[628] | 42 | // The cluster internal architecture is defined in file tsar_leti_cluster, |
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| 43 | // that must be considered as an extension of this top.cpp file. |
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[621] | 44 | // |
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[628] | 45 | // Besides the hardware components contained in clusters, external peripherals |
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| 46 | // are connected to an external IO bus (implemented as a vci_local_crossbar): |
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| 47 | // - one disk controller |
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| 48 | // - one multi-channel ethernet controller |
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| 49 | // - one multi-channel chained buffer dma controller |
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| 50 | // - one multi-channel tty controller |
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| 51 | // - one frame buffer controller |
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| 52 | // - one 16 channels iopic controller |
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| 53 | // |
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| 54 | // This IOBUS is connected to the north port of the DIR_CMD |
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| 55 | // and DIR_RSP routers, in cluster(X_SIZE-1, Y_SIZE-1). |
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| 56 | // For all external peripherals, the hardware interrupts (HWI) are |
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| 57 | // translated to software interrupts (SWI) by the iopic component: |
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| 58 | // - IRQ_MNIC_RX[1:0] connected to IOPIC HWI[1:0] |
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| 59 | // - IRQ_MNIC_TX[1:0] connected to IOPIC HWI[3:2] |
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| 60 | // - IRQ_CDMA[3:0] connected to IOPIC HWI[7:4] |
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| 61 | // - IRQ_BDEV connected to IOPIC HWI[9] |
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| 62 | // - IRQ_MTTY[3:0] connected to IOPIC HWI[15:12] |
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| 63 | //////////////////////////////////////////////////////////////////////////// |
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| 64 | // The following parameters must be defined in the hard_config.h file : |
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[621] | 65 | // - X_WIDTH : number of bits for x coordinate (must be 4) |
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| 66 | // - Y_WIDTH : number of bits for y coordinate (must be 4) |
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| 67 | // - X_SIZE : number of clusters in a row |
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| 68 | // - Y_SIZE : number of clusters in a column |
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[628] | 69 | // - NB_PROCS_MAX : number of processors per cluster (1, 2 or 4) |
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| 70 | // - NB_CMA_CHANNELS : number of CMA channels in I/0 cluster (8 max) |
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| 71 | // - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (16 max) |
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| 72 | // - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (2 max) |
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| 73 | // - USE_EXT_IO : use external peripherals if non zero |
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[621] | 74 | // |
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| 75 | // Some other hardware parameters are not used when compiling the OS, |
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[628] | 76 | // and are only defined in this top.cpp file: |
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[621] | 77 | // - XRAM_LATENCY : external ram latency |
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| 78 | // - MEMC_WAYS : L2 cache number of ways |
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| 79 | // - MEMC_SETS : L2 cache number of sets |
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[628] | 80 | // - L1_IWAYS : L1 cache instruction number of ways |
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| 81 | // - L1_ISETS : L1 cache instruction number of sets |
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| 82 | // - L1_DWAYS : L1 cache data number of ways |
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| 83 | // - L1_DSETS : L1 cache data number of sets |
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[621] | 84 | // - FBUF_X_SIZE : width of frame buffer (pixels) |
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| 85 | // - FBUF_Y_SIZE : heigth of frame buffer (lines) |
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| 86 | // - BDEV_IMAGE_NAME : file pathname for block device |
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| 87 | // - NIC_RX_NAME : file pathname for NIC received packets |
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| 88 | // - NIC_TX_NAME : file pathname for NIC transmited packets |
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[628] | 89 | // - NIC_MAC4 : MAC address |
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| 90 | // - NIC_MAC2 : MAC address |
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[621] | 91 | ///////////////////////////////////////////////////////////////////////// |
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| 92 | // General policy for 40 bits physical address decoding: |
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| 93 | // All physical segments base addresses are multiple of 1 Mbytes |
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| 94 | // (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) |
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| 95 | // The (X_WIDTH + Y_WIDTH) MSB bits (left aligned) define |
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| 96 | // the cluster index, and the LADR bits define the local index: |
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| 97 | // |X_ID|Y_ID| LADR | OFFSET | |
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| 98 | // | 4 | 4 | 8 | 24 | |
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| 99 | ///////////////////////////////////////////////////////////////////////// |
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| 100 | // General policy for 14 bits SRCID decoding: |
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| 101 | // Each component is identified by (x_id, y_id, l_id) tuple. |
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| 102 | // |X_ID|Y_ID| L_ID | |
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| 103 | // | 4 | 4 | 6 | |
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| 104 | ///////////////////////////////////////////////////////////////////////// |
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| 105 | |
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| 106 | #include <systemc> |
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| 107 | #include <sys/time.h> |
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| 108 | #include <iostream> |
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| 109 | #include <sstream> |
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| 110 | #include <cstdlib> |
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| 111 | #include <cstdarg> |
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| 112 | #include <stdint.h> |
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| 113 | |
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| 114 | #include "gdbserver.h" |
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| 115 | #include "mapping_table.h" |
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| 116 | #include "tsar_leti_cluster.h" |
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[628] | 117 | #include "vci_local_crossbar.h" |
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| 118 | #include "vci_dspin_initiator_wrapper.h" |
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| 119 | #include "vci_dspin_target_wrapper.h" |
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| 120 | #include "vci_multi_tty.h" |
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| 121 | #include "vci_multi_nic.h" |
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| 122 | #include "vci_chbuf_dma.h" |
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| 123 | #include "vci_block_device_tsar.h" |
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| 124 | #include "vci_framebuffer.h" |
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| 125 | #include "vci_iopic.h" |
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[621] | 126 | #include "alloc_elems.h" |
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| 127 | |
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| 128 | /////////////////////////////////////////////////// |
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| 129 | // OS |
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| 130 | /////////////////////////////////////////////////// |
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| 131 | |
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| 132 | #define USE_GIET_VM 0 |
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| 133 | #define USE_GIET_TSAR 1 |
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| 134 | |
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| 135 | #if ( USE_GIET_VM and USE_GIET_TSAR ) |
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| 136 | #error "Can't use Two different OS" |
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| 137 | #endif |
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| 138 | |
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| 139 | #if ( (not USE_GIET_VM) and (not USE_GIET_TSAR) ) |
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| 140 | #error "You need to specify one OS" |
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| 141 | #endif |
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| 142 | |
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| 143 | /////////////////////////////////////////////////// |
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| 144 | // Parallelisation |
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| 145 | /////////////////////////////////////////////////// |
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| 146 | #define USE_OPENMP 0 |
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| 147 | |
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| 148 | #if USE_OPENMP |
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| 149 | #include <omp.h> |
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| 150 | #endif |
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| 151 | |
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| 152 | /////////////////////////////////////////////////// |
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| 153 | // cluster index (from x,y coordinates) |
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| 154 | /////////////////////////////////////////////////// |
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| 155 | |
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| 156 | #define cluster(x,y) (y + (x << Y_WIDTH)) |
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| 157 | |
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| 158 | #define min(a, b) (a < b ? a : b) |
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| 159 | |
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| 160 | /////////////////////////////////////////////////////////// |
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| 161 | // DSPIN parameters |
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| 162 | /////////////////////////////////////////////////////////// |
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| 163 | |
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| 164 | #define dspin_cmd_width 39 |
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| 165 | #define dspin_rsp_width 32 |
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| 166 | |
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| 167 | /////////////////////////////////////////////////////////// |
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| 168 | // VCI parameters |
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| 169 | /////////////////////////////////////////////////////////// |
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| 170 | |
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| 171 | #define vci_cell_width_int 4 |
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| 172 | #define vci_cell_width_ext 8 |
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| 173 | #define vci_address_width 40 |
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| 174 | #define vci_plen_width 8 |
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| 175 | #define vci_rerror_width 1 |
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| 176 | #define vci_clen_width 1 |
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| 177 | #define vci_rflag_width 1 |
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| 178 | #define vci_srcid_width 14 |
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| 179 | #define vci_pktid_width 4 |
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| 180 | #define vci_trdid_width 4 |
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| 181 | #define vci_wrplen_width 1 |
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| 182 | |
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| 183 | //////////////////////////////////////////////////////////// |
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| 184 | // Main Hardware Parameters values |
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| 185 | //////////////////////i///////////////////////////////////// |
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| 186 | |
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| 187 | #if USE_GIET_VM |
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| 188 | #include "giet_vm/hard_config.h" |
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| 189 | #endif |
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| 190 | |
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| 191 | #if USE_GIET_TSAR |
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[628] | 192 | #include "../../softs/soft_transpose_giet/hard_config.h" |
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[621] | 193 | #endif |
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| 194 | |
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| 195 | //////////////////////////////////////////////////////////// |
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| 196 | // Secondary Hardware Parameters |
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| 197 | //////////////////////i///////////////////////////////////// |
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| 198 | |
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| 199 | #define RESET_ADDRESS 0x0 |
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| 200 | |
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| 201 | #define XRAM_LATENCY 0 |
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| 202 | |
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| 203 | #define MEMC_WAYS 16 |
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| 204 | #define MEMC_SETS 256 |
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| 205 | |
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| 206 | #define L1_IWAYS 4 |
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| 207 | #define L1_ISETS 64 |
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| 208 | |
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| 209 | #define L1_DWAYS 4 |
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| 210 | #define L1_DSETS 64 |
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| 211 | |
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| 212 | #define FBUF_X_SIZE 128 |
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| 213 | #define FBUF_Y_SIZE 128 |
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| 214 | |
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[628] | 215 | #define BDEV_IMAGE_NAME "../../softs/soft_transpose_giet/images.raw" |
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[621] | 216 | |
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[628] | 217 | #define NIC_MAC4 0XBABEF00D |
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| 218 | #define NIC_MAC2 0xBEEF |
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[621] | 219 | #define NIC_RX_NAME "../../softs/soft_hello_giet/fake" |
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| 220 | #define NIC_TX_NAME "../../softs/soft_hello_giet/fake" |
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| 221 | |
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| 222 | #define NORTH 0 |
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| 223 | #define SOUTH 1 |
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| 224 | #define EAST 2 |
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| 225 | #define WEST 3 |
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| 226 | |
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| 227 | //////////////////////////////////////////////////////////// |
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| 228 | // Arguments for the SoCLib loader |
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| 229 | //////////////////////i///////////////////////////////////// |
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| 230 | |
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| 231 | #if USE_GIET_VM |
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| 232 | #define loader_args "TBD" |
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| 233 | #endif |
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| 234 | |
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| 235 | #if USE_GIET_TSAR |
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[628] | 236 | #define loader_args "../../softs/soft_transpose_giet/bin.soft" |
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[621] | 237 | #endif |
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| 238 | |
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| 239 | //////////////////////////////////////////////////////////// |
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| 240 | // DEBUG Parameters default values |
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| 241 | //////////////////////i///////////////////////////////////// |
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| 242 | |
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[628] | 243 | #define MAX_FROZEN_CYCLES 10000 |
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[621] | 244 | |
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| 245 | //////////////////////////////////////////////////////////////////// |
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[628] | 246 | // LOCAL TGTID & SRCID definition |
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[621] | 247 | // For all components: global TGTID = global SRCID = cluster_index |
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| 248 | //////////////////////////////////////////////////////////////////// |
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| 249 | |
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| 250 | #define MEMC_TGTID 0 |
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| 251 | #define XICU_TGTID 1 |
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[628] | 252 | #define MTTY_TGTID 2 |
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| 253 | #define BDEV_TGTID 3 |
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[621] | 254 | #define FBUF_TGTID 4 |
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[628] | 255 | #define MNIC_TGTID 5 |
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| 256 | #define CDMA_TGTID 6 |
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| 257 | #define IOPI_TGTID 7 |
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[621] | 258 | |
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[628] | 259 | #define BDEV_SRCID NB_PROCS_MAX |
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| 260 | #define CDMA_SRCID NB_PROCS_MAX + 1 |
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| 261 | #define IOPI_SRCID NB_PROCS_MAX + 2 |
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| 262 | |
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| 263 | ///////////////////////////////////////////////////////////////////// |
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[621] | 264 | // Physical segments definition |
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[628] | 265 | ///////////////////////////////////////////////////////////////////// |
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| 266 | // - 3 segments are replicated in all clusters |
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| 267 | // - 2 segments are replicated in cluster[0,0] & [X_SIZE-1,Y_SIZE-1] |
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| 268 | // - 4 segments are only in cluster [X_SIZE-1,Y_SIZE] |
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| 269 | // The following values are for segments in cluster 0, |
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| 270 | // and these 32 bits values must be concatenate with the cluster |
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[621] | 271 | // index (on 8 bits) to obtain the 40 bits address. |
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[628] | 272 | ///////////////////////////////////////////////////////////////////// |
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[621] | 273 | |
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[628] | 274 | // in cluster [0,0] & [X_SIZE-1,Y_SIZE] |
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[621] | 275 | |
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[628] | 276 | #define MTTY_BASE 0xF4000000 |
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| 277 | #define MTTY_SIZE 0x00001000 // 4 Kbytes |
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[621] | 278 | |
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[628] | 279 | #define BDEV_BASE 0xF2000000 |
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[621] | 280 | #define BDEV_SIZE 0x00001000 // 4 Kbytes |
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| 281 | |
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[628] | 282 | // in cluster [X_SIZE-1,Y_SIZE] |
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[621] | 283 | |
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[628] | 284 | #define FBUF_BASE 0xF3000000 |
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| 285 | #define FBUF_SIZE (FBUF_X_SIZE * FBUF_Y_SIZE * 2) |
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| 286 | |
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| 287 | #define MNIC_BASE 0xF7000000 |
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[621] | 288 | #define MNIC_SIZE 0x00800000 // 512 Kbytes (for 8 channels) |
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| 289 | |
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[628] | 290 | #define CDMA_BASE 0xF8000000 |
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[621] | 291 | #define CDMA_SIZE 0x00004000 * NB_CMA_CHANNELS |
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| 292 | |
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[628] | 293 | #define IOPI_BASE 0xF9000000 |
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| 294 | #define IOPI_SIZE 0x00001000 // 4 Kbytes |
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| 295 | |
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[621] | 296 | // replicated segments : address is extended to 40 bits by cluster_xy |
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| 297 | |
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| 298 | #define MEMC_BASE 0x00000000 |
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| 299 | #define MEMC_SIZE 0x01000000 // 16 Mbytes per cluster |
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| 300 | |
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[628] | 301 | #define MCFG_BASE 0xE0000000 |
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| 302 | #define MCFG_SIZE 0x00001000 // 4 Kbytes per cluster |
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| 303 | |
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[621] | 304 | #define XICU_BASE 0xF0000000 |
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[628] | 305 | #define XICU_SIZE 0x00001000 // 4 Kbytes per cluster |
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[621] | 306 | |
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| 307 | bool stop_called = false; |
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| 308 | |
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| 309 | ///////////////////////////////// |
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| 310 | int _main(int argc, char *argv[]) |
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| 311 | { |
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| 312 | using namespace sc_core; |
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| 313 | using namespace soclib::caba; |
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| 314 | using namespace soclib::common; |
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| 315 | |
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[628] | 316 | uint32_t ncycles = 0xFFFFFFFF; // max simulated cycles |
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| 317 | size_t threads = 1; // simulator's threads number |
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[621] | 318 | bool trace_ok = false; // trace activated |
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| 319 | uint32_t trace_from = 0; // trace start cycle |
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| 320 | bool trace_proc_ok = false; // detailed proc trace activated |
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| 321 | size_t trace_memc_ok = false; // detailed memc trace activated |
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| 322 | size_t trace_memc_id = 0; // index of memc to be traced |
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| 323 | size_t trace_proc_id = 0; // index of proc to be traced |
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| 324 | uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor |
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| 325 | struct timeval t1,t2; |
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| 326 | uint64_t ms1,ms2; |
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| 327 | |
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| 328 | ////////////// command line arguments ////////////////////// |
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| 329 | if (argc > 1) |
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| 330 | { |
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| 331 | for (int n = 1; n < argc; n = n + 2) |
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| 332 | { |
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| 333 | if ((strcmp(argv[n], "-NCYCLES") == 0) && (n + 1 < argc)) |
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| 334 | { |
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| 335 | ncycles = (uint64_t) strtol(argv[n + 1], NULL, 0); |
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| 336 | } |
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| 337 | else if ((strcmp(argv[n],"-DEBUG") == 0) && (n + 1 < argc)) |
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| 338 | { |
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| 339 | trace_ok = true; |
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| 340 | trace_from = (uint32_t) strtol(argv[n + 1], NULL, 0); |
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| 341 | } |
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| 342 | else if ((strcmp(argv[n], "-MEMCID") == 0) && (n + 1 < argc)) |
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| 343 | { |
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| 344 | trace_memc_ok = true; |
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| 345 | trace_memc_id = (size_t) strtol(argv[n + 1], NULL, 0); |
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| 346 | size_t x = trace_memc_id >> Y_WIDTH; |
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| 347 | size_t y = trace_memc_id & ((1<<Y_WIDTH)-1); |
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| 348 | |
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| 349 | assert( (x <= X_SIZE) and (y <= Y_SIZE) && |
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| 350 | "MEMCID parameter refers a not valid memory cache"); |
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| 351 | } |
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| 352 | else if ((strcmp(argv[n], "-PROCID") == 0) && (n + 1 < argc)) |
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| 353 | { |
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| 354 | trace_proc_ok = true; |
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| 355 | trace_proc_id = (size_t) strtol(argv[n + 1], NULL, 0); |
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| 356 | size_t cluster_xy = trace_proc_id / NB_PROCS_MAX ; |
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| 357 | size_t x = cluster_xy >> Y_WIDTH; |
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| 358 | size_t y = cluster_xy & ((1<<Y_WIDTH)-1); |
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| 359 | |
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| 360 | assert( (x <= X_SIZE) and (y <= Y_SIZE) && |
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| 361 | "PROCID parameter refers a not valid processor"); |
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| 362 | } |
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| 363 | else if ((strcmp(argv[n], "-THREADS") == 0) && ((n + 1) < argc)) |
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| 364 | { |
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[628] | 365 | threads = (size_t) strtol(argv[n + 1], NULL, 0); |
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| 366 | threads = (threads < 1) ? 1 : threads; |
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[621] | 367 | } |
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| 368 | else if ((strcmp(argv[n], "-FROZEN") == 0) && (n + 1 < argc)) |
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| 369 | { |
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| 370 | frozen_cycles = (uint32_t) strtol(argv[n + 1], NULL, 0); |
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| 371 | } |
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| 372 | else |
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| 373 | { |
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| 374 | std::cout << " Arguments are (key,value) couples." << std::endl; |
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| 375 | std::cout << " The order is not important." << std::endl; |
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| 376 | std::cout << " Accepted arguments are :" << std::endl << std::endl; |
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| 377 | std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl; |
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| 378 | std::cout << " -DEBUG debug_start_cycle" << std::endl; |
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| 379 | std::cout << " -THREADS simulator's threads number" << std::endl; |
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| 380 | std::cout << " -FROZEN max_number_of_lines" << std::endl; |
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| 381 | std::cout << " -PERIOD number_of_cycles between trace" << std::endl; |
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| 382 | std::cout << " -MEMCID index_memc_to_be_traced" << std::endl; |
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| 383 | std::cout << " -PROCID index_proc_to_be_traced" << std::endl; |
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| 384 | exit(0); |
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| 385 | } |
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| 386 | } |
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| 387 | } |
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| 388 | |
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| 389 | // checking hardware parameters |
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| 390 | assert( (X_SIZE <= 16) and |
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| 391 | "The X_SIZE parameter cannot be larger than 16" ); |
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| 392 | |
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| 393 | assert( (Y_SIZE <= 16) and |
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| 394 | "The Y_SIZE parameter cannot be larger than 16" ); |
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| 395 | |
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| 396 | assert( (NB_PROCS_MAX <= 8) and |
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[628] | 397 | "The NB_PROCS_MAX parameter cannot be larger than 4" ); |
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[621] | 398 | |
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[628] | 399 | assert( (NB_CMA_CHANNELS <= 4) and |
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| 400 | "The NB_CMA_CHANNELS parameter cannot be larger than 4" ); |
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[621] | 401 | |
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[628] | 402 | assert( (NB_TTY_CHANNELS <= 4) and |
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| 403 | "The NB_TTY_CHANNELS parameter cannot be larger than 4" ); |
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[621] | 404 | |
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[628] | 405 | assert( (NB_NIC_CHANNELS <= 2) and |
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| 406 | "The NB_NIC_CHANNELS parameter cannot be larger than 2" ); |
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[621] | 407 | |
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| 408 | assert( (vci_address_width == 40) and |
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| 409 | "VCI address width with the GIET must be 40 bits" ); |
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| 410 | |
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| 411 | assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and |
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| 412 | "ERROR: you must have X_WIDTH == Y_WIDTH == 4"); |
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| 413 | |
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| 414 | std::cout << std::endl; |
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| 415 | |
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| 416 | std::cout << " - X_SIZE = " << X_SIZE << std::endl; |
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| 417 | std::cout << " - Y_SIZE = " << Y_SIZE << std::endl; |
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| 418 | std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl; |
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| 419 | std::cout << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl; |
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| 420 | std::cout << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl; |
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| 421 | std::cout << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl; |
---|
| 422 | std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl; |
---|
| 423 | std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl; |
---|
| 424 | std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl; |
---|
| 425 | std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl; |
---|
| 426 | std::cout << " - MAX_CYCLES = " << ncycles << std::endl; |
---|
| 427 | std::cout << " - RESET_ADDRESS = " << RESET_ADDRESS << std::endl; |
---|
[628] | 428 | std::cout << " - SOFT_FILENAME = " << loader_args << std::endl; |
---|
[621] | 429 | |
---|
| 430 | std::cout << std::endl; |
---|
| 431 | |
---|
| 432 | // Internal and External VCI parameters definition |
---|
| 433 | typedef soclib::caba::VciParams<vci_cell_width_int, |
---|
| 434 | vci_plen_width, |
---|
| 435 | vci_address_width, |
---|
| 436 | vci_rerror_width, |
---|
| 437 | vci_clen_width, |
---|
| 438 | vci_rflag_width, |
---|
| 439 | vci_srcid_width, |
---|
| 440 | vci_pktid_width, |
---|
| 441 | vci_trdid_width, |
---|
| 442 | vci_wrplen_width> vci_param_int; |
---|
| 443 | |
---|
| 444 | typedef soclib::caba::VciParams<vci_cell_width_ext, |
---|
| 445 | vci_plen_width, |
---|
| 446 | vci_address_width, |
---|
| 447 | vci_rerror_width, |
---|
| 448 | vci_clen_width, |
---|
| 449 | vci_rflag_width, |
---|
| 450 | vci_srcid_width, |
---|
| 451 | vci_pktid_width, |
---|
| 452 | vci_trdid_width, |
---|
| 453 | vci_wrplen_width> vci_param_ext; |
---|
| 454 | |
---|
| 455 | #if USE_OPENMP |
---|
| 456 | omp_set_dynamic(false); |
---|
[628] | 457 | omp_set_num_threads(threads); |
---|
[621] | 458 | std::cerr << "Built with openmp version " << _OPENMP << std::endl; |
---|
| 459 | #endif |
---|
| 460 | |
---|
| 461 | |
---|
[628] | 462 | /////////////////////////////////////// |
---|
| 463 | // Direct Network Mapping Table |
---|
| 464 | /////////////////////////////////////// |
---|
[621] | 465 | |
---|
| 466 | MappingTable maptabd(vci_address_width, |
---|
| 467 | IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH), |
---|
| 468 | IntTab(X_WIDTH + Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH), |
---|
[628] | 469 | 0x00FF000000ULL); |
---|
[621] | 470 | |
---|
[628] | 471 | // replicated segments |
---|
[621] | 472 | for (size_t x = 0; x < X_SIZE; x++) |
---|
| 473 | { |
---|
| 474 | for (size_t y = 0; y < Y_SIZE; y++) |
---|
| 475 | { |
---|
| 476 | sc_uint<vci_address_width> offset; |
---|
[628] | 477 | offset = ((sc_uint<vci_address_width>)cluster(x,y)) << 32; |
---|
[621] | 478 | |
---|
| 479 | std::ostringstream si; |
---|
| 480 | si << "seg_xicu_" << x << "_" << y; |
---|
| 481 | maptabd.add(Segment(si.str(), XICU_BASE + offset, XICU_SIZE, |
---|
| 482 | IntTab(cluster(x,y),XICU_TGTID), false)); |
---|
| 483 | |
---|
| 484 | std::ostringstream sd; |
---|
[628] | 485 | sd << "seg_mcfg_" << x << "_" << y; |
---|
| 486 | maptabd.add(Segment(sd.str(), MCFG_BASE + offset, MCFG_SIZE, |
---|
| 487 | IntTab(cluster(x,y),MEMC_TGTID), false)); |
---|
[621] | 488 | |
---|
| 489 | std::ostringstream sh; |
---|
| 490 | sh << "seg_memc_" << x << "_" << y; |
---|
| 491 | maptabd.add(Segment(sh.str(), MEMC_BASE + offset, MEMC_SIZE, |
---|
| 492 | IntTab(cluster(x,y),MEMC_TGTID), true)); |
---|
| 493 | } |
---|
| 494 | } |
---|
[628] | 495 | |
---|
| 496 | // segments in cluster(0,0) |
---|
| 497 | maptabd.add(Segment("seg_tty0", MTTY_BASE, MTTY_SIZE, |
---|
| 498 | IntTab(cluster(0,0),MTTY_TGTID), false)); |
---|
| 499 | |
---|
| 500 | maptabd.add(Segment("seg_ioc0", BDEV_BASE, BDEV_SIZE, |
---|
| 501 | IntTab(cluster(0,0),BDEV_TGTID), false)); |
---|
| 502 | |
---|
| 503 | // segments in cluster_io (X_SIZE-1,Y_SIZE) |
---|
| 504 | sc_uint<vci_address_width> offset; |
---|
| 505 | offset = ((sc_uint<vci_address_width>)cluster(X_SIZE-1,Y_SIZE)) << 32; |
---|
| 506 | |
---|
| 507 | maptabd.add(Segment("seg_mtty", MTTY_BASE + offset, MTTY_SIZE, |
---|
| 508 | IntTab(cluster(X_SIZE-1, Y_SIZE),MTTY_TGTID), false)); |
---|
| 509 | |
---|
| 510 | maptabd.add(Segment("seg_fbuf", FBUF_BASE + offset, FBUF_SIZE, |
---|
| 511 | IntTab(cluster(X_SIZE-1, Y_SIZE),FBUF_TGTID), false)); |
---|
| 512 | |
---|
| 513 | maptabd.add(Segment("seg_bdev", BDEV_BASE + offset, BDEV_SIZE, |
---|
| 514 | IntTab(cluster(X_SIZE-1, Y_SIZE),BDEV_TGTID), false)); |
---|
| 515 | |
---|
| 516 | maptabd.add(Segment("seg_mnic", MNIC_BASE + offset, MNIC_SIZE, |
---|
| 517 | IntTab(cluster(X_SIZE-1, Y_SIZE),MNIC_TGTID), false)); |
---|
| 518 | |
---|
| 519 | maptabd.add(Segment("seg_cdma", CDMA_BASE + offset, CDMA_SIZE, |
---|
| 520 | IntTab(cluster(X_SIZE-1, Y_SIZE),CDMA_TGTID), false)); |
---|
| 521 | |
---|
| 522 | maptabd.add(Segment("seg_iopi", IOPI_BASE + offset, IOPI_SIZE, |
---|
| 523 | IntTab(cluster(X_SIZE-1, Y_SIZE),IOPI_TGTID), false)); |
---|
| 524 | |
---|
[621] | 525 | std::cout << maptabd << std::endl; |
---|
| 526 | |
---|
[628] | 527 | ///////////////////////////////////////////////// |
---|
| 528 | // Ram network mapping table |
---|
| 529 | ///////////////////////////////////////////////// |
---|
[621] | 530 | |
---|
[628] | 531 | MappingTable maptabx(vci_address_width, |
---|
| 532 | IntTab(X_WIDTH+Y_WIDTH), |
---|
| 533 | IntTab(X_WIDTH+Y_WIDTH), |
---|
| 534 | 0x00FF000000ULL); |
---|
[621] | 535 | |
---|
[628] | 536 | for (size_t x = 0; x < X_SIZE; x++) |
---|
| 537 | { |
---|
| 538 | for (size_t y = 0; y < Y_SIZE ; y++) |
---|
| 539 | { |
---|
| 540 | sc_uint<vci_address_width> offset; |
---|
| 541 | offset = (sc_uint<vci_address_width>)cluster(x,y) |
---|
| 542 | << (vci_address_width-X_WIDTH-Y_WIDTH); |
---|
[621] | 543 | |
---|
[628] | 544 | std::ostringstream sh; |
---|
| 545 | sh << "x_seg_memc_" << x << "_" << y; |
---|
[621] | 546 | |
---|
[628] | 547 | maptabx.add(Segment(sh.str(), MEMC_BASE + offset, |
---|
[621] | 548 | MEMC_SIZE, IntTab(cluster(x,y)), false)); |
---|
[628] | 549 | } |
---|
| 550 | } |
---|
| 551 | std::cout << maptabx << std::endl; |
---|
[621] | 552 | |
---|
[628] | 553 | //////////////////// |
---|
| 554 | // Signals |
---|
| 555 | /////////////////// |
---|
[621] | 556 | |
---|
[628] | 557 | sc_clock signal_clk("clk"); |
---|
| 558 | sc_signal<bool> signal_resetn("resetn"); |
---|
[621] | 559 | |
---|
[628] | 560 | // IRQs from external peripherals |
---|
| 561 | sc_signal<bool> signal_irq_bdev; |
---|
| 562 | sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS]; |
---|
| 563 | sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS]; |
---|
| 564 | sc_signal<bool> signal_irq_mtty[NB_TTY_CHANNELS]; |
---|
| 565 | sc_signal<bool> signal_irq_cdma[NB_CMA_CHANNELS]; |
---|
| 566 | sc_signal<bool> signal_irq_false; |
---|
| 567 | |
---|
[621] | 568 | // Horizontal inter-clusters DSPIN signals |
---|
[628] | 569 | DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_inc = |
---|
| 570 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", X_SIZE-1, Y_SIZE); |
---|
| 571 | DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_dec = |
---|
| 572 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", X_SIZE-1, Y_SIZE); |
---|
[621] | 573 | |
---|
[628] | 574 | DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_inc = |
---|
| 575 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", X_SIZE-1, Y_SIZE); |
---|
| 576 | DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_dec = |
---|
| 577 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", X_SIZE-1, Y_SIZE); |
---|
| 578 | |
---|
| 579 | DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_inc = |
---|
| 580 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_inc", X_SIZE-1, Y_SIZE); |
---|
| 581 | DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_dec = |
---|
| 582 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_dec", X_SIZE-1, Y_SIZE); |
---|
| 583 | |
---|
| 584 | DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_inc = |
---|
| 585 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_inc", X_SIZE-1, Y_SIZE); |
---|
| 586 | DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_dec = |
---|
| 587 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_dec", X_SIZE-1, Y_SIZE); |
---|
| 588 | |
---|
| 589 | DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_inc = |
---|
| 590 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_inc", X_SIZE-1, Y_SIZE); |
---|
| 591 | DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_dec = |
---|
| 592 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_dec", X_SIZE-1, Y_SIZE); |
---|
| 593 | |
---|
[621] | 594 | // Vertical inter-clusters DSPIN signals |
---|
[628] | 595 | DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_inc = |
---|
| 596 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", X_SIZE, Y_SIZE-1); |
---|
| 597 | DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_dec = |
---|
| 598 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", X_SIZE, Y_SIZE-1); |
---|
[621] | 599 | |
---|
[628] | 600 | DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_inc = |
---|
| 601 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", X_SIZE, Y_SIZE-1); |
---|
| 602 | DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_dec = |
---|
| 603 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", X_SIZE, Y_SIZE-1); |
---|
[621] | 604 | |
---|
[628] | 605 | DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_inc = |
---|
| 606 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_inc", X_SIZE, Y_SIZE-1); |
---|
| 607 | DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_dec = |
---|
| 608 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_dec", X_SIZE, Y_SIZE-1); |
---|
[621] | 609 | |
---|
[628] | 610 | DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_inc = |
---|
| 611 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_inc", X_SIZE, Y_SIZE-1); |
---|
| 612 | DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_dec = |
---|
| 613 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_dec", X_SIZE, Y_SIZE-1); |
---|
| 614 | |
---|
| 615 | DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_inc = |
---|
| 616 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_inc", X_SIZE, Y_SIZE-1); |
---|
| 617 | DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_dec = |
---|
| 618 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_dec", X_SIZE, Y_SIZE-1); |
---|
| 619 | |
---|
| 620 | // Mesh boundaries DSPIN signals (Most of those signals are not used...) |
---|
| 621 | DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_in = |
---|
| 622 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_in" , X_SIZE, Y_SIZE, 4); |
---|
| 623 | DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_out = |
---|
| 624 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_out", X_SIZE, Y_SIZE, 4); |
---|
| 625 | |
---|
| 626 | DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_in = |
---|
| 627 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_in" , X_SIZE, Y_SIZE, 4); |
---|
| 628 | DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_out = |
---|
| 629 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_out", X_SIZE, Y_SIZE, 4); |
---|
| 630 | |
---|
| 631 | DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_in = |
---|
| 632 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_in" , X_SIZE, Y_SIZE, 4); |
---|
| 633 | DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_out = |
---|
| 634 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_out", X_SIZE, Y_SIZE, 4); |
---|
| 635 | |
---|
| 636 | DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_in = |
---|
| 637 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_in" , X_SIZE, Y_SIZE, 4); |
---|
| 638 | DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_out = |
---|
| 639 | alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_out", X_SIZE, Y_SIZE, 4); |
---|
| 640 | |
---|
| 641 | DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_in = |
---|
| 642 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_in" , X_SIZE, Y_SIZE, 4); |
---|
| 643 | DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_out = |
---|
| 644 | alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_out", X_SIZE, Y_SIZE, 4); |
---|
| 645 | |
---|
| 646 | // VCI signals for iobus and peripherals |
---|
| 647 | VciSignals<vci_param_int> signal_vci_ini_bdev("signal_vci_ini_bdev"); |
---|
| 648 | VciSignals<vci_param_int> signal_vci_ini_cdma("signal_vci_ini_cdma"); |
---|
| 649 | VciSignals<vci_param_int> signal_vci_ini_iopi("signal_vci_ini_iopi"); |
---|
| 650 | |
---|
| 651 | VciSignals<vci_param_int>* signal_vci_ini_proc = |
---|
| 652 | alloc_elems<VciSignals<vci_param_int> >("signal_vci_ini_proc", NB_PROCS_MAX ); |
---|
| 653 | |
---|
| 654 | VciSignals<vci_param_int> signal_vci_tgt_memc("signal_vci_tgt_memc"); |
---|
| 655 | VciSignals<vci_param_int> signal_vci_tgt_xicu("signal_vci_tgt_xicu"); |
---|
| 656 | VciSignals<vci_param_int> signal_vci_tgt_bdev("signal_vci_tgt_bdev"); |
---|
| 657 | VciSignals<vci_param_int> signal_vci_tgt_mtty("signal_vci_tgt_mtty"); |
---|
| 658 | VciSignals<vci_param_int> signal_vci_tgt_fbuf("signal_vci_tgt_fbuf"); |
---|
| 659 | VciSignals<vci_param_int> signal_vci_tgt_mnic("signal_vci_tgt_mnic"); |
---|
| 660 | VciSignals<vci_param_int> signal_vci_tgt_cdma("signal_vci_tgt_cdma"); |
---|
| 661 | VciSignals<vci_param_int> signal_vci_tgt_iopi("signal_vci_tgt_iopi"); |
---|
| 662 | |
---|
| 663 | VciSignals<vci_param_int> signal_vci_cmd_to_noc("signal_vci_cmd_to_noc"); |
---|
| 664 | VciSignals<vci_param_int> signal_vci_cmd_from_noc("signal_vci_cmd_from_noc"); |
---|
| 665 | |
---|
[621] | 666 | //////////////////////////// |
---|
| 667 | // Loader |
---|
| 668 | //////////////////////////// |
---|
| 669 | |
---|
| 670 | soclib::common::Loader loader( loader_args ); |
---|
| 671 | |
---|
| 672 | typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss; |
---|
| 673 | proc_iss::set_loader(loader); |
---|
| 674 | |
---|
| 675 | //////////////////////////// |
---|
| 676 | // Clusters construction |
---|
| 677 | //////////////////////////// |
---|
| 678 | |
---|
| 679 | TsarLetiCluster<dspin_cmd_width, |
---|
| 680 | dspin_rsp_width, |
---|
| 681 | vci_param_int, |
---|
| 682 | vci_param_ext>* clusters[X_SIZE][Y_SIZE]; |
---|
| 683 | |
---|
| 684 | #if USE_OPENMP |
---|
| 685 | #pragma omp parallel |
---|
| 686 | { |
---|
| 687 | #pragma omp for |
---|
| 688 | #endif |
---|
| 689 | for (size_t i = 0; i < (X_SIZE * Y_SIZE); i++) |
---|
| 690 | { |
---|
| 691 | size_t x = i / Y_SIZE; |
---|
| 692 | size_t y = i % Y_SIZE; |
---|
| 693 | |
---|
| 694 | #if USE_OPENMP |
---|
| 695 | #pragma omp critical |
---|
| 696 | { |
---|
| 697 | #endif |
---|
| 698 | std::cout << std::endl; |
---|
[628] | 699 | std::cout << "Cluster_" << std::dec << x << "_" << y |
---|
| 700 | << " with cluster_xy = " << std::hex << cluster(x,y) << std::endl; |
---|
[621] | 701 | std::cout << std::endl; |
---|
| 702 | |
---|
| 703 | clusters[x][y] = new TsarLetiCluster<dspin_cmd_width, |
---|
| 704 | dspin_rsp_width, |
---|
| 705 | vci_param_int, |
---|
| 706 | vci_param_ext> |
---|
| 707 | ( |
---|
[628] | 708 | "cluster", |
---|
[621] | 709 | NB_PROCS_MAX, |
---|
| 710 | x, |
---|
| 711 | y, |
---|
| 712 | cluster(x,y), |
---|
| 713 | maptabd, |
---|
| 714 | maptabx, |
---|
| 715 | RESET_ADDRESS, |
---|
| 716 | X_WIDTH, |
---|
| 717 | Y_WIDTH, |
---|
| 718 | vci_srcid_width - X_WIDTH - Y_WIDTH, // l_id width, |
---|
| 719 | MEMC_TGTID, |
---|
| 720 | XICU_TGTID, |
---|
| 721 | MTTY_TGTID, |
---|
| 722 | BDEV_TGTID, |
---|
[628] | 723 | BDEV_IMAGE_NAME, |
---|
[621] | 724 | MEMC_WAYS, |
---|
| 725 | MEMC_SETS, |
---|
| 726 | L1_IWAYS, |
---|
| 727 | L1_ISETS, |
---|
| 728 | L1_DWAYS, |
---|
| 729 | L1_DSETS, |
---|
| 730 | XRAM_LATENCY, |
---|
| 731 | loader, |
---|
| 732 | frozen_cycles, |
---|
| 733 | trace_from, |
---|
| 734 | trace_proc_ok, |
---|
| 735 | trace_proc_id, |
---|
| 736 | trace_memc_ok, |
---|
| 737 | trace_memc_id |
---|
| 738 | ); |
---|
| 739 | |
---|
| 740 | #if USE_OPENMP |
---|
| 741 | } // end critical |
---|
| 742 | #endif |
---|
| 743 | } // end for |
---|
| 744 | #if USE_OPENMP |
---|
| 745 | } |
---|
| 746 | #endif |
---|
| 747 | |
---|
[628] | 748 | ////////////////////////////////////////////////////////////////// |
---|
| 749 | // IO bus and external peripherals in cluster[X_SIZE-1,Y_SIZE] |
---|
| 750 | ////////////////////////////////////////////////////////////////// |
---|
[621] | 751 | |
---|
[628] | 752 | size_t cluster_io = cluster(X_SIZE-1, Y_SIZE); |
---|
[621] | 753 | |
---|
[628] | 754 | //////////// vci_local_crossbar |
---|
| 755 | VciLocalCrossbar<vci_param_int>* |
---|
| 756 | iobus = new VciLocalCrossbar<vci_param_int>( |
---|
| 757 | "iobus", |
---|
| 758 | maptabd, // mapping table |
---|
| 759 | cluster_io, // cluster_xy |
---|
| 760 | NB_PROCS_MAX + 3, // number of local initiators |
---|
| 761 | 8, // number of local targets |
---|
| 762 | BDEV_TGTID ); // default target index |
---|
[621] | 763 | |
---|
[628] | 764 | //////////// vci_framebuffer |
---|
| 765 | VciFrameBuffer<vci_param_int>* |
---|
| 766 | fbuf = new VciFrameBuffer<vci_param_int>( |
---|
| 767 | "fbuf", |
---|
| 768 | IntTab(cluster_io, FBUF_TGTID), |
---|
| 769 | maptabd, |
---|
| 770 | FBUF_X_SIZE, FBUF_Y_SIZE ); |
---|
[621] | 771 | |
---|
[628] | 772 | //////////// vci_block_device |
---|
| 773 | VciBlockDeviceTsar<vci_param_int>* |
---|
| 774 | bdev = new VciBlockDeviceTsar<vci_param_int>( |
---|
| 775 | "bdev", |
---|
| 776 | maptabd, |
---|
| 777 | IntTab(cluster_io, BDEV_SRCID), |
---|
| 778 | IntTab(cluster_io, BDEV_TGTID), |
---|
| 779 | BDEV_IMAGE_NAME, |
---|
| 780 | 512, // block size |
---|
| 781 | 64 ); // burst size |
---|
| 782 | |
---|
| 783 | //////////// vci_multi_nic |
---|
| 784 | VciMultiNic<vci_param_int>* |
---|
| 785 | mnic = new VciMultiNic<vci_param_int>( |
---|
| 786 | "mnic", |
---|
| 787 | IntTab(cluster_io, MNIC_TGTID), |
---|
| 788 | maptabd, |
---|
| 789 | NB_NIC_CHANNELS, |
---|
| 790 | NIC_MAC4, |
---|
| 791 | NIC_MAC2, |
---|
| 792 | NIC_RX_NAME, |
---|
| 793 | NIC_TX_NAME ); |
---|
| 794 | |
---|
| 795 | ///////////// vci_chbuf_dma |
---|
| 796 | VciChbufDma<vci_param_int>* |
---|
| 797 | cdma = new VciChbufDma<vci_param_int>( |
---|
| 798 | "cdma", |
---|
| 799 | maptabd, |
---|
| 800 | IntTab(cluster_io, CDMA_SRCID), |
---|
| 801 | IntTab(cluster_io, CDMA_TGTID), |
---|
| 802 | 64, // burst size |
---|
| 803 | NB_CMA_CHANNELS ); |
---|
| 804 | |
---|
| 805 | ////////////// vci_multi_tty |
---|
| 806 | std::vector<std::string> vect_names; |
---|
| 807 | for (size_t id = 0; id < NB_TTY_CHANNELS; id++) |
---|
| 808 | { |
---|
| 809 | std::ostringstream term_name; |
---|
| 810 | term_name << "ext_" << id; |
---|
| 811 | vect_names.push_back(term_name.str().c_str()); |
---|
| 812 | } |
---|
| 813 | |
---|
| 814 | VciMultiTty<vci_param_int>* |
---|
| 815 | mtty = new VciMultiTty<vci_param_int>( |
---|
| 816 | "mtty", |
---|
| 817 | IntTab(cluster_io, MTTY_TGTID), |
---|
| 818 | maptabd, |
---|
| 819 | vect_names ); |
---|
| 820 | |
---|
| 821 | ///////////// vci_iopic |
---|
| 822 | VciIopic<vci_param_int>* |
---|
| 823 | iopic = new VciIopic<vci_param_int>( |
---|
| 824 | "iopic", |
---|
| 825 | maptabd, |
---|
| 826 | IntTab(cluster_io, IOPI_SRCID), |
---|
| 827 | IntTab(cluster_io, IOPI_TGTID), |
---|
| 828 | 16 ); |
---|
| 829 | |
---|
| 830 | ////////////// vci_dspin wrappers |
---|
| 831 | VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>* |
---|
| 832 | wt_iobus = new VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>( |
---|
| 833 | "wt_bdev", |
---|
| 834 | vci_srcid_width ); |
---|
| 835 | |
---|
| 836 | VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>* |
---|
| 837 | wi_iobus = new VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>( |
---|
| 838 | "wi_bdev", |
---|
| 839 | vci_srcid_width ); |
---|
| 840 | |
---|
| 841 | /////////////////////////////////////////////////////////////// |
---|
| 842 | // Net-list |
---|
| 843 | /////////////////////////////////////////////////////////////// |
---|
| 844 | |
---|
| 845 | // iobus |
---|
| 846 | iobus->p_clk (signal_clk); |
---|
| 847 | iobus->p_resetn (signal_resetn); |
---|
| 848 | |
---|
| 849 | iobus->p_target_to_up (signal_vci_cmd_from_noc); |
---|
| 850 | iobus->p_initiator_to_up (signal_vci_cmd_to_noc); |
---|
| 851 | |
---|
| 852 | iobus->p_to_target[MEMC_TGTID] (signal_vci_tgt_memc); |
---|
| 853 | iobus->p_to_target[XICU_TGTID] (signal_vci_tgt_xicu); |
---|
| 854 | iobus->p_to_target[MTTY_TGTID] (signal_vci_tgt_mtty); |
---|
| 855 | iobus->p_to_target[FBUF_TGTID] (signal_vci_tgt_fbuf); |
---|
| 856 | iobus->p_to_target[MNIC_TGTID] (signal_vci_tgt_mnic); |
---|
| 857 | iobus->p_to_target[BDEV_TGTID] (signal_vci_tgt_bdev); |
---|
| 858 | iobus->p_to_target[CDMA_TGTID] (signal_vci_tgt_cdma); |
---|
| 859 | iobus->p_to_target[IOPI_TGTID] (signal_vci_tgt_iopi); |
---|
| 860 | |
---|
| 861 | for( size_t p=0 ; p<NB_PROCS_MAX ; p++ ) |
---|
| 862 | { |
---|
| 863 | iobus->p_to_initiator[p] (signal_vci_ini_proc[p]); |
---|
| 864 | } |
---|
| 865 | iobus->p_to_initiator[BDEV_SRCID] (signal_vci_ini_bdev); |
---|
| 866 | iobus->p_to_initiator[CDMA_SRCID] (signal_vci_ini_cdma); |
---|
| 867 | iobus->p_to_initiator[IOPI_SRCID] (signal_vci_ini_iopi); |
---|
| 868 | |
---|
| 869 | std::cout << " - IOBUS connected" << std::endl; |
---|
| 870 | |
---|
| 871 | // block_device |
---|
| 872 | bdev->p_clk (signal_clk); |
---|
| 873 | bdev->p_resetn (signal_resetn); |
---|
| 874 | bdev->p_vci_target (signal_vci_tgt_bdev); |
---|
| 875 | bdev->p_vci_initiator (signal_vci_ini_bdev); |
---|
| 876 | bdev->p_irq (signal_irq_bdev); |
---|
| 877 | |
---|
| 878 | std::cout << " - BDEV connected" << std::endl; |
---|
| 879 | |
---|
| 880 | // frame_buffer |
---|
| 881 | fbuf->p_clk (signal_clk); |
---|
| 882 | fbuf->p_resetn (signal_resetn); |
---|
| 883 | fbuf->p_vci (signal_vci_tgt_fbuf); |
---|
| 884 | |
---|
| 885 | std::cout << " - FBUF connected" << std::endl; |
---|
| 886 | |
---|
| 887 | // multi_nic |
---|
| 888 | mnic->p_clk (signal_clk); |
---|
| 889 | mnic->p_resetn (signal_resetn); |
---|
| 890 | mnic->p_vci (signal_vci_tgt_mnic); |
---|
| 891 | for ( size_t i=0 ; i<NB_NIC_CHANNELS ; i++ ) |
---|
| 892 | { |
---|
| 893 | mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]); |
---|
| 894 | mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]); |
---|
| 895 | } |
---|
| 896 | |
---|
| 897 | std::cout << " - MNIC connected" << std::endl; |
---|
| 898 | |
---|
| 899 | // chbuf_dma |
---|
| 900 | cdma->p_clk (signal_clk); |
---|
| 901 | cdma->p_resetn (signal_resetn); |
---|
| 902 | cdma->p_vci_target (signal_vci_tgt_cdma); |
---|
| 903 | cdma->p_vci_initiator (signal_vci_ini_cdma); |
---|
| 904 | for ( size_t i=0 ; i<NB_CMA_CHANNELS ; i++) |
---|
| 905 | { |
---|
| 906 | cdma->p_irq[i] (signal_irq_cdma[i]); |
---|
| 907 | } |
---|
| 908 | |
---|
| 909 | std::cout << " - CDMA connected" << std::endl; |
---|
| 910 | |
---|
| 911 | // multi_tty |
---|
| 912 | mtty->p_clk (signal_clk); |
---|
| 913 | mtty->p_resetn (signal_resetn); |
---|
| 914 | mtty->p_vci (signal_vci_tgt_mtty); |
---|
| 915 | for ( size_t i=0 ; i<NB_TTY_CHANNELS ; i++ ) |
---|
| 916 | { |
---|
| 917 | mtty->p_irq[i] (signal_irq_mtty[i]); |
---|
| 918 | } |
---|
| 919 | |
---|
| 920 | std::cout << " - MTTY connected" << std::endl; |
---|
| 921 | |
---|
| 922 | // iopic |
---|
| 923 | iopic->p_clk (signal_clk); |
---|
| 924 | iopic->p_resetn (signal_resetn); |
---|
| 925 | iopic->p_vci_target (signal_vci_tgt_iopi); |
---|
| 926 | iopic->p_vci_initiator (signal_vci_ini_iopi); |
---|
| 927 | for ( size_t i=0 ; i<16 ; i++) |
---|
| 928 | { |
---|
| 929 | if (i < NB_NIC_CHANNELS) iopic->p_hwi[i] (signal_irq_mnic_rx[i]); |
---|
| 930 | else if(i < 2 ) iopic->p_hwi[i] (signal_irq_false); |
---|
| 931 | else if(i < 2+NB_NIC_CHANNELS) iopic->p_hwi[i] (signal_irq_mnic_tx[i-2]); |
---|
| 932 | else if(i < 4 ) iopic->p_hwi[i] (signal_irq_false); |
---|
| 933 | else if(i < 4+NB_CMA_CHANNELS) iopic->p_hwi[i] (signal_irq_cdma[i-4]); |
---|
| 934 | else if(i < 9) iopic->p_hwi[i] (signal_irq_false); |
---|
| 935 | else if(i == 9) iopic->p_hwi[i] (signal_irq_bdev); |
---|
| 936 | else if(i < 12) iopic->p_hwi[i] (signal_irq_false); |
---|
| 937 | else if(i < 12+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_mtty[i-12]); |
---|
| 938 | else iopic->p_hwi[i] (signal_irq_false); |
---|
| 939 | } |
---|
| 940 | |
---|
| 941 | // vci/dspin wrappers |
---|
| 942 | wi_iobus->p_clk (signal_clk); |
---|
| 943 | wi_iobus->p_resetn (signal_resetn); |
---|
| 944 | wi_iobus->p_vci (signal_vci_cmd_to_noc); |
---|
| 945 | wi_iobus->p_dspin_cmd (signal_dspin_bound_cmd_in[X_SIZE-1][Y_SIZE-1][NORTH]); |
---|
| 946 | wi_iobus->p_dspin_rsp (signal_dspin_bound_rsp_out[X_SIZE-1][Y_SIZE-1][NORTH]); |
---|
| 947 | |
---|
| 948 | // vci/dspin wrappers |
---|
| 949 | wt_iobus->p_clk (signal_clk); |
---|
| 950 | wt_iobus->p_resetn (signal_resetn); |
---|
| 951 | wt_iobus->p_vci (signal_vci_cmd_from_noc); |
---|
| 952 | wt_iobus->p_dspin_cmd (signal_dspin_bound_cmd_out[X_SIZE-1][Y_SIZE-1][NORTH]); |
---|
| 953 | wt_iobus->p_dspin_rsp (signal_dspin_bound_rsp_in[X_SIZE-1][Y_SIZE-1][NORTH]); |
---|
| 954 | |
---|
| 955 | // Clock & RESET for clusters |
---|
| 956 | for (size_t x = 0; x < (X_SIZE); x++) |
---|
| 957 | { |
---|
| 958 | for (size_t y = 0; y < Y_SIZE; y++) |
---|
| 959 | { |
---|
| 960 | clusters[x][y]->p_clk (signal_clk); |
---|
| 961 | clusters[x][y]->p_resetn (signal_resetn); |
---|
| 962 | } |
---|
| 963 | } |
---|
| 964 | |
---|
| 965 | // Inter Clusters horizontal connections |
---|
| 966 | if (X_SIZE > 1) |
---|
| 967 | { |
---|
| 968 | for (size_t x = 0; x < (X_SIZE-1); x++) |
---|
| 969 | { |
---|
| 970 | for (size_t y = 0; y < Y_SIZE; y++) |
---|
| 971 | { |
---|
| 972 | clusters[x][y]->p_cmd_out[EAST] (signal_dspin_h_cmd_inc[x][y]); |
---|
| 973 | clusters[x+1][y]->p_cmd_in[WEST] (signal_dspin_h_cmd_inc[x][y]); |
---|
| 974 | clusters[x][y]->p_cmd_in[EAST] (signal_dspin_h_cmd_dec[x][y]); |
---|
| 975 | clusters[x+1][y]->p_cmd_out[WEST] (signal_dspin_h_cmd_dec[x][y]); |
---|
| 976 | |
---|
| 977 | clusters[x][y]->p_rsp_out[EAST] (signal_dspin_h_rsp_inc[x][y]); |
---|
| 978 | clusters[x+1][y]->p_rsp_in[WEST] (signal_dspin_h_rsp_inc[x][y]); |
---|
| 979 | clusters[x][y]->p_rsp_in[EAST] (signal_dspin_h_rsp_dec[x][y]); |
---|
| 980 | clusters[x+1][y]->p_rsp_out[WEST] (signal_dspin_h_rsp_dec[x][y]); |
---|
| 981 | |
---|
| 982 | clusters[x][y]->p_m2p_out[EAST] (signal_dspin_h_m2p_inc[x][y]); |
---|
| 983 | clusters[x+1][y]->p_m2p_in[WEST] (signal_dspin_h_m2p_inc[x][y]); |
---|
| 984 | clusters[x][y]->p_m2p_in[EAST] (signal_dspin_h_m2p_dec[x][y]); |
---|
| 985 | clusters[x+1][y]->p_m2p_out[WEST] (signal_dspin_h_m2p_dec[x][y]); |
---|
| 986 | |
---|
| 987 | clusters[x][y]->p_p2m_out[EAST] (signal_dspin_h_p2m_inc[x][y]); |
---|
| 988 | clusters[x+1][y]->p_p2m_in[WEST] (signal_dspin_h_p2m_inc[x][y]); |
---|
| 989 | clusters[x][y]->p_p2m_in[EAST] (signal_dspin_h_p2m_dec[x][y]); |
---|
| 990 | clusters[x+1][y]->p_p2m_out[WEST] (signal_dspin_h_p2m_dec[x][y]); |
---|
| 991 | |
---|
| 992 | clusters[x][y]->p_cla_out[EAST] (signal_dspin_h_cla_inc[x][y]); |
---|
| 993 | clusters[x+1][y]->p_cla_in[WEST] (signal_dspin_h_cla_inc[x][y]); |
---|
| 994 | clusters[x][y]->p_cla_in[EAST] (signal_dspin_h_cla_dec[x][y]); |
---|
| 995 | clusters[x+1][y]->p_cla_out[WEST] (signal_dspin_h_cla_dec[x][y]); |
---|
[621] | 996 | } |
---|
[628] | 997 | } |
---|
| 998 | } |
---|
| 999 | std::cout << std::endl << "Horizontal connections done" << std::endl; |
---|
[621] | 1000 | |
---|
[628] | 1001 | // Inter Clusters vertical connections |
---|
| 1002 | if (Y_SIZE > 1) |
---|
| 1003 | { |
---|
| 1004 | for (size_t y = 0; y < (Y_SIZE-1); y++) |
---|
| 1005 | { |
---|
| 1006 | for (size_t x = 0; x < X_SIZE; x++) |
---|
| 1007 | { |
---|
| 1008 | clusters[x][y]->p_cmd_out[NORTH] (signal_dspin_v_cmd_inc[x][y]); |
---|
| 1009 | clusters[x][y+1]->p_cmd_in[SOUTH] (signal_dspin_v_cmd_inc[x][y]); |
---|
| 1010 | clusters[x][y]->p_cmd_in[NORTH] (signal_dspin_v_cmd_dec[x][y]); |
---|
| 1011 | clusters[x][y+1]->p_cmd_out[SOUTH] (signal_dspin_v_cmd_dec[x][y]); |
---|
| 1012 | |
---|
| 1013 | clusters[x][y]->p_rsp_out[NORTH] (signal_dspin_v_rsp_inc[x][y]); |
---|
| 1014 | clusters[x][y+1]->p_rsp_in[SOUTH] (signal_dspin_v_rsp_inc[x][y]); |
---|
| 1015 | clusters[x][y]->p_rsp_in[NORTH] (signal_dspin_v_rsp_dec[x][y]); |
---|
| 1016 | clusters[x][y+1]->p_rsp_out[SOUTH] (signal_dspin_v_rsp_dec[x][y]); |
---|
| 1017 | |
---|
| 1018 | clusters[x][y]->p_m2p_out[NORTH] (signal_dspin_v_m2p_inc[x][y]); |
---|
| 1019 | clusters[x][y+1]->p_m2p_in[SOUTH] (signal_dspin_v_m2p_inc[x][y]); |
---|
| 1020 | clusters[x][y]->p_m2p_in[NORTH] (signal_dspin_v_m2p_dec[x][y]); |
---|
| 1021 | clusters[x][y+1]->p_m2p_out[SOUTH] (signal_dspin_v_m2p_dec[x][y]); |
---|
| 1022 | |
---|
| 1023 | clusters[x][y]->p_p2m_out[NORTH] (signal_dspin_v_p2m_inc[x][y]); |
---|
| 1024 | clusters[x][y+1]->p_p2m_in[SOUTH] (signal_dspin_v_p2m_inc[x][y]); |
---|
| 1025 | clusters[x][y]->p_p2m_in[NORTH] (signal_dspin_v_p2m_dec[x][y]); |
---|
| 1026 | clusters[x][y+1]->p_p2m_out[SOUTH] (signal_dspin_v_p2m_dec[x][y]); |
---|
| 1027 | |
---|
| 1028 | clusters[x][y]->p_cla_out[NORTH] (signal_dspin_v_cla_inc[x][y]); |
---|
| 1029 | clusters[x][y+1]->p_cla_in[SOUTH] (signal_dspin_v_cla_inc[x][y]); |
---|
| 1030 | clusters[x][y]->p_cla_in[NORTH] (signal_dspin_v_cla_dec[x][y]); |
---|
| 1031 | clusters[x][y+1]->p_cla_out[SOUTH] (signal_dspin_v_cla_dec[x][y]); |
---|
[621] | 1032 | } |
---|
[628] | 1033 | } |
---|
| 1034 | } |
---|
| 1035 | std::cout << std::endl << "Vertical connections done" << std::endl; |
---|
[621] | 1036 | |
---|
[628] | 1037 | // East & West boundary cluster connections |
---|
| 1038 | for (size_t y = 0; y < Y_SIZE; y++) |
---|
| 1039 | { |
---|
| 1040 | clusters[0][y]->p_cmd_in[WEST] (signal_dspin_bound_cmd_in[0][y][WEST]); |
---|
| 1041 | clusters[0][y]->p_cmd_out[WEST] (signal_dspin_bound_cmd_out[0][y][WEST]); |
---|
| 1042 | clusters[X_SIZE-1][y]->p_cmd_in[EAST] (signal_dspin_bound_cmd_in[X_SIZE-1][y][EAST]); |
---|
| 1043 | clusters[X_SIZE-1][y]->p_cmd_out[EAST] (signal_dspin_bound_cmd_out[X_SIZE-1][y][EAST]); |
---|
[621] | 1044 | |
---|
[628] | 1045 | clusters[0][y]->p_rsp_in[WEST] (signal_dspin_bound_rsp_in[0][y][WEST]); |
---|
| 1046 | clusters[0][y]->p_rsp_out[WEST] (signal_dspin_bound_rsp_out[0][y][WEST]); |
---|
| 1047 | clusters[X_SIZE-1][y]->p_rsp_in[EAST] (signal_dspin_bound_rsp_in[X_SIZE-1][y][EAST]); |
---|
| 1048 | clusters[X_SIZE-1][y]->p_rsp_out[EAST] (signal_dspin_bound_rsp_out[X_SIZE-1][y][EAST]); |
---|
[621] | 1049 | |
---|
[628] | 1050 | clusters[0][y]->p_m2p_in[WEST] (signal_dspin_bound_m2p_in[0][y][WEST]); |
---|
| 1051 | clusters[0][y]->p_m2p_out[WEST] (signal_dspin_bound_m2p_out[0][y][WEST]); |
---|
| 1052 | clusters[X_SIZE-1][y]->p_m2p_in[EAST] (signal_dspin_bound_m2p_in[X_SIZE-1][y][EAST]); |
---|
| 1053 | clusters[X_SIZE-1][y]->p_m2p_out[EAST] (signal_dspin_bound_m2p_out[X_SIZE-1][y][EAST]); |
---|
[621] | 1054 | |
---|
[628] | 1055 | clusters[0][y]->p_p2m_in[WEST] (signal_dspin_bound_p2m_in[0][y][WEST]); |
---|
| 1056 | clusters[0][y]->p_p2m_out[WEST] (signal_dspin_bound_p2m_out[0][y][WEST]); |
---|
| 1057 | clusters[X_SIZE-1][y]->p_p2m_in[EAST] (signal_dspin_bound_p2m_in[X_SIZE-1][y][EAST]); |
---|
| 1058 | clusters[X_SIZE-1][y]->p_p2m_out[EAST] (signal_dspin_bound_p2m_out[X_SIZE-1][y][EAST]); |
---|
[621] | 1059 | |
---|
[628] | 1060 | clusters[0][y]->p_cla_in[WEST] (signal_dspin_bound_cla_in[0][y][WEST]); |
---|
| 1061 | clusters[0][y]->p_cla_out[WEST] (signal_dspin_bound_cla_out[0][y][WEST]); |
---|
| 1062 | clusters[X_SIZE-1][y]->p_cla_in[EAST] (signal_dspin_bound_cla_in[X_SIZE-1][y][EAST]); |
---|
| 1063 | clusters[X_SIZE-1][y]->p_cla_out[EAST] (signal_dspin_bound_cla_out[X_SIZE-1][y][EAST]); |
---|
| 1064 | } |
---|
[621] | 1065 | |
---|
[628] | 1066 | // North & South boundary clusters connections |
---|
| 1067 | for (size_t x = 0; x < X_SIZE; x++) |
---|
| 1068 | { |
---|
| 1069 | clusters[x][0]->p_cmd_in[SOUTH] (signal_dspin_bound_cmd_in[x][0][SOUTH]); |
---|
| 1070 | clusters[x][0]->p_cmd_out[SOUTH] (signal_dspin_bound_cmd_out[x][0][SOUTH]); |
---|
| 1071 | clusters[x][Y_SIZE-1]->p_cmd_in[NORTH] (signal_dspin_bound_cmd_in[x][Y_SIZE-1][NORTH]); |
---|
| 1072 | clusters[x][Y_SIZE-1]->p_cmd_out[NORTH] (signal_dspin_bound_cmd_out[x][Y_SIZE-1][NORTH]); |
---|
[621] | 1073 | |
---|
[628] | 1074 | clusters[x][0]->p_rsp_in[SOUTH] (signal_dspin_bound_rsp_in[x][0][SOUTH]); |
---|
| 1075 | clusters[x][0]->p_rsp_out[SOUTH] (signal_dspin_bound_rsp_out[x][0][SOUTH]); |
---|
| 1076 | clusters[x][Y_SIZE-1]->p_rsp_in[NORTH] (signal_dspin_bound_rsp_in[x][Y_SIZE-1][NORTH]); |
---|
| 1077 | clusters[x][Y_SIZE-1]->p_rsp_out[NORTH] (signal_dspin_bound_rsp_out[x][Y_SIZE-1][NORTH]); |
---|
[621] | 1078 | |
---|
[628] | 1079 | clusters[x][0]->p_m2p_in[SOUTH] (signal_dspin_bound_m2p_in[x][0][SOUTH]); |
---|
| 1080 | clusters[x][0]->p_m2p_out[SOUTH] (signal_dspin_bound_m2p_out[x][0][SOUTH]); |
---|
| 1081 | clusters[x][Y_SIZE-1]->p_m2p_in[NORTH] (signal_dspin_bound_m2p_in[x][Y_SIZE-1][NORTH]); |
---|
| 1082 | clusters[x][Y_SIZE-1]->p_m2p_out[NORTH] (signal_dspin_bound_m2p_out[x][Y_SIZE-1][NORTH]); |
---|
[621] | 1083 | |
---|
[628] | 1084 | clusters[x][0]->p_p2m_in[SOUTH] (signal_dspin_bound_p2m_in[x][0][SOUTH]); |
---|
| 1085 | clusters[x][0]->p_p2m_out[SOUTH] (signal_dspin_bound_p2m_out[x][0][SOUTH]); |
---|
| 1086 | clusters[x][Y_SIZE-1]->p_p2m_in[NORTH] (signal_dspin_bound_p2m_in[x][Y_SIZE-1][NORTH]); |
---|
| 1087 | clusters[x][Y_SIZE-1]->p_p2m_out[NORTH] (signal_dspin_bound_p2m_out[x][Y_SIZE-1][NORTH]); |
---|
| 1088 | |
---|
| 1089 | clusters[x][0]->p_cla_in[SOUTH] (signal_dspin_bound_cla_in[x][0][SOUTH]); |
---|
| 1090 | clusters[x][0]->p_cla_out[SOUTH] (signal_dspin_bound_cla_out[x][0][SOUTH]); |
---|
| 1091 | clusters[x][Y_SIZE-1]->p_cla_in[NORTH] (signal_dspin_bound_cla_in[x][Y_SIZE-1][NORTH]); |
---|
| 1092 | clusters[x][Y_SIZE-1]->p_cla_out[NORTH] (signal_dspin_bound_cla_out[x][Y_SIZE-1][NORTH]); |
---|
| 1093 | } |
---|
| 1094 | |
---|
| 1095 | std::cout << std::endl << "North, South, West, East connections done" << std::endl; |
---|
| 1096 | std::cout << std::endl; |
---|
| 1097 | |
---|
| 1098 | //////////////////////////////////////////////////////// |
---|
| 1099 | // Simulation |
---|
| 1100 | /////////////////////////////////////////////////////// |
---|
| 1101 | |
---|
| 1102 | sc_start(sc_core::sc_time(0, SC_NS)); |
---|
| 1103 | signal_resetn = false; |
---|
| 1104 | signal_irq_false = false; |
---|
| 1105 | |
---|
| 1106 | // set network boundaries signals default values |
---|
| 1107 | // for all boundary clusters but the IO cluster |
---|
| 1108 | for (size_t x = 0; x < X_SIZE ; x++) |
---|
| 1109 | { |
---|
| 1110 | for (size_t y = 0; y < Y_SIZE ; y++) |
---|
| 1111 | { |
---|
| 1112 | for (size_t face = 0; face < 4; face++) |
---|
| 1113 | { |
---|
| 1114 | if ( (x != X_SIZE-1) or (y != Y_SIZE-1) or (face != NORTH) ) |
---|
| 1115 | { |
---|
| 1116 | signal_dspin_bound_cmd_in [x][y][face].write = false; |
---|
| 1117 | signal_dspin_bound_cmd_in [x][y][face].read = true; |
---|
| 1118 | signal_dspin_bound_cmd_out[x][y][face].write = false; |
---|
| 1119 | signal_dspin_bound_cmd_out[x][y][face].read = true; |
---|
| 1120 | |
---|
| 1121 | signal_dspin_bound_rsp_in [x][y][face].write = false; |
---|
| 1122 | signal_dspin_bound_rsp_in [x][y][face].read = true; |
---|
| 1123 | signal_dspin_bound_rsp_out[x][y][face].write = false; |
---|
| 1124 | signal_dspin_bound_rsp_out[x][y][face].read = true; |
---|
| 1125 | } |
---|
| 1126 | |
---|
| 1127 | signal_dspin_bound_m2p_in [x][y][face].write = false; |
---|
| 1128 | signal_dspin_bound_m2p_in [x][y][face].read = true; |
---|
| 1129 | signal_dspin_bound_m2p_out[x][y][face].write = false; |
---|
| 1130 | signal_dspin_bound_m2p_out[x][y][face].read = true; |
---|
| 1131 | |
---|
| 1132 | signal_dspin_bound_p2m_in [x][y][face].write = false; |
---|
| 1133 | signal_dspin_bound_p2m_in [x][y][face].read = true; |
---|
| 1134 | signal_dspin_bound_p2m_out[x][y][face].write = false; |
---|
| 1135 | signal_dspin_bound_p2m_out[x][y][face].read = true; |
---|
| 1136 | |
---|
| 1137 | signal_dspin_bound_cla_in [x][y][face].write = false; |
---|
| 1138 | signal_dspin_bound_cla_in [x][y][face].read = true; |
---|
| 1139 | signal_dspin_bound_cla_out[x][y][face].write = false; |
---|
| 1140 | signal_dspin_bound_cla_out[x][y][face].read = true; |
---|
[621] | 1141 | } |
---|
[628] | 1142 | } |
---|
| 1143 | } |
---|
[621] | 1144 | |
---|
[628] | 1145 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
| 1146 | signal_resetn = true; |
---|
[621] | 1147 | |
---|
[628] | 1148 | if (gettimeofday(&t1, NULL) != 0) |
---|
| 1149 | { |
---|
| 1150 | perror("gettimeofday"); |
---|
| 1151 | return EXIT_FAILURE; |
---|
| 1152 | } |
---|
[621] | 1153 | |
---|
| 1154 | for (uint64_t n = 1; n < ncycles && !stop_called; n++) |
---|
| 1155 | { |
---|
| 1156 | // Monitor a specific address for L1 & L2 caches |
---|
[628] | 1157 | // clusters[0][0]->proc[0]->cache_monitor(0x0000010000ULL); |
---|
| 1158 | // clusters[0][0]->memc->cache_monitor(0x0000030000ULL); |
---|
[621] | 1159 | |
---|
| 1160 | if( (n % 5000000) == 0) |
---|
| 1161 | { |
---|
| 1162 | |
---|
| 1163 | if (gettimeofday(&t2, NULL) != 0) |
---|
| 1164 | { |
---|
| 1165 | perror("gettimeofday"); |
---|
| 1166 | return EXIT_FAILURE; |
---|
| 1167 | } |
---|
| 1168 | |
---|
| 1169 | ms1 = (uint64_t) t1.tv_sec * 1000ULL + (uint64_t) t1.tv_usec / 1000; |
---|
| 1170 | ms2 = (uint64_t) t2.tv_sec * 1000ULL + (uint64_t) t2.tv_usec / 1000; |
---|
| 1171 | std::cerr << "platform clock frequency " |
---|
| 1172 | << (double) 5000000 / (double) (ms2 - ms1) << "Khz" << std::endl; |
---|
| 1173 | |
---|
| 1174 | if (gettimeofday(&t1, NULL) != 0) |
---|
| 1175 | { |
---|
| 1176 | perror("gettimeofday"); |
---|
| 1177 | return EXIT_FAILURE; |
---|
| 1178 | } |
---|
| 1179 | } |
---|
| 1180 | |
---|
| 1181 | if ( trace_ok and (n > trace_from) ) |
---|
| 1182 | { |
---|
| 1183 | std::cout << "****************** cycle " << std::dec << n ; |
---|
| 1184 | std::cout << " ************************************************" << std::endl; |
---|
| 1185 | |
---|
| 1186 | // trace proc[trace_proc_id] |
---|
| 1187 | size_t l = trace_proc_id % NB_PROCS_MAX ; |
---|
| 1188 | size_t x = (trace_proc_id / NB_PROCS_MAX) >> Y_WIDTH ; |
---|
| 1189 | size_t y = (trace_proc_id / NB_PROCS_MAX) & ((1<<Y_WIDTH) - 1); |
---|
| 1190 | |
---|
| 1191 | std::ostringstream proc_signame; |
---|
| 1192 | proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; |
---|
[628] | 1193 | std::ostringstream xicu_signame; |
---|
| 1194 | xicu_signame << "[SIG]XICU_" << x << "_" << y ; |
---|
[621] | 1195 | |
---|
[628] | 1196 | clusters[x][y]->proc[l]->print_trace(0x1); |
---|
[621] | 1197 | clusters[x][y]->signal_vci_ini_proc[l].print_trace(proc_signame.str()); |
---|
| 1198 | |
---|
[628] | 1199 | clusters[x][y]->xicu->print_trace(0); |
---|
| 1200 | clusters[x][y]->signal_vci_tgt_xicu.print_trace(xicu_signame.str()); |
---|
| 1201 | |
---|
| 1202 | if ( clusters[x][y]->signal_proc_irq[0].read() ) |
---|
| 1203 | std::cout << " IRQ_PROC active in cluster " << cluster(x,y) << std::endl; |
---|
| 1204 | |
---|
| 1205 | if ( signal_irq_bdev.read() ) |
---|
| 1206 | std::cout << " IRQ_BDEV in cluster_io active" << std::endl; |
---|
| 1207 | |
---|
| 1208 | // trace memc[trace_memc_id] and xram[trace_memc_id] |
---|
[621] | 1209 | x = trace_memc_id >> Y_WIDTH; |
---|
| 1210 | y = trace_memc_id & ((1<<Y_WIDTH) - 1); |
---|
| 1211 | |
---|
| 1212 | std::ostringstream smemc; |
---|
| 1213 | smemc << "[SIG]MEMC_" << x << "_" << y; |
---|
| 1214 | std::ostringstream sxram; |
---|
| 1215 | sxram << "[SIG]XRAM_" << x << "_" << y; |
---|
| 1216 | |
---|
| 1217 | clusters[x][y]->memc->print_trace(); |
---|
| 1218 | clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str()); |
---|
| 1219 | clusters[x][y]->signal_vci_xram.print_trace(sxram.str()); |
---|
| 1220 | |
---|
[628] | 1221 | // trace coherence signals |
---|
| 1222 | // clusters[0][0]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_0_0]"); |
---|
| 1223 | // clusters[0][1]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_0_1]"); |
---|
| 1224 | // clusters[1][0]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_1_0]"); |
---|
| 1225 | // clusters[1][1]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_1_1]"); |
---|
| 1226 | |
---|
| 1227 | // clusters[0][0]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_0_0]"); |
---|
| 1228 | // clusters[0][1]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_0_1]"); |
---|
| 1229 | // clusters[1][0]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_1_0]"); |
---|
| 1230 | // clusters[1][1]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_1_1]"); |
---|
| 1231 | |
---|
| 1232 | // trace xbar(s) m2p |
---|
| 1233 | // clusters[0][0]->xbar_m2p->print_trace(); |
---|
| 1234 | // clusters[1][0]->xbar_m2p->print_trace(); |
---|
| 1235 | // clusters[0][1]->xbar_m2p->print_trace(); |
---|
| 1236 | // clusters[1][1]->xbar_m2p->print_trace(); |
---|
[621] | 1237 | |
---|
[628] | 1238 | // trace router(s) m2p |
---|
| 1239 | // clusters[0][0]->router_m2p->print_trace(); |
---|
| 1240 | // clusters[1][0]->router_m2p->print_trace(); |
---|
| 1241 | // clusters[0][1]->router_m2p->print_trace(); |
---|
| 1242 | // clusters[1][1]->router_m2p->print_trace(); |
---|
| 1243 | |
---|
[621] | 1244 | // trace external peripherals |
---|
[628] | 1245 | bdev->print_trace(); |
---|
| 1246 | signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT"); |
---|
| 1247 | signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI"); |
---|
[621] | 1248 | |
---|
[628] | 1249 | iopic->print_trace(); |
---|
| 1250 | signal_vci_tgt_iopi.print_trace("[SIG]IOPI_TGT"); |
---|
| 1251 | signal_vci_ini_iopi.print_trace("[SIG]IOPI_INI"); |
---|
[621] | 1252 | |
---|
[628] | 1253 | clusters[0][0]->mtty->print_trace(); |
---|
| 1254 | clusters[0][0]->signal_vci_tgt_mtty.print_trace("[SIG]MTTY"); |
---|
| 1255 | } // end trace |
---|
| 1256 | |
---|
[621] | 1257 | sc_start(sc_core::sc_time(1, SC_NS)); |
---|
| 1258 | } |
---|
| 1259 | |
---|
| 1260 | |
---|
| 1261 | // Free memory |
---|
| 1262 | for (size_t i = 0; i < (X_SIZE * Y_SIZE); i++) |
---|
| 1263 | { |
---|
| 1264 | size_t x = i / Y_SIZE; |
---|
| 1265 | size_t y = i % Y_SIZE; |
---|
| 1266 | delete clusters[x][y]; |
---|
| 1267 | } |
---|
| 1268 | |
---|
| 1269 | return EXIT_SUCCESS; |
---|
| 1270 | } |
---|
| 1271 | |
---|
| 1272 | |
---|
[628] | 1273 | void handler(int dummy = 0) |
---|
| 1274 | { |
---|
[621] | 1275 | stop_called = true; |
---|
| 1276 | sc_stop(); |
---|
| 1277 | } |
---|
| 1278 | |
---|
| 1279 | void voidhandler(int dummy = 0) {} |
---|
| 1280 | |
---|
| 1281 | int sc_main (int argc, char *argv[]) |
---|
| 1282 | { |
---|
| 1283 | signal(SIGINT, handler); |
---|
| 1284 | signal(SIGPIPE, voidhandler); |
---|
| 1285 | |
---|
| 1286 | try { |
---|
| 1287 | return _main(argc, argv); |
---|
| 1288 | } catch (std::exception &e) { |
---|
| 1289 | std::cout << e.what() << std::endl; |
---|
| 1290 | } catch (...) { |
---|
| 1291 | std::cout << "Unknown exception occured" << std::endl; |
---|
| 1292 | throw; |
---|
| 1293 | } |
---|
| 1294 | return 1; |
---|
| 1295 | } |
---|
| 1296 | |
---|
| 1297 | |
---|
| 1298 | // Local Variables: |
---|
| 1299 | // tab-width: 3 |
---|
| 1300 | // c-basic-offset: 3 |
---|
| 1301 | // c-file-offsets:((innamespace . 0)(inline-open . 0)) |
---|
| 1302 | // indent-tabs-mode: nil |
---|
| 1303 | // End: |
---|
| 1304 | |
---|
| 1305 | // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 |
---|