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source: trunk/platforms/tsar_generic_leti/top.cpp @ 792

Last change on this file since 792 was 792, checked in by cfuguet, 10 years ago

tsar_generic_leti: modifying platform to comply with the new hard_config.h

Peripheral base addresses are defined in the hard_config.h file.
Every platform parameter (X_SIZE, Y_SIZE, ...) are defined in this file too.

File size: 55.8 KB

Rev	Line
[621]	1	/////////////////////////////////////////////////////////////////////////
[664]	2	// File: top.cpp (for tsar_generic_leti)
[792]	3	// Author: Alain Greiner
[621]	4	// Copyright: UPMC/LIP6
[628]	5	// Date : february 2014
[621]	6	// This program is released under the GNU public license
	7	/////////////////////////////////////////////////////////////////////////
[681]	8	// This file define a generic TSAR architecture, fully compatible
	9	// with the VLSI Hardware prototype developped by CEA-LETI and LIP6
	10	// in the framework of the SHARP project.
[792]	11	//
[621]	12	// The processor is a MIPS32 processor wrapped in a GDB server
	13	// (this is defined in the tsar_xbar_cluster).
[792]	14	//
[681]	15	// It does not use an external ROM, as the boot code is (pre)loaded
	16	// in cluster (0,0) memory at address 0x0.
[621]	17	//
	18	// The physical address space is 40 bits.
	19	// The 8 address MSB bits define the cluster index.
	20	//
[681]	21	// The main hardware parameters are the mesh size (X_SIZE & Y_SIZE),
	22	// and the number of processors per cluster (NB_PROCS_MAX).
	23	// The number of clusters cannot be larger than 128.
[621]	24	// The number of processors per cluster cannot be larger than 4.
[792]	25	//
[628]	26	// Each cluster contains:
	27	// - 5 dspin_local_crossbar (local interconnect)
	28	// - 5 dspin_router (global interconnect)
	29	// - up to 4 vci_cc_vcache wrapping a MIPS32 processor
	30	// - 1 vci_mem_cache
	31	// - 1 vci_xicu
	32	// - 1 vci_simple_ram (to model the L3 cache).
[621]	33	//
[681]	34	// Each processor receives 4 consecutive IRQ lines from the local XICU.
[664]	35	//
[628]	36	// In all clusters, the MEMC IRQ line (signaling a late write error)
	37	// is connected to XICU HWI[8]
[681]	38	// The cluster (0,0) contains two "backup" peripherals:
[628]	39	// - one block device controller, whose IRQ is connected to XICU HWI[9].
	40	// - one single channel TTY controller, whose IRQ is connected to XICU HWI[10].
[621]	41	//
[628]	42	// The cluster internal architecture is defined in file tsar_leti_cluster,
	43	// that must be considered as an extension of this top.cpp file.
[621]	44	//
[792]	45	// Besides the hardware components in clusters, "external" peripherals
[628]	46	// are connected to an external IO bus (implemented as a vci_local_crossbar):
[792]	47	// - one disk controller
	48	// - one multi-channel ethernet controller
[628]	49	// - one multi-channel chained buffer dma controller
[792]	50	// - one multi-channel tty controller
	51	// - one frame buffer controller
[664]	52	// - one 32 channels iopic controller
[628]	53	//
[792]	54	// This IOBUS is connected to the north port of the DIR_CMD
[681]	55	// and DIR_RSP routers, in cluster(X_SIZE-1, Y_SIZE-1).
[628]	56	// For all external peripherals, the hardware interrupts (HWI) are
[664]	57	// translated to write interrupts (WTI) by the iopic component:
	58	// - IOPIC HWI[1:0] connected to IRQ_NIC_RX[1:0]
[792]	59	// - IOPIC HWI[3:2] connected to IRQ_NIC_TX[1:0]
[664]	60	// - IOPIC HWI[7:4] connected to IRQ_CMA_TX[3:0]]
	61	// - IOPIC HWI[8] connected to IRQ_BDEV
	62	// - IOPIC HWI[15:9] unused (grounded)
	63	// - IOPIC HWI[23:16] connected to IRQ_TTY_RX[7:0]]
	64	// - IOPIC HWI[31:24] connected to IRQ_TTY_TX[7:0]]
[628]	65	////////////////////////////////////////////////////////////////////////////
	66	// The following parameters must be defined in the hard_config.h file :
[621]	67	// - X_WIDTH : number of bits for x coordinate (must be 4)
	68	// - Y_WIDTH : number of bits for y coordinate (must be 4)
[681]	69	// - X_SIZE : number of clusters in a row (1,2,4,8,16)
	70	// - Y_SIZE : number of clusters in a column (1,2,4,8)
[628]	71	// - NB_PROCS_MAX : number of processors per cluster (1, 2 or 4)
[664]	72	// - NB_CMA_CHANNELS : number of CMA channels in I/0 cluster (4 max)
	73	// - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (8 max)
[628]	74	// - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (2 max)
[792]	75	//
[621]	76	// Some other hardware parameters are not used when compiling the OS,
[628]	77	// and are only defined in this top.cpp file:
[792]	78	// - XRAM_LATENCY : external ram latency
[621]	79	// - MEMC_WAYS : L2 cache number of ways
	80	// - MEMC_SETS : L2 cache number of sets
[628]	81	// - L1_IWAYS : L1 cache instruction number of ways
	82	// - L1_ISETS : L1 cache instruction number of sets
	83	// - L1_DWAYS : L1 cache data number of ways
	84	// - L1_DSETS : L1 cache data number of sets
[621]	85	// - FBUF_X_SIZE : width of frame buffer (pixels)
	86	// - FBUF_Y_SIZE : heigth of frame buffer (lines)
[792]	87	// - BDEV_IMAGE_NAME : file pathname for block device
[621]	88	// - NIC_RX_NAME : file pathname for NIC received packets
	89	// - NIC_TX_NAME : file pathname for NIC transmited packets
[628]	90	// - NIC_MAC4 : MAC address
	91	// - NIC_MAC2 : MAC address
[621]	92	/////////////////////////////////////////////////////////////////////////
	93	// General policy for 40 bits physical address decoding:
	94	// All physical segments base addresses are multiple of 1 Mbytes
[792]	95	// (=> the 24 LSB bits = 0, and the 16 MSB bits define the target)
[621]	96	// The (X_WIDTH + Y_WIDTH) MSB bits (left aligned) define
	97	// the cluster index, and the LADR bits define the local index:
	98	// \|X_ID\|Y_ID\| LADR \| OFFSET \|
	99	// \| 4 \| 4 \| 8 \| 24 \|
	100	/////////////////////////////////////////////////////////////////////////
	101	// General policy for 14 bits SRCID decoding:
	102	// Each component is identified by (x_id, y_id, l_id) tuple.
	103	// \|X_ID\|Y_ID\| L_ID \|
	104	// \| 4 \| 4 \| 6 \|
	105	/////////////////////////////////////////////////////////////////////////
	106
	107	#include <systemc>
	108	#include <sys/time.h>
	109	#include <iostream>
	110	#include <sstream>
	111	#include <cstdlib>
	112	#include <cstdarg>
	113	#include <stdint.h>
	114
	115	#include "gdbserver.h"
	116	#include "mapping_table.h"
	117	#include "tsar_leti_cluster.h"
[628]	118	#include "vci_local_crossbar.h"
	119	#include "vci_dspin_initiator_wrapper.h"
	120	#include "vci_dspin_target_wrapper.h"
	121	#include "vci_multi_tty.h"
	122	#include "vci_multi_nic.h"
	123	#include "vci_chbuf_dma.h"
	124	#include "vci_block_device_tsar.h"
	125	#include "vci_framebuffer.h"
	126	#include "vci_iopic.h"
[621]	127	#include "alloc_elems.h"
	128
[792]	129	#include "hard_config.h"
[621]	130
	131	///////////////////////////////////////////////////
	132	// Parallelisation
	133	///////////////////////////////////////////////////
[708]	134	#define USE_OPENMP _OPENMP
[621]	135
	136	#if USE_OPENMP
	137	#include <omp.h>
	138	#endif
	139
	140	///////////////////////////////////////////////////
	141	// cluster index (from x,y coordinates)
	142	///////////////////////////////////////////////////
	143
[692]	144	#define cluster(x,y) ((y) + ((x) << Y_WIDTH))
[621]	145
	146	///////////////////////////////////////////////////////////
[792]	147	// DSPIN parameters
[621]	148	///////////////////////////////////////////////////////////
	149
	150	#define dspin_cmd_width 39
	151	#define dspin_rsp_width 32
	152
	153	///////////////////////////////////////////////////////////
[792]	154	// VCI parameters
[621]	155	///////////////////////////////////////////////////////////
	156
	157	#define vci_cell_width_int 4
	158	#define vci_cell_width_ext 8
	159	#define vci_address_width 40
	160	#define vci_plen_width 8
	161	#define vci_rerror_width 1
	162	#define vci_clen_width 1
	163	#define vci_rflag_width 1
	164	#define vci_srcid_width 14
	165	#define vci_pktid_width 4
	166	#define vci_trdid_width 4
	167	#define vci_wrplen_width 1
	168
	169
[664]	170	/////////////////////////////////////////////////////////////////////////////////////////
[792]	171	// Secondary Hardware Parameters
[664]	172	/////////////////////////////////////////////////////////////////////////////////////////
[621]	173
[664]	174	#define MAX_TTY_CHANNELS 8
	175	#define MAX_CMA_CHANNELS 4
	176	#define MAX_NIC_CHANNELS 2
	177
[621]	178	#define XRAM_LATENCY 0
	179
	180	#define MEMC_WAYS 16
	181	#define MEMC_SETS 256
	182
	183	#define L1_IWAYS 4
	184	#define L1_ISETS 64
	185
	186	#define L1_DWAYS 4
	187	#define L1_DSETS 64
	188
[628]	189	#define NIC_MAC4 0XBABEF00D
	190	#define NIC_MAC2 0xBEEF
[708]	191	#define NIC_RX_NAME "/dev/null"
	192	#define NIC_TX_NAME "/dev/null"
[621]	193
	194	#define NORTH 0
	195	#define SOUTH 1
	196	#define EAST 2
	197	#define WEST 3
	198
[664]	199	///////////////////////////////////////////////////////////////////////////////////////
[792]	200	// DEBUG Parameters default values
[664]	201	///////////////////////////////////////////////////////////////////////////////////////
[621]	202
[681]	203	#define MAX_FROZEN_CYCLES 500000
[621]	204
[664]	205	///////////////////////////////////////////////////////////////////////////////////////
[792]	206	// LOCAL TGTID & SRCID definition
[621]	207	// For all components: global TGTID = global SRCID = cluster_index
[664]	208	///////////////////////////////////////////////////////////////////////////////////////
[621]	209
[664]	210	#define MEMC_TGTID 0
	211	#define XICU_TGTID 1
	212	#define MTTY_TGTID 2
	213	#define BDEV_TGTID 3
	214	#define FBUF_TGTID 4
	215	#define MNIC_TGTID 5
	216	#define CDMA_TGTID 6
	217	#define IOPI_TGTID 7
[621]	218
[664]	219	#define BDEV_SRCID NB_PROCS_MAX
	220	#define CDMA_SRCID NB_PROCS_MAX + 1
	221	#define IOPI_SRCID NB_PROCS_MAX + 2
[628]	222
[621]	223	bool stop_called = false;
	224
	225	/////////////////////////////////
	226	int _main(int argc, char *argv[])
	227	{
	228	using namespace sc_core;
	229	using namespace soclib::caba;
	230	using namespace soclib::common;
	231
[692]	232	uint32_t ncycles = 0xFFFFFFFF; // max simulated cycles
	233	size_t threads = 1; // simulator's threads number
	234	bool trace_ok = false; // trace activated
	235	uint32_t trace_from = 0; // trace start cycle
	236	bool trace_proc_ok = false; // detailed proc trace activated
	237	size_t trace_memc_ok = false; // detailed memc trace activated
[792]	238	size_t trace_memc_id = 0; // index of memc to be traced
[692]	239	size_t trace_proc_id = 0; // index of proc to be traced
	240	uint32_t frozen_cycles = MAX_FROZEN_CYCLES;
[792]	241	char soft_name[256] = "soft.elf";
	242	char disk_name[256] = "disk.img";
	243	char ramdisk_name[256] = "disk.img@0x02000000:";
[621]	244	struct timeval t1,t2;
	245	uint64_t ms1,ms2;
	246
	247	////////////// command line arguments //////////////////////
	248	if (argc > 1)
	249	{
	250	for (int n = 1; n < argc; n = n + 2)
	251	{
	252	if ((strcmp(argv[n], "-NCYCLES") == 0) && (n + 1 < argc))
	253	{
	254	ncycles = (uint64_t) strtol(argv[n + 1], NULL, 0);
	255	}
	256	else if ((strcmp(argv[n],"-DEBUG") == 0) && (n + 1 < argc))
	257	{
	258	trace_ok = true;
	259	trace_from = (uint32_t) strtol(argv[n + 1], NULL, 0);
	260	}
	261	else if ((strcmp(argv[n], "-MEMCID") == 0) && (n + 1 < argc))
	262	{
	263	trace_memc_ok = true;
	264	trace_memc_id = (size_t) strtol(argv[n + 1], NULL, 0);
	265	size_t x = trace_memc_id >> Y_WIDTH;
	266	size_t y = trace_memc_id & ((1<<Y_WIDTH)-1);
	267
[681]	268	assert( (x < X_SIZE) and (y < (Y_SIZE)) and
[621]	269	"MEMCID parameter refers a not valid memory cache");
	270	}
	271	else if ((strcmp(argv[n], "-PROCID") == 0) && (n + 1 < argc))
	272	{
	273	trace_proc_ok = true;
	274	trace_proc_id = (size_t) strtol(argv[n + 1], NULL, 0);
	275	size_t cluster_xy = trace_proc_id / NB_PROCS_MAX ;
	276	size_t x = cluster_xy >> Y_WIDTH;
	277	size_t y = cluster_xy & ((1<<Y_WIDTH)-1);
[664]	278	size_t l = trace_proc_id % NB_PROCS_MAX ;
[621]	279
[692]	280	assert( (x < X_SIZE) and (y < Y_SIZE) and (l < NB_PROCS_MAX) and
[621]	281	"PROCID parameter refers a not valid processor");
	282	}
[692]	283	else if ((strcmp(argv[n], "-SOFT") == 0) && ((n + 1) < argc))
	284	{
[792]	285	strcpy(soft_name, argv[n + 1]);
[692]	286	}
	287	else if ((strcmp(argv[n], "-DISK") == 0) && ((n + 1) < argc))
	288	{
	289	strcpy(disk_name, argv[n + 1]);
	290	}
	291	else if ((strcmp(argv[n], "-RAMDISK") == 0) && ((n + 1) < argc))
	292	{
[792]	293	strcpy(ramdisk_name, argv[n + 1]);
[692]	294	}
[621]	295	else if ((strcmp(argv[n], "-THREADS") == 0) && ((n + 1) < argc))
	296	{
[628]	297	threads = (size_t) strtol(argv[n + 1], NULL, 0);
	298	threads = (threads < 1) ? 1 : threads;
[621]	299	}
	300	else if ((strcmp(argv[n], "-FROZEN") == 0) && (n + 1 < argc))
	301	{
	302	frozen_cycles = (uint32_t) strtol(argv[n + 1], NULL, 0);
	303	}
	304	else
	305	{
	306	std::cout << " Arguments are (key,value) couples." << std::endl;
	307	std::cout << " The order is not important." << std::endl;
	308	std::cout << " Accepted arguments are :" << std::endl << std::endl;
	309	std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl;
	310	std::cout << " -DEBUG debug_start_cycle" << std::endl;
[692]	311	std::cout << " -SOFT path to soft" << std::endl;
	312	std::cout << " -DISK path to disk image" << std::endl;
	313	std::cout << " -RAMDISK path to ramdisk image" << std::endl;
[621]	314	std::cout << " -THREADS simulator's threads number" << std::endl;
	315	std::cout << " -FROZEN max_number_of_lines" << std::endl;
	316	std::cout << " -PERIOD number_of_cycles between trace" << std::endl;
	317	std::cout << " -MEMCID index_memc_to_be_traced" << std::endl;
	318	std::cout << " -PROCID index_proc_to_be_traced" << std::endl;
	319	exit(0);
	320	}
	321	}
	322	}
	323
	324	// checking hardware parameters
[792]	325	assert( ((X_SIZE==1) or (X_SIZE==2) or (X_SIZE==4) or (X_SIZE==8) or
	326	(X_SIZE==16)) and
[681]	327	"Illegal X_SIZE parameter" );
[621]	328
[792]	329	assert( ((Y_SIZE==1) or (Y_SIZE==2) or (Y_SIZE==4) or (Y_SIZE==8)) and
[681]	330	"Illegal Y_SIZE parameter" );
[621]	331
[664]	332	assert( (NB_PROCS_MAX <= 4) and
[681]	333	"Illegal NB_PROCS_MAX parameter" );
[621]	334
[664]	335	assert( (NB_CMA_CHANNELS <= MAX_CMA_CHANNELS) and
[628]	336	"The NB_CMA_CHANNELS parameter cannot be larger than 4" );
[621]	337
[664]	338	assert( (NB_TTY_CHANNELS <= MAX_TTY_CHANNELS) and
	339	"The NB_TTY_CHANNELS parameter cannot be larger than 8" );
[621]	340
[664]	341	assert( (NB_NIC_CHANNELS <= MAX_NIC_CHANNELS) and
[628]	342	"The NB_NIC_CHANNELS parameter cannot be larger than 2" );
[621]	343
	344	assert( (vci_address_width == 40) and
	345	"VCI address width with the GIET must be 40 bits" );
	346
	347	assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and
	348	"ERROR: you must have X_WIDTH == Y_WIDTH == 4");
[792]	349
[621]	350	std::cout << std::endl;
	351
	352	std::cout << " - X_SIZE = " << X_SIZE << std::endl;
	353	std::cout << " - Y_SIZE = " << Y_SIZE << std::endl;
	354	std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl;
	355	std::cout << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl;
	356	std::cout << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl;
	357	std::cout << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl;
	358	std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl;
	359	std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl;
	360	std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl;
	361	std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl;
	362	std::cout << " - MAX_CYCLES = " << ncycles << std::endl;
	363	std::cout << " - RESET_ADDRESS = " << RESET_ADDRESS << std::endl;
[692]	364	std::cout << " - SOFT_FILENAME = " << soft_name << std::endl;
	365	std::cout << " - DISK_IMAGENAME = " << disk_name << std::endl;
	366	std::cout << " - RAMDISK_FILENAME = " << ramdisk_name << std::endl;
	367	std::cout << " - OPENMP THREADS = " << threads << std::endl;
[621]	368
	369	std::cout << std::endl;
	370
	371	// Internal and External VCI parameters definition
	372	typedef soclib::caba::VciParams<vci_cell_width_int,
	373	vci_plen_width,
	374	vci_address_width,
	375	vci_rerror_width,
	376	vci_clen_width,
	377	vci_rflag_width,
	378	vci_srcid_width,
	379	vci_pktid_width,
	380	vci_trdid_width,
	381	vci_wrplen_width> vci_param_int;
	382
	383	typedef soclib::caba::VciParams<vci_cell_width_ext,
	384	vci_plen_width,
	385	vci_address_width,
	386	vci_rerror_width,
	387	vci_clen_width,
	388	vci_rflag_width,
	389	vci_srcid_width,
	390	vci_pktid_width,
	391	vci_trdid_width,
	392	vci_wrplen_width> vci_param_ext;
	393
	394	#if USE_OPENMP
	395	omp_set_dynamic(false);
[628]	396	omp_set_num_threads(threads);
[621]	397	std::cerr << "Built with openmp version " << _OPENMP << std::endl;
	398	#endif
	399
	400
[628]	401	///////////////////////////////////////
	402	// Direct Network Mapping Table
	403	///////////////////////////////////////
[621]	404
[792]	405	MappingTable maptabd(vci_address_width,
	406	IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH),
	407	IntTab(X_WIDTH + Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH),
[628]	408	0x00FF000000ULL);
[621]	409
[628]	410	// replicated segments
[621]	411	for (size_t x = 0; x < X_SIZE; x++)
	412	{
[681]	413	for (size_t y = 0; y < (Y_SIZE) ; y++)
[621]	414	{
	415	sc_uint<vci_address_width> offset;
[628]	416	offset = ((sc_uint<vci_address_width>)cluster(x,y)) << 32;
[621]	417
	418	std::ostringstream si;
	419	si << "seg_xicu_" << x << "_" << y;
[792]	420	maptabd.add(Segment(si.str(), SEG_XCU_BASE + offset, SEG_XCU_SIZE,
[621]	421	IntTab(cluster(x,y),XICU_TGTID), false));
	422
	423	std::ostringstream sd;
[628]	424	sd << "seg_mcfg_" << x << "_" << y;
[792]	425	maptabd.add(Segment(sd.str(), SEG_MMC_BASE + offset, SEG_MMC_SIZE,
[628]	426	IntTab(cluster(x,y),MEMC_TGTID), false));
[621]	427
	428	std::ostringstream sh;
	429	sh << "seg_memc_" << x << "_" << y;
[792]	430	maptabd.add(Segment(sh.str(), SEG_RAM_BASE + offset, SEG_RAM_SIZE,
[621]	431	IntTab(cluster(x,y),MEMC_TGTID), true));
	432	}
	433	}
[628]	434
[664]	435	// segments for peripherals in cluster(0,0)
[792]	436	maptabd.add(Segment("seg_tty0", SEG_TTY_BASE, SEG_TTY_SIZE,
[628]	437	IntTab(cluster(0,0),MTTY_TGTID), false));
	438
[792]	439	maptabd.add(Segment("seg_ioc0", SEG_IOC_BASE, SEG_IOC_SIZE,
[628]	440	IntTab(cluster(0,0),BDEV_TGTID), false));
	441
[681]	442	// segments for peripherals in cluster_io (X_SIZE-1,Y_SIZE)
[628]	443	sc_uint<vci_address_width> offset;
[681]	444	offset = ((sc_uint<vci_address_width>)cluster(X_SIZE-1,Y_SIZE)) << 32;
[628]	445
[792]	446	maptabd.add(Segment("seg_mtty", SEG_TTY_BASE + offset, SEG_TTY_SIZE,
[681]	447	IntTab(cluster(X_SIZE-1, Y_SIZE),MTTY_TGTID), false));
[628]	448
[792]	449	maptabd.add(Segment("seg_fbuf", SEG_FBF_BASE + offset, SEG_FBF_SIZE,
[681]	450	IntTab(cluster(X_SIZE-1, Y_SIZE),FBUF_TGTID), false));
[628]	451
[792]	452	maptabd.add(Segment("seg_bdev", SEG_IOC_BASE + offset, SEG_IOC_SIZE,
[681]	453	IntTab(cluster(X_SIZE-1, Y_SIZE),BDEV_TGTID), false));
[628]	454
[792]	455	maptabd.add(Segment("seg_mnic", SEG_NIC_BASE + offset, SEG_NIC_SIZE,
[681]	456	IntTab(cluster(X_SIZE-1, Y_SIZE),MNIC_TGTID), false));
[628]	457
[792]	458	maptabd.add(Segment("seg_cdma", SEG_CMA_BASE + offset, SEG_CMA_SIZE,
[681]	459	IntTab(cluster(X_SIZE-1, Y_SIZE),CDMA_TGTID), false));
[628]	460
[792]	461	maptabd.add(Segment("seg_iopi", SEG_PIC_BASE + offset, SEG_PIC_SIZE,
[681]	462	IntTab(cluster(X_SIZE-1, Y_SIZE),IOPI_TGTID), false));
[628]	463
[621]	464	std::cout << maptabd << std::endl;
	465
[628]	466	/////////////////////////////////////////////////
	467	// Ram network mapping table
	468	/////////////////////////////////////////////////
[621]	469
[792]	470	MappingTable maptabx(vci_address_width,
	471	IntTab(X_WIDTH+Y_WIDTH),
	472	IntTab(X_WIDTH+Y_WIDTH),
[628]	473	0x00FF000000ULL);
[621]	474
[628]	475	for (size_t x = 0; x < X_SIZE; x++)
	476	{
[681]	477	for (size_t y = 0; y < (Y_SIZE) ; y++)
[792]	478	{
[628]	479	sc_uint<vci_address_width> offset;
[792]	480	offset = (sc_uint<vci_address_width>)cluster(x,y)
[628]	481	<< (vci_address_width-X_WIDTH-Y_WIDTH);
[621]	482
[628]	483	std::ostringstream sh;
	484	sh << "x_seg_memc_" << x << "_" << y;
[621]	485
[792]	486	maptabx.add(Segment(sh.str(), SEG_RAM_BASE + offset,
	487	SEG_RAM_SIZE, IntTab(cluster(x,y)), false));
[628]	488	}
	489	}
	490	std::cout << maptabx << std::endl;
[621]	491
[628]	492	////////////////////
	493	// Signals
	494	///////////////////
[621]	495
[628]	496	sc_clock signal_clk("clk");
	497	sc_signal<bool> signal_resetn("resetn");
[621]	498
[628]	499	// IRQs from external peripherals
	500	sc_signal<bool> signal_irq_bdev;
	501	sc_signal<bool> signal_irq_mnic_rx[NB_NIC_CHANNELS];
	502	sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS];
[664]	503	sc_signal<bool> signal_irq_mtty_rx[NB_TTY_CHANNELS];
	504	// sc_signal<bool> signal_irq_mtty_tx[NB_TTY_CHANNELS];
[628]	505	sc_signal<bool> signal_irq_cdma[NB_CMA_CHANNELS];
	506	sc_signal<bool> signal_irq_false;
	507
[621]	508	// Horizontal inter-clusters DSPIN signals
[628]	509	DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_inc =
[681]	510	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", X_SIZE-1, Y_SIZE);
[628]	511	DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_dec =
[681]	512	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", X_SIZE-1, Y_SIZE);
[621]	513
[628]	514	DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_inc =
[681]	515	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", X_SIZE-1, Y_SIZE);
[628]	516	DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_dec =
[681]	517	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", X_SIZE-1, Y_SIZE);
[628]	518
	519	DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_inc =
[681]	520	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_inc", X_SIZE-1, Y_SIZE);
[628]	521	DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_dec =
[681]	522	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_dec", X_SIZE-1, Y_SIZE);
[628]	523
	524	DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_inc =
[681]	525	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_inc", X_SIZE-1, Y_SIZE);
[628]	526	DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_dec =
[681]	527	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_dec", X_SIZE-1, Y_SIZE);
[628]	528
	529	DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_inc =
[681]	530	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_inc", X_SIZE-1, Y_SIZE);
[628]	531	DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_dec =
[681]	532	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_dec", X_SIZE-1, Y_SIZE);
[628]	533
[621]	534	// Vertical inter-clusters DSPIN signals
[628]	535	DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_inc =
[681]	536	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", X_SIZE, Y_SIZE-1);
[628]	537	DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_dec =
[681]	538	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", X_SIZE, Y_SIZE-1);
[621]	539
[628]	540	DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_inc =
[681]	541	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", X_SIZE, Y_SIZE-1);
[628]	542	DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_dec =
[681]	543	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", X_SIZE, Y_SIZE-1);
[621]	544
[628]	545	DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_inc =
[681]	546	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_inc", X_SIZE, Y_SIZE-1);
[628]	547	DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_dec =
[681]	548	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_dec", X_SIZE, Y_SIZE-1);
[621]	549
[628]	550	DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_inc =
[681]	551	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_inc", X_SIZE, Y_SIZE-1);
[628]	552	DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_dec =
[681]	553	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_dec", X_SIZE, Y_SIZE-1);
[628]	554
	555	DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_inc =
[681]	556	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_inc", X_SIZE, Y_SIZE-1);
[628]	557	DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_dec =
[681]	558	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_dec", X_SIZE, Y_SIZE-1);
[628]	559
	560	// Mesh boundaries DSPIN signals (Most of those signals are not used...)
	561	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_in =
[681]	562	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_in" , X_SIZE, Y_SIZE, 4);
[628]	563	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_out =
[681]	564	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_out", X_SIZE, Y_SIZE, 4);
[628]	565
	566	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_in =
[681]	567	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_in" , X_SIZE, Y_SIZE, 4);
[628]	568	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_out =
[681]	569	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_out", X_SIZE, Y_SIZE, 4);
[628]	570
	571	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_in =
[681]	572	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_in" , X_SIZE, Y_SIZE, 4);
[628]	573	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_out =
[681]	574	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_out", X_SIZE, Y_SIZE, 4);
[628]	575
	576	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_in =
[681]	577	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_in" , X_SIZE, Y_SIZE, 4);
[628]	578	DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_out =
[681]	579	alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_out", X_SIZE, Y_SIZE, 4);
[628]	580
	581	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_in =
[681]	582	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_in" , X_SIZE, Y_SIZE, 4);
[628]	583	DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_out =
[681]	584	alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_out", X_SIZE, Y_SIZE, 4);
[628]	585
	586	// VCI signals for iobus and peripherals
	587	VciSignals<vci_param_int> signal_vci_ini_bdev("signal_vci_ini_bdev");
	588	VciSignals<vci_param_int> signal_vci_ini_cdma("signal_vci_ini_cdma");
	589	VciSignals<vci_param_int> signal_vci_ini_iopi("signal_vci_ini_iopi");
	590
[792]	591	VciSignals<vci_param_int>* signal_vci_ini_proc =
[628]	592	alloc_elems<VciSignals<vci_param_int> >("signal_vci_ini_proc", NB_PROCS_MAX );
	593
	594	VciSignals<vci_param_int> signal_vci_tgt_memc("signal_vci_tgt_memc");
	595	VciSignals<vci_param_int> signal_vci_tgt_xicu("signal_vci_tgt_xicu");
	596	VciSignals<vci_param_int> signal_vci_tgt_bdev("signal_vci_tgt_bdev");
	597	VciSignals<vci_param_int> signal_vci_tgt_mtty("signal_vci_tgt_mtty");
	598	VciSignals<vci_param_int> signal_vci_tgt_fbuf("signal_vci_tgt_fbuf");
	599	VciSignals<vci_param_int> signal_vci_tgt_mnic("signal_vci_tgt_mnic");
	600	VciSignals<vci_param_int> signal_vci_tgt_cdma("signal_vci_tgt_cdma");
	601	VciSignals<vci_param_int> signal_vci_tgt_iopi("signal_vci_tgt_iopi");
	602
	603	VciSignals<vci_param_int> signal_vci_cmd_to_noc("signal_vci_cmd_to_noc");
	604	VciSignals<vci_param_int> signal_vci_cmd_from_noc("signal_vci_cmd_from_noc");
[792]	605
[621]	606	////////////////////////////
[792]	607	// Loader
[621]	608	////////////////////////////
	609
[792]	610	#if USE_RAMDISK
[692]	611	soclib::common::Loader loader( soft_name, ramdisk_name );
[664]	612	#else
[692]	613	soclib::common::Loader loader( soft_name );
[664]	614	#endif
[708]	615	loader.memory_default(0xAA);
[621]	616
[630]	617	///////////////////////////
	618	// processor iss
	619	///////////////////////////
	620
[621]	621	typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss;
[630]	622	proc_iss::set_loader( loader );
[621]	623
[664]	624	//////////////////////////////////////////////////////////////
[681]	625	// mesh construction: only (X_SIZE) * (Y_SIZE) clusters
[664]	626	//////////////////////////////////////////////////////////////
[621]	627
	628	TsarLetiCluster<dspin_cmd_width,
	629	dspin_rsp_width,
	630	vci_param_int,
[681]	631	vci_param_ext>* clusters[X_SIZE][Y_SIZE];
[621]	632
	633	#if USE_OPENMP
	634	#pragma omp parallel
	635	{
	636	#pragma omp for
	637	#endif
[681]	638	for (size_t i = 0; i < (X_SIZE * (Y_SIZE)); i++)
[621]	639	{
[681]	640	size_t x = i / (Y_SIZE);
	641	size_t y = i % (Y_SIZE);
[621]	642
	643	#if USE_OPENMP
	644	#pragma omp critical
	645	{
	646	#endif
	647	std::cout << std::endl;
[792]	648	std::cout << "Cluster_" << std::dec << x << "_" << y
[628]	649	<< " with cluster_xy = " << std::hex << cluster(x,y) << std::endl;
[621]	650	std::cout << std::endl;
	651
[664]	652	std::ostringstream cluster_name;
	653	cluster_name << "cluster_" << std::dec << x << "_" << y;
	654
[621]	655	clusters[x][y] = new TsarLetiCluster<dspin_cmd_width,
	656	dspin_rsp_width,
	657	vci_param_int,
	658	vci_param_ext>
	659	(
[664]	660	cluster_name.str().c_str(),
[621]	661	NB_PROCS_MAX,
	662	x,
	663	y,
	664	cluster(x,y),
	665	maptabd,
	666	maptabx,
	667	RESET_ADDRESS,
	668	X_WIDTH,
	669	Y_WIDTH,
	670	vci_srcid_width - X_WIDTH - Y_WIDTH, // l_id width,
	671	MEMC_TGTID,
	672	XICU_TGTID,
	673	MTTY_TGTID,
	674	BDEV_TGTID,
[692]	675	disk_name,
[621]	676	MEMC_WAYS,
	677	MEMC_SETS,
	678	L1_IWAYS,
	679	L1_ISETS,
	680	L1_DWAYS,
	681	L1_DSETS,
	682	XRAM_LATENCY,
	683	loader,
	684	frozen_cycles,
	685	trace_from,
[792]	686	trace_proc_ok,
[621]	687	trace_proc_id,
[792]	688	trace_memc_ok,
[621]	689	trace_memc_id
	690	);
	691
	692	#if USE_OPENMP
	693	} // end critical
	694	#endif
	695	} // end for
	696	#if USE_OPENMP
	697	}
	698	#endif
	699
[628]	700	//////////////////////////////////////////////////////////////////
	701	// IO bus and external peripherals in cluster[X_SIZE-1,Y_SIZE]
[664]	702	// - 6 local targets : FBF, TTY, CMA, NIC, PIC, IOC
	703	// - 3 local initiators : IOC, CMA, PIC
	704	// There is no PROC, no MEMC and no XICU in this cluster,
	705	// but the crossbar has (NB_PROCS_MAX + 3) intiators and
	706	// 8 targets, in order to use the same SRCID and TGTID space
[792]	707	// (same mapping table for the internal components,
	708	// and for the external peripherals)
[628]	709	//////////////////////////////////////////////////////////////////
[621]	710
[664]	711	std::cout << std::endl;
	712	std::cout << " Building IO cluster (external peripherals)" << std::endl;
	713	std::cout << std::endl;
[792]	714
[681]	715	size_t cluster_io = cluster(X_SIZE-1, Y_SIZE);
[621]	716
[792]	717	//////////// vci_local_crossbar
[628]	718	VciLocalCrossbar<vci_param_int>*
	719	iobus = new VciLocalCrossbar<vci_param_int>(
	720	"iobus",
	721	maptabd, // mapping table
	722	cluster_io, // cluster_xy
	723	NB_PROCS_MAX + 3, // number of local initiators
	724	8, // number of local targets
	725	BDEV_TGTID ); // default target index
[621]	726
[792]	727	//////////// vci_framebuffer
[628]	728	VciFrameBuffer<vci_param_int>*
	729	fbuf = new VciFrameBuffer<vci_param_int>(
	730	"fbuf",
	731	IntTab(cluster_io, FBUF_TGTID),
	732	maptabd,
	733	FBUF_X_SIZE, FBUF_Y_SIZE );
[621]	734
[792]	735	//////////// vci_block_device
[628]	736	VciBlockDeviceTsar<vci_param_int>*
	737	bdev = new VciBlockDeviceTsar<vci_param_int>(
	738	"bdev",
	739	maptabd,
	740	IntTab(cluster_io, BDEV_SRCID),
	741	IntTab(cluster_io, BDEV_TGTID),
[692]	742	disk_name,
[628]	743	512, // block size
	744	64 ); // burst size
	745
[792]	746	//////////// vci_multi_nic
[628]	747	VciMultiNic<vci_param_int>*
	748	mnic = new VciMultiNic<vci_param_int>(
[681]	749	"mnic",
[628]	750	IntTab(cluster_io, MNIC_TGTID),
	751	maptabd,
	752	NB_NIC_CHANNELS,
	753	NIC_MAC4,
	754	NIC_MAC2,
	755	NIC_RX_NAME,
	756	NIC_TX_NAME );
	757
[792]	758	///////////// vci_chbuf_dma
[628]	759	VciChbufDma<vci_param_int>*
	760	cdma = new VciChbufDma<vci_param_int>(
	761	"cdma",
	762	maptabd,
	763	IntTab(cluster_io, CDMA_SRCID),
	764	IntTab(cluster_io, CDMA_TGTID),
	765	64, // burst size
[792]	766	NB_CMA_CHANNELS );
[628]	767
	768	////////////// vci_multi_tty
	769	std::vector<std::string> vect_names;
	770	for (size_t id = 0; id < NB_TTY_CHANNELS; id++)
	771	{
	772	std::ostringstream term_name;
	773	term_name << "ext_" << id;
	774	vect_names.push_back(term_name.str().c_str());
	775	}
	776
[792]	777	VciMultiTty<vci_param_int>*
[628]	778	mtty = new VciMultiTty<vci_param_int>(
	779	"mtty",
	780	IntTab(cluster_io, MTTY_TGTID),
	781	maptabd,
	782	vect_names );
	783
	784	///////////// vci_iopic
	785	VciIopic<vci_param_int>*
	786	iopic = new VciIopic<vci_param_int>(
	787	"iopic",
	788	maptabd,
	789	IntTab(cluster_io, IOPI_SRCID),
	790	IntTab(cluster_io, IOPI_TGTID),
[792]	791	32 );
[628]	792
[792]	793	////////////// vci_dspin wrappers
[628]	794	VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>*
	795	wt_iobus = new VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>(
	796	"wt_bdev",
	797	vci_srcid_width );
	798
	799	VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>*
	800	wi_iobus = new VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>(
	801	"wi_bdev",
	802	vci_srcid_width );
	803
	804	///////////////////////////////////////////////////////////////
[792]	805	// Net-list
[628]	806	///////////////////////////////////////////////////////////////
	807
[792]	808	// iobus
	809	iobus->p_clk (signal_clk);
[628]	810	iobus->p_resetn (signal_resetn);
	811
	812	iobus->p_target_to_up (signal_vci_cmd_from_noc);
	813	iobus->p_initiator_to_up (signal_vci_cmd_to_noc);
	814
	815	iobus->p_to_target[MEMC_TGTID] (signal_vci_tgt_memc);
	816	iobus->p_to_target[XICU_TGTID] (signal_vci_tgt_xicu);
	817	iobus->p_to_target[MTTY_TGTID] (signal_vci_tgt_mtty);
	818	iobus->p_to_target[FBUF_TGTID] (signal_vci_tgt_fbuf);
	819	iobus->p_to_target[MNIC_TGTID] (signal_vci_tgt_mnic);
	820	iobus->p_to_target[BDEV_TGTID] (signal_vci_tgt_bdev);
	821	iobus->p_to_target[CDMA_TGTID] (signal_vci_tgt_cdma);
	822	iobus->p_to_target[IOPI_TGTID] (signal_vci_tgt_iopi);
	823
	824	for( size_t p=0 ; p<NB_PROCS_MAX ; p++ )
	825	{
	826	iobus->p_to_initiator[p] (signal_vci_ini_proc[p]);
	827	}
	828	iobus->p_to_initiator[BDEV_SRCID] (signal_vci_ini_bdev);
	829	iobus->p_to_initiator[CDMA_SRCID] (signal_vci_ini_cdma);
	830	iobus->p_to_initiator[IOPI_SRCID] (signal_vci_ini_iopi);
	831
	832	std::cout << " - IOBUS connected" << std::endl;
	833
	834	// block_device
	835	bdev->p_clk (signal_clk);
	836	bdev->p_resetn (signal_resetn);
	837	bdev->p_vci_target (signal_vci_tgt_bdev);
	838	bdev->p_vci_initiator (signal_vci_ini_bdev);
	839	bdev->p_irq (signal_irq_bdev);
	840
	841	std::cout << " - BDEV connected" << std::endl;
	842
	843	// frame_buffer
	844	fbuf->p_clk (signal_clk);
	845	fbuf->p_resetn (signal_resetn);
	846	fbuf->p_vci (signal_vci_tgt_fbuf);
	847
	848	std::cout << " - FBUF connected" << std::endl;
	849
	850	// multi_nic
	851	mnic->p_clk (signal_clk);
	852	mnic->p_resetn (signal_resetn);
	853	mnic->p_vci (signal_vci_tgt_mnic);
	854	for ( size_t i=0 ; i<NB_NIC_CHANNELS ; i++ )
	855	{
	856	mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]);
	857	mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]);
	858	}
	859
	860	std::cout << " - MNIC connected" << std::endl;
	861
	862	// chbuf_dma
	863	cdma->p_clk (signal_clk);
	864	cdma->p_resetn (signal_resetn);
	865	cdma->p_vci_target (signal_vci_tgt_cdma);
	866	cdma->p_vci_initiator (signal_vci_ini_cdma);
	867	for ( size_t i=0 ; i<NB_CMA_CHANNELS ; i++)
	868	{
	869	cdma->p_irq[i] (signal_irq_cdma[i]);
	870	}
	871
	872	std::cout << " - CDMA connected" << std::endl;
	873
	874	// multi_tty
	875	mtty->p_clk (signal_clk);
	876	mtty->p_resetn (signal_resetn);
	877	mtty->p_vci (signal_vci_tgt_mtty);
	878	for ( size_t i=0 ; i<NB_TTY_CHANNELS ; i++ )
	879	{
[664]	880	mtty->p_irq[i] (signal_irq_mtty_rx[i]);
[628]	881	}
	882
	883	std::cout << " - MTTY connected" << std::endl;
	884
	885	// iopic
[664]	886	// NB_NIC_CHANNELS <= 2
	887	// NB_CMA_CHANNELS <= 4
	888	// NB_TTY_CHANNELS <= 8
[628]	889	iopic->p_clk (signal_clk);
	890	iopic->p_resetn (signal_resetn);
	891	iopic->p_vci_target (signal_vci_tgt_iopi);
	892	iopic->p_vci_initiator (signal_vci_ini_iopi);
[664]	893	for ( size_t i=0 ; i<32 ; i++)
[628]	894	{
	895	if (i < NB_NIC_CHANNELS) iopic->p_hwi[i] (signal_irq_mnic_rx[i]);
	896	else if(i < 2 ) iopic->p_hwi[i] (signal_irq_false);
	897	else if(i < 2+NB_NIC_CHANNELS) iopic->p_hwi[i] (signal_irq_mnic_tx[i-2]);
	898	else if(i < 4 ) iopic->p_hwi[i] (signal_irq_false);
	899	else if(i < 4+NB_CMA_CHANNELS) iopic->p_hwi[i] (signal_irq_cdma[i-4]);
[664]	900	else if(i < 8) iopic->p_hwi[i] (signal_irq_false);
	901	else if(i == 8) iopic->p_hwi[i] (signal_irq_bdev);
	902	else if(i < 16) iopic->p_hwi[i] (signal_irq_false);
	903	else if(i < 16+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_mtty_rx[i-16]);
	904	else if(i < 24) iopic->p_hwi[i] (signal_irq_false);
	905	else if(i < 24+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_false);
	906	// else if(i < 24+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_mtty_tx[i-24]);
[628]	907	else iopic->p_hwi[i] (signal_irq_false);
	908	}
	909
[664]	910	std::cout << " - IOPIC connected" << std::endl;
	911
[628]	912	// vci/dspin wrappers
	913	wi_iobus->p_clk (signal_clk);
	914	wi_iobus->p_resetn (signal_resetn);
	915	wi_iobus->p_vci (signal_vci_cmd_to_noc);
[681]	916	wi_iobus->p_dspin_cmd (signal_dspin_bound_cmd_in[X_SIZE-1][Y_SIZE-1][NORTH]);
	917	wi_iobus->p_dspin_rsp (signal_dspin_bound_rsp_out[X_SIZE-1][Y_SIZE-1][NORTH]);
[628]	918
	919	// vci/dspin wrappers
	920	wt_iobus->p_clk (signal_clk);
	921	wt_iobus->p_resetn (signal_resetn);
	922	wt_iobus->p_vci (signal_vci_cmd_from_noc);
[681]	923	wt_iobus->p_dspin_cmd (signal_dspin_bound_cmd_out[X_SIZE-1][Y_SIZE-1][NORTH]);
	924	wt_iobus->p_dspin_rsp (signal_dspin_bound_rsp_in[X_SIZE-1][Y_SIZE-1][NORTH]);
[628]	925
	926	// Clock & RESET for clusters
	927	for (size_t x = 0; x < (X_SIZE); x++)
	928	{
[681]	929	for (size_t y = 0; y < (Y_SIZE); y++)
[628]	930	{
	931	clusters[x][y]->p_clk (signal_clk);
	932	clusters[x][y]->p_resetn (signal_resetn);
	933	}
	934	}
	935
	936	// Inter Clusters horizontal connections
	937	if (X_SIZE > 1)
	938	{
	939	for (size_t x = 0; x < (X_SIZE-1); x++)
	940	{
[681]	941	for (size_t y = 0; y < (Y_SIZE); y++)
[628]	942	{
	943	clusters[x][y]->p_cmd_out[EAST] (signal_dspin_h_cmd_inc[x][y]);
	944	clusters[x+1][y]->p_cmd_in[WEST] (signal_dspin_h_cmd_inc[x][y]);
	945	clusters[x][y]->p_cmd_in[EAST] (signal_dspin_h_cmd_dec[x][y]);
	946	clusters[x+1][y]->p_cmd_out[WEST] (signal_dspin_h_cmd_dec[x][y]);
	947
	948	clusters[x][y]->p_rsp_out[EAST] (signal_dspin_h_rsp_inc[x][y]);
	949	clusters[x+1][y]->p_rsp_in[WEST] (signal_dspin_h_rsp_inc[x][y]);
	950	clusters[x][y]->p_rsp_in[EAST] (signal_dspin_h_rsp_dec[x][y]);
	951	clusters[x+1][y]->p_rsp_out[WEST] (signal_dspin_h_rsp_dec[x][y]);
	952
	953	clusters[x][y]->p_m2p_out[EAST] (signal_dspin_h_m2p_inc[x][y]);
	954	clusters[x+1][y]->p_m2p_in[WEST] (signal_dspin_h_m2p_inc[x][y]);
	955	clusters[x][y]->p_m2p_in[EAST] (signal_dspin_h_m2p_dec[x][y]);
	956	clusters[x+1][y]->p_m2p_out[WEST] (signal_dspin_h_m2p_dec[x][y]);
	957
	958	clusters[x][y]->p_p2m_out[EAST] (signal_dspin_h_p2m_inc[x][y]);
	959	clusters[x+1][y]->p_p2m_in[WEST] (signal_dspin_h_p2m_inc[x][y]);
	960	clusters[x][y]->p_p2m_in[EAST] (signal_dspin_h_p2m_dec[x][y]);
	961	clusters[x+1][y]->p_p2m_out[WEST] (signal_dspin_h_p2m_dec[x][y]);
	962
	963	clusters[x][y]->p_cla_out[EAST] (signal_dspin_h_cla_inc[x][y]);
	964	clusters[x+1][y]->p_cla_in[WEST] (signal_dspin_h_cla_inc[x][y]);
	965	clusters[x][y]->p_cla_in[EAST] (signal_dspin_h_cla_dec[x][y]);
	966	clusters[x+1][y]->p_cla_out[WEST] (signal_dspin_h_cla_dec[x][y]);
[621]	967	}
[628]	968	}
	969	}
[792]	970	std::cout << std::endl << "Horizontal connections done" << std::endl;
[621]	971
[628]	972	// Inter Clusters vertical connections
[792]	973	if (Y_SIZE > 1)
[628]	974	{
[681]	975	for (size_t y = 0; y < (Y_SIZE-1); y++)
[628]	976	{
	977	for (size_t x = 0; x < X_SIZE; x++)
	978	{
	979	clusters[x][y]->p_cmd_out[NORTH] (signal_dspin_v_cmd_inc[x][y]);
	980	clusters[x][y+1]->p_cmd_in[SOUTH] (signal_dspin_v_cmd_inc[x][y]);
	981	clusters[x][y]->p_cmd_in[NORTH] (signal_dspin_v_cmd_dec[x][y]);
	982	clusters[x][y+1]->p_cmd_out[SOUTH] (signal_dspin_v_cmd_dec[x][y]);
	983
	984	clusters[x][y]->p_rsp_out[NORTH] (signal_dspin_v_rsp_inc[x][y]);
	985	clusters[x][y+1]->p_rsp_in[SOUTH] (signal_dspin_v_rsp_inc[x][y]);
	986	clusters[x][y]->p_rsp_in[NORTH] (signal_dspin_v_rsp_dec[x][y]);
	987	clusters[x][y+1]->p_rsp_out[SOUTH] (signal_dspin_v_rsp_dec[x][y]);
	988
	989	clusters[x][y]->p_m2p_out[NORTH] (signal_dspin_v_m2p_inc[x][y]);
	990	clusters[x][y+1]->p_m2p_in[SOUTH] (signal_dspin_v_m2p_inc[x][y]);
	991	clusters[x][y]->p_m2p_in[NORTH] (signal_dspin_v_m2p_dec[x][y]);
	992	clusters[x][y+1]->p_m2p_out[SOUTH] (signal_dspin_v_m2p_dec[x][y]);
	993
	994	clusters[x][y]->p_p2m_out[NORTH] (signal_dspin_v_p2m_inc[x][y]);
	995	clusters[x][y+1]->p_p2m_in[SOUTH] (signal_dspin_v_p2m_inc[x][y]);
	996	clusters[x][y]->p_p2m_in[NORTH] (signal_dspin_v_p2m_dec[x][y]);
	997	clusters[x][y+1]->p_p2m_out[SOUTH] (signal_dspin_v_p2m_dec[x][y]);
	998
	999	clusters[x][y]->p_cla_out[NORTH] (signal_dspin_v_cla_inc[x][y]);
	1000	clusters[x][y+1]->p_cla_in[SOUTH] (signal_dspin_v_cla_inc[x][y]);
	1001	clusters[x][y]->p_cla_in[NORTH] (signal_dspin_v_cla_dec[x][y]);
	1002	clusters[x][y+1]->p_cla_out[SOUTH] (signal_dspin_v_cla_dec[x][y]);
[621]	1003	}
[628]	1004	}
	1005	}
	1006	std::cout << std::endl << "Vertical connections done" << std::endl;
[621]	1007
[628]	1008	// East & West boundary cluster connections
[681]	1009	for (size_t y = 0; y < (Y_SIZE); y++)
[628]	1010	{
	1011	clusters[0][y]->p_cmd_in[WEST] (signal_dspin_bound_cmd_in[0][y][WEST]);
	1012	clusters[0][y]->p_cmd_out[WEST] (signal_dspin_bound_cmd_out[0][y][WEST]);
	1013	clusters[X_SIZE-1][y]->p_cmd_in[EAST] (signal_dspin_bound_cmd_in[X_SIZE-1][y][EAST]);
	1014	clusters[X_SIZE-1][y]->p_cmd_out[EAST] (signal_dspin_bound_cmd_out[X_SIZE-1][y][EAST]);
[621]	1015
[628]	1016	clusters[0][y]->p_rsp_in[WEST] (signal_dspin_bound_rsp_in[0][y][WEST]);
	1017	clusters[0][y]->p_rsp_out[WEST] (signal_dspin_bound_rsp_out[0][y][WEST]);
	1018	clusters[X_SIZE-1][y]->p_rsp_in[EAST] (signal_dspin_bound_rsp_in[X_SIZE-1][y][EAST]);
	1019	clusters[X_SIZE-1][y]->p_rsp_out[EAST] (signal_dspin_bound_rsp_out[X_SIZE-1][y][EAST]);
[621]	1020
[628]	1021	clusters[0][y]->p_m2p_in[WEST] (signal_dspin_bound_m2p_in[0][y][WEST]);
	1022	clusters[0][y]->p_m2p_out[WEST] (signal_dspin_bound_m2p_out[0][y][WEST]);
	1023	clusters[X_SIZE-1][y]->p_m2p_in[EAST] (signal_dspin_bound_m2p_in[X_SIZE-1][y][EAST]);
	1024	clusters[X_SIZE-1][y]->p_m2p_out[EAST] (signal_dspin_bound_m2p_out[X_SIZE-1][y][EAST]);
[621]	1025
[628]	1026	clusters[0][y]->p_p2m_in[WEST] (signal_dspin_bound_p2m_in[0][y][WEST]);
	1027	clusters[0][y]->p_p2m_out[WEST] (signal_dspin_bound_p2m_out[0][y][WEST]);
	1028	clusters[X_SIZE-1][y]->p_p2m_in[EAST] (signal_dspin_bound_p2m_in[X_SIZE-1][y][EAST]);
	1029	clusters[X_SIZE-1][y]->p_p2m_out[EAST] (signal_dspin_bound_p2m_out[X_SIZE-1][y][EAST]);
[621]	1030
[628]	1031	clusters[0][y]->p_cla_in[WEST] (signal_dspin_bound_cla_in[0][y][WEST]);
	1032	clusters[0][y]->p_cla_out[WEST] (signal_dspin_bound_cla_out[0][y][WEST]);
	1033	clusters[X_SIZE-1][y]->p_cla_in[EAST] (signal_dspin_bound_cla_in[X_SIZE-1][y][EAST]);
	1034	clusters[X_SIZE-1][y]->p_cla_out[EAST] (signal_dspin_bound_cla_out[X_SIZE-1][y][EAST]);
	1035	}
[621]	1036
[664]	1037	std::cout << std::endl << "West & East boundaries connections done" << std::endl;
	1038
[628]	1039	// North & South boundary clusters connections
	1040	for (size_t x = 0; x < X_SIZE; x++)
	1041	{
	1042	clusters[x][0]->p_cmd_in[SOUTH] (signal_dspin_bound_cmd_in[x][0][SOUTH]);
	1043	clusters[x][0]->p_cmd_out[SOUTH] (signal_dspin_bound_cmd_out[x][0][SOUTH]);
[681]	1044	clusters[x][Y_SIZE-1]->p_cmd_in[NORTH] (signal_dspin_bound_cmd_in[x][Y_SIZE-1][NORTH]);
	1045	clusters[x][Y_SIZE-1]->p_cmd_out[NORTH] (signal_dspin_bound_cmd_out[x][Y_SIZE-1][NORTH]);
[621]	1046
[628]	1047	clusters[x][0]->p_rsp_in[SOUTH] (signal_dspin_bound_rsp_in[x][0][SOUTH]);
	1048	clusters[x][0]->p_rsp_out[SOUTH] (signal_dspin_bound_rsp_out[x][0][SOUTH]);
[681]	1049	clusters[x][Y_SIZE-1]->p_rsp_in[NORTH] (signal_dspin_bound_rsp_in[x][Y_SIZE-1][NORTH]);
	1050	clusters[x][Y_SIZE-1]->p_rsp_out[NORTH] (signal_dspin_bound_rsp_out[x][Y_SIZE-1][NORTH]);
[621]	1051
[628]	1052	clusters[x][0]->p_m2p_in[SOUTH] (signal_dspin_bound_m2p_in[x][0][SOUTH]);
	1053	clusters[x][0]->p_m2p_out[SOUTH] (signal_dspin_bound_m2p_out[x][0][SOUTH]);
[681]	1054	clusters[x][Y_SIZE-1]->p_m2p_in[NORTH] (signal_dspin_bound_m2p_in[x][Y_SIZE-1][NORTH]);
	1055	clusters[x][Y_SIZE-1]->p_m2p_out[NORTH] (signal_dspin_bound_m2p_out[x][Y_SIZE-1][NORTH]);
[621]	1056
[628]	1057	clusters[x][0]->p_p2m_in[SOUTH] (signal_dspin_bound_p2m_in[x][0][SOUTH]);
	1058	clusters[x][0]->p_p2m_out[SOUTH] (signal_dspin_bound_p2m_out[x][0][SOUTH]);
[681]	1059	clusters[x][Y_SIZE-1]->p_p2m_in[NORTH] (signal_dspin_bound_p2m_in[x][Y_SIZE-1][NORTH]);
	1060	clusters[x][Y_SIZE-1]->p_p2m_out[NORTH] (signal_dspin_bound_p2m_out[x][Y_SIZE-1][NORTH]);
[628]	1061
	1062	clusters[x][0]->p_cla_in[SOUTH] (signal_dspin_bound_cla_in[x][0][SOUTH]);
	1063	clusters[x][0]->p_cla_out[SOUTH] (signal_dspin_bound_cla_out[x][0][SOUTH]);
[681]	1064	clusters[x][Y_SIZE-1]->p_cla_in[NORTH] (signal_dspin_bound_cla_in[x][Y_SIZE-1][NORTH]);
	1065	clusters[x][Y_SIZE-1]->p_cla_out[NORTH] (signal_dspin_bound_cla_out[x][Y_SIZE-1][NORTH]);
[628]	1066	}
	1067
[664]	1068	std::cout << std::endl << "North & South boundaries connections done" << std::endl;
	1069
[628]	1070	std::cout << std::endl;
	1071
	1072	////////////////////////////////////////////////////////
	1073	// Simulation
	1074	///////////////////////////////////////////////////////
	1075
	1076	sc_start(sc_core::sc_time(0, SC_NS));
	1077	signal_resetn = false;
	1078	signal_irq_false = false;
	1079
	1080	// set network boundaries signals default values
	1081	// for all boundary clusters but the IO cluster
	1082	for (size_t x = 0; x < X_SIZE ; x++)
	1083	{
[681]	1084	for (size_t y = 0; y < Y_SIZE ; y++)
[628]	1085	{
	1086	for (size_t face = 0; face < 4; face++)
	1087	{
[681]	1088	if ( (x != X_SIZE-1) or (y != Y_SIZE-1) or (face != NORTH) )
[628]	1089	{
	1090	signal_dspin_bound_cmd_in [x][y][face].write = false;
	1091	signal_dspin_bound_cmd_in [x][y][face].read = true;
	1092	signal_dspin_bound_cmd_out[x][y][face].write = false;
	1093	signal_dspin_bound_cmd_out[x][y][face].read = true;
	1094
	1095	signal_dspin_bound_rsp_in [x][y][face].write = false;
	1096	signal_dspin_bound_rsp_in [x][y][face].read = true;
	1097	signal_dspin_bound_rsp_out[x][y][face].write = false;
	1098	signal_dspin_bound_rsp_out[x][y][face].read = true;
	1099	}
	1100
	1101	signal_dspin_bound_m2p_in [x][y][face].write = false;
	1102	signal_dspin_bound_m2p_in [x][y][face].read = true;
	1103	signal_dspin_bound_m2p_out[x][y][face].write = false;
	1104	signal_dspin_bound_m2p_out[x][y][face].read = true;
	1105
	1106	signal_dspin_bound_p2m_in [x][y][face].write = false;
	1107	signal_dspin_bound_p2m_in [x][y][face].read = true;
	1108	signal_dspin_bound_p2m_out[x][y][face].write = false;
	1109	signal_dspin_bound_p2m_out[x][y][face].read = true;
	1110
	1111	signal_dspin_bound_cla_in [x][y][face].write = false;
	1112	signal_dspin_bound_cla_in [x][y][face].read = true;
	1113	signal_dspin_bound_cla_out[x][y][face].write = false;
	1114	signal_dspin_bound_cla_out[x][y][face].read = true;
[621]	1115	}
[628]	1116	}
	1117	}
[621]	1118
[792]	1119	// set default values for VCI signals connected to unused ports on iobus
[664]	1120	signal_vci_tgt_memc.rspval = false;
	1121	signal_vci_tgt_xicu.rspval = false;
	1122	for ( size_t p = 0 ; p < NB_PROCS_MAX ; p++ ) signal_vci_ini_proc[p].cmdval = false;
	1123
[628]	1124	sc_start(sc_core::sc_time(1, SC_NS));
	1125	signal_resetn = true;
[621]	1126
[792]	1127	if (gettimeofday(&t1, NULL) != 0)
[628]	1128	{
	1129	perror("gettimeofday");
	1130	return EXIT_FAILURE;
	1131	}
[621]	1132
[664]	1133	// variable used for IRQ trace
	1134	bool prev_irq_bdev = false;
	1135	bool prev_irq_mtty_rx[8];
	1136	bool prev_irq_proc[16][16][4];
[621]	1137
[664]	1138	for( size_t x = 0 ; x<8 ; x++ ) prev_irq_mtty_rx[x] = false;
[621]	1139
[664]	1140	for( size_t x = 0 ; x<16 ; x++ )
	1141	for( size_t y = 0 ; y<16 ; y++ )
	1142	for( size_t i = 0 ; i<4 ; i++ ) prev_irq_proc[x][y][i] = false;
[621]	1143
[664]	1144	for (uint64_t n = 1; n < ncycles && !stop_called; n++)
	1145	{
	1146	// Monitor a specific address for L1 & L2 caches
	1147	// clusters[0][0]->proc[0]->cache_monitor(0x110002C078ULL);
	1148	// clusters[1][1]->memc->cache_monitor(0x110002c078ULL);
[621]	1149
[664]	1150	// stats display
	1151	if( (n % 5000000) == 0)
	1152	{
[621]	1153
[792]	1154	if (gettimeofday(&t2, NULL) != 0)
[664]	1155	{
	1156	perror("gettimeofday");
	1157	return EXIT_FAILURE;
	1158	}
[621]	1159
[664]	1160	ms1 = (uint64_t) t1.tv_sec * 1000ULL + (uint64_t) t1.tv_usec / 1000;
	1161	ms2 = (uint64_t) t2.tv_sec * 1000ULL + (uint64_t) t2.tv_usec / 1000;
[792]	1162	std::cerr << "platform clock frequency "
[664]	1163	<< (double) 5000000 / (double) (ms2 - ms1) << "Khz" << std::endl;
[621]	1164
[792]	1165	if (gettimeofday(&t1, NULL) != 0)
[664]	1166	{
	1167	perror("gettimeofday");
	1168	return EXIT_FAILURE;
	1169	}
	1170	}
[621]	1171
[664]	1172	// trace display
	1173	if ( trace_ok and (n > trace_from) )
	1174	{
	1175	std::cout << "****************** cycle " << std::dec << n ;
	1176	std::cout << " ************************************************" << std::endl;
[621]	1177
[664]	1178	size_t l = 0;
	1179	size_t x = 0;
	1180	size_t y = 0;
[621]	1181
[664]	1182	if ( trace_proc_ok )
	1183	{
	1184	l = trace_proc_id % NB_PROCS_MAX ;
	1185	x = (trace_proc_id / NB_PROCS_MAX) >> Y_WIDTH ;
	1186	y = (trace_proc_id / NB_PROCS_MAX) & ((1<<Y_WIDTH) - 1);
[621]	1187
[664]	1188	std::ostringstream proc_signame;
	1189	proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ;
[681]	1190	clusters[x][y]->proc[l]->print_trace(1);
[664]	1191	clusters[x][y]->signal_vci_ini_proc[l].print_trace(proc_signame.str());
[628]	1192
[664]	1193	std::ostringstream xicu_signame;
	1194	xicu_signame << "[SIG]XICU_" << x << "_" << y ;
	1195	clusters[x][y]->xicu->print_trace(0);
	1196	clusters[x][y]->signal_vci_tgt_xicu.print_trace(xicu_signame.str());
	1197	}
[628]	1198
[664]	1199	if ( trace_memc_ok )
	1200	{
	1201	x = trace_memc_id >> Y_WIDTH;
	1202	y = trace_memc_id & ((1<<Y_WIDTH) - 1);
	1203
	1204	std::ostringstream smemc;
	1205	smemc << "[SIG]MEMC_" << x << "_" << y;
	1206	std::ostringstream sxram;
	1207	sxram << "[SIG]XRAM_" << x << "_" << y;
	1208
	1209	clusters[x][y]->memc->print_trace();
	1210	clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str());
	1211	clusters[x][y]->signal_vci_xram.print_trace(sxram.str());
[792]	1212	}
[664]	1213
	1214	// trace coherence signals
	1215	// clusters[0][0]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_0_0]");
	1216	// clusters[0][1]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_0_1]");
	1217	// clusters[1][0]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_1_0]");
	1218	// clusters[1][1]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_1_1]");
	1219
	1220	// clusters[0][0]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_0_0]");
	1221	// clusters[0][1]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_0_1]");
	1222	// clusters[1][0]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_1_0]");
	1223	// clusters[1][1]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_1_1]");
	1224
	1225	// trace xbar(s) m2p
	1226	// clusters[0][0]->xbar_m2p->print_trace();
	1227	// clusters[1][0]->xbar_m2p->print_trace();
	1228	// clusters[0][1]->xbar_m2p->print_trace();
	1229	// clusters[1][1]->xbar_m2p->print_trace();
[792]	1230
[664]	1231	// trace router(s) m2p
	1232	// clusters[0][0]->router_m2p->print_trace();
	1233	// clusters[1][0]->router_m2p->print_trace();
	1234	// clusters[0][1]->router_m2p->print_trace();
	1235	// clusters[1][1]->router_m2p->print_trace();
[792]	1236
[664]	1237	// trace external ioc
	1238	bdev->print_trace();
	1239	signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT");
	1240	signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI");
[621]	1241
[664]	1242	// trace external iopic
	1243	iopic->print_trace();
	1244	signal_vci_tgt_iopi.print_trace("[SIG]IOPI_TGT");
	1245	signal_vci_ini_iopi.print_trace("[SIG]IOPI_INI");
[621]	1246
[664]	1247	// trace internal tty
	1248	// clusters[0][0]->mtty->print_trace();
	1249	// clusters[0][0]->signal_vci_tgt_mtty.print_trace("[SIG]MTTY");
[628]	1250
[664]	1251	} // end trace
[621]	1252
[664]	1253	if (0)
	1254	{
	1255	// trace BDV interrupts events
[792]	1256	if ( signal_irq_bdev.read() != prev_irq_bdev )
[664]	1257	{
	1258	prev_irq_bdev = signal_irq_bdev.read();
	1259	std::cout << std::dec << "@@@ IRQ_BDEV = " << signal_irq_bdev.read()
	1260	<< " at cycle " << n << std::endl;
	1261	}
[792]	1262
[664]	1263	// trace TTY interrupts events
	1264	for ( size_t x = 0 ; x < 8 ; x++ )
	1265	{
[792]	1266	if ( signal_irq_mtty_rx[x].read() != prev_irq_mtty_rx[x] )
[664]	1267	{
	1268	prev_irq_mtty_rx[x] = signal_irq_mtty_rx[x].read();
[792]	1269	std::cout << std::dec << "@@@ IRQ_MTTY["<<x<<"] = "
[664]	1270	<< signal_irq_mtty_rx[x].read()
	1271	<< " at cycle " << n << std::endl;
	1272	}
	1273	}
[621]	1274
[664]	1275	// trace processor interrupts events
[681]	1276	for ( size_t x = 0 ; x < X_SIZE ; x++ )
	1277	for ( size_t y = 0 ; y < Y_SIZE ; y++ )
	1278	for ( size_t i = 0 ; i < NB_PROCS_MAX ; i++ )
[664]	1279	{
	1280	if ( clusters[x][y]->signal_proc_irq[i] != prev_irq_proc[x][y][i] )
[792]	1281	{
[664]	1282	prev_irq_proc[x][y][i] = clusters[x][y]->signal_proc_irq[i];
	1283	std::cout << std::dec << "@@@ IRQ_PROC["<<x<<","<<y<<","<<i<<"] = "
	1284	<< clusters[x][y]->signal_proc_irq[i]
	1285	<< " at cycle " << n << std::endl;
	1286	}
	1287	}
	1288
	1289	// trace VCI transactions on IOPIC and XCU(0,0)
	1290	signal_vci_tgt_iopi.print_trace("@@@ IOPI_TGT");
	1291	signal_vci_ini_iopi.print_trace("@@@ IOPI_INI");
	1292	clusters[0][0]->signal_vci_tgt_xicu.print_trace("@@@ XCU_0_0");
	1293	}
	1294
	1295	sc_start(sc_core::sc_time(1, SC_NS));
	1296	}
	1297	// Free memory
[681]	1298	for (size_t i = 0 ; i < (X_SIZE * Y_SIZE) ; i++)
[664]	1299	{
[681]	1300	size_t x = i / (Y_SIZE);
	1301	size_t y = i % (Y_SIZE);
[664]	1302	delete clusters[x][y];
	1303	}
	1304
	1305	return EXIT_SUCCESS;
[621]	1306	}
	1307
[792]	1308	void handler(int dummy = 0)
[628]	1309	{
[621]	1310	stop_called = true;
	1311	sc_stop();
	1312	}
	1313
	1314	void voidhandler(int dummy = 0) {}
	1315
	1316	int sc_main (int argc, char *argv[])
	1317	{
	1318	signal(SIGINT, handler);
	1319	signal(SIGPIPE, voidhandler);
	1320
	1321	try {
	1322	return _main(argc, argv);
	1323	} catch (std::exception &e) {
	1324	std::cout << e.what() << std::endl;
	1325	} catch (...) {
	1326	std::cout << "Unknown exception occured" << std::endl;
	1327	throw;
	1328	}
	1329	return 1;
	1330	}
	1331
	1332
	1333	// Local Variables:
	1334	// tab-width: 3
	1335	// c-basic-offset: 3
	1336	// c-file-offsets:((innamespace . 0)(inline-open . 0))
	1337	// indent-tabs-mode: nil
	1338	// End:
	1339
	1340	// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3

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Project-Id-Version: Trac 0.12
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POT-Creation-Date: 2018-07-07 16:55+0000
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