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tsar_leti_cluster.cpp

Last change on this file was 1029, checked in by cfuguet, 8 years ago

Support the cluster 0 to be the IO cluster.

Update the arch.py to allow the execution of new revisions of the Giet-VM.

File size: 26.5 KB

Line
1	//////////////////////////////////////////////////////////////////////////////
2	// File: tsar_leti_cluster.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : february 2014
6	// This program is released under the GNU public license
7	//////////////////////////////////////////////////////////////////////////////
8
9	#include "../include/tsar_leti_cluster.h"
10
11	namespace soclib {
12	namespace caba {
13
14	////////////////////////////////////////////////////////////////////////////////////
15	template<size_t dspin_cmd_width,
16	size_t dspin_rsp_width,
17	typename vci_param_int,
18	typename vci_param_ext> TsarLetiCluster<dspin_cmd_width,
19	dspin_rsp_width,
20	vci_param_int,
21	vci_param_ext>::TsarLetiCluster(
22	////////////////////////////////////////////////////////////////////////////////////
23	sc_module_name insname,
24	size_t nb_procs,
25	size_t x_id,
26	size_t y_id,
27	size_t cluster_xy,
28	const soclib::common::MappingTable &mtd,
29	const soclib::common::MappingTable &mtx,
30	uint32_t reset_address,
31	size_t x_width,
32	size_t y_width,
33	size_t l_width,
34	size_t p_width,
35	size_t tgtid_memc,
36	size_t tgtid_xicu,
37	size_t tgtid_mtty,
38	size_t tgtid_bdev,
39	bool use_ramdisk,
40	const char* disk_pathname,
41	size_t memc_ways,
42	size_t memc_sets,
43	size_t l1_i_ways,
44	size_t l1_i_sets,
45	size_t l1_d_ways,
46	size_t l1_d_sets,
47	size_t xram_latency,
48	const Loader &loader,
49	uint32_t frozen_cycles,
50	uint32_t trace_start_cycle,
51	bool trace_proc_ok,
52	uint32_t trace_proc_id,
53	bool trace_memc_ok,
54	uint32_t trace_memc_id )
55	: soclib::caba::BaseModule(insname),
56	m_nprocs(nb_procs),
57	p_clk("clk"),
58	p_resetn("resetn")
59
60	{
61	/////////////////////////////////////////////////////////////////////////////
62	// Vectors of ports definition and allocation
63	/////////////////////////////////////////////////////////////////////////////
64
65	p_cmd_in = alloc_elems<DspinInput<dspin_cmd_width> > ("p_cmd_in", 4);
66	p_cmd_out = alloc_elems<DspinOutput<dspin_cmd_width> > ("p_cmd_out", 4);
67
68	p_rsp_in = alloc_elems<DspinInput<dspin_rsp_width> > ("p_rsp_in", 4);
69	p_rsp_out = alloc_elems<DspinOutput<dspin_rsp_width> > ("p_rsp_out", 4);
70
71	p_m2p_in = alloc_elems<DspinInput<dspin_cmd_width> > ("p_m2p_in", 4);
72	p_m2p_out = alloc_elems<DspinOutput<dspin_cmd_width> > ("p_m2p_out", 4);
73
74	p_p2m_in = alloc_elems<DspinInput<dspin_rsp_width> > ("p_p2m_in", 4);
75	p_p2m_out = alloc_elems<DspinOutput<dspin_rsp_width> > ("p_p2m_out", 4);
76
77	p_cla_in = alloc_elems<DspinInput<dspin_cmd_width> > ("p_cla_in", 4);
78	p_cla_out = alloc_elems<DspinOutput<dspin_cmd_width> > ("p_cla_out", 4);
79
80	/////////////////////////////////////////////////////////////////////////////
81	// Components definition and allocation
82	/////////////////////////////////////////////////////////////////////////////
83
84	// The processor is a MIPS32 wrapped in the GDB server
85	// the reset address is defined by the reset_address argument
86	typedef GdbServer<Mips32ElIss> mips_iss;
87	mips_iss::setResetAddress( reset_address );
88
89	for (size_t p = 0; p < nb_procs; p++)
90	{
91	uint32_t global_proc_id = (cluster_xy << p_width) + p;
92	uint32_t global_cc_id = (cluster_xy << l_width) + p;
93	bool trace_ok = trace_proc_ok and (trace_proc_id == global_proc_id);
94
95	std::ostringstream sproc;
96	sproc << "proc_" << x_id << "_" << y_id << "_" << p;
97	proc[p] = new VciCcVCacheWrapper<vci_param_int,
98	dspin_cmd_width,
99	dspin_rsp_width,
100	mips_iss >(
101	sproc.str().c_str(),
102	global_proc_id, // GLOBAL PROC_ID
103	mtd, // Mapping Table
104	IntTab(cluster_xy,p), // SRCID
105	global_cc_id, // GLOBAL_CC_ID
106	8, // ITLB ways
107	8, // ITLB sets
108	8, // DTLB ways
109	8, // DTLB sets
110	l1_i_ways,l1_i_sets, 16, // ICACHE size
111	l1_d_ways,l1_d_sets, 16, // DCACHE size
112	4, // WBUF nlines
113	4, // WBUF nwords
114	x_width,
115	y_width,
116	frozen_cycles, // max frozen cycles
117	trace_start_cycle,
118	trace_ok );
119	}
120
121	/////////////////////////////////////////////////////////////////////////////
122	bool trace_ok = trace_memc_ok and (trace_memc_id == cluster_xy);
123	std::ostringstream smemc;
124	smemc << "memc_" << x_id << "_" << y_id;
125	memc = new VciMemCache<vci_param_int,
126	vci_param_ext,
127	dspin_rsp_width,
128	dspin_cmd_width>(
129	smemc.str().c_str(),
130	mtd, // Mapping Table direct space
131	mtx, // Mapping Table external space
132	IntTab(cluster_xy), // SRCID external space
133	IntTab(cluster_xy, tgtid_memc), // TGTID direct space
134	x_width, // Number of x bits in platform
135	y_width, // Number of y bits in platform
136	memc_ways, memc_sets, 16, // CACHE SIZE
137	3, // MAX NUMBER OF COPIES
138	4096, // HEAP SIZE
139	8, // TRANSACTION TABLE DEPTH
140	8, // UPDATE TABLE DEPTH
141	8, // INVALIDATE TABLE DEPTH
142	trace_start_cycle,
143	trace_ok );
144
145	/////////////////////////////////////////////////////////////////////////////
146	std::ostringstream sxram;
147	sxram << "xram_" << x_id << "_" << y_id;
148	xram = new VciSimpleRam<vci_param_ext>(
149	sxram.str().c_str(),
150	IntTab(cluster_xy),
151	mtx,
152	loader,
153	xram_latency);
154
155	/////////////////////////////////////////////////////////////////////////////
156	std::ostringstream sxicu;
157	sxicu << "xicu_" << x_id << "_" << y_id;
158	xicu = new VciXicu<vci_param_int>(
159	sxicu.str().c_str(),
160	mtd, // mapping table
161	IntTab(cluster_xy, tgtid_xicu), // TGTID_D
162	16, // number of timer IRQs
163	16, // number of hard IRQs
164	16, // number of soft IRQs
165	16 ); // number of output IRQs
166
167	/////////////////////////////////////////////////////////////////////////////
168	size_t nb_initiators = nb_procs;
169	size_t nb_targets = 2;
170
171	if ((x_id == 0) and (y_id == 0)) // cluster(0,0)
172	{
173	nb_targets++; // TTY
174
175	if (not use_ramdisk)
176	{
177	nb_initiators++;
178	nb_targets++;
179	}
180	}
181
182	std::ostringstream s_xbar_cmd;
183	xbar_cmd = new VciLocalCrossbar<vci_param_int>(
184	s_xbar_cmd.str().c_str(),
185	mtd, // mapping table
186	cluster_xy, // cluster id
187	nb_initiators, // number of local initiators
188	nb_targets, // number of local targets
189	0 ); // default target
190
191	wi_gate = new VciDspinInitiatorWrapper<vci_param_int,
192	dspin_cmd_width,
193	dspin_rsp_width>(
194	"wi_gate",
195	x_width + y_width + l_width);
196
197	wt_gate = new VciDspinTargetWrapper<vci_param_int,
198	dspin_cmd_width,
199	dspin_rsp_width>(
200	"wt_gate",
201	x_width + y_width + l_width);
202
203	/////////////////////////////////////////////////////////////////////////////
204	std::ostringstream s_xbar_m2p;
205	s_xbar_m2p << "xbar_m2p_" << x_id << "_" << y_id;
206	xbar_m2p = new DspinLocalCrossbar<dspin_cmd_width>(
207	s_xbar_m2p.str().c_str(),
208	mtd, // mapping table
209	x_id, y_id, // cluster coordinates
210	x_width, y_width, l_width,
211	1, // number of local sources
212	nb_procs, // number of local dests
213	2, 2, // fifo depths
214	true, // CMD
215	false, // don't use local routing table
216	true ); // broadcast
217
218	/////////////////////////////////////////////////////////////////////////////
219	std::ostringstream s_xbar_p2m;
220	s_xbar_p2m << "xbar_p2m_" << x_id << "_" << y_id;
221	xbar_p2m = new DspinLocalCrossbar<dspin_rsp_width>(
222	s_xbar_p2m.str().c_str(),
223	mtd, // mapping table
224	x_id, y_id, // cluster coordinates
225	x_width, y_width, 0, // l_width unused on p2m network
226	nb_procs, // number of local sources
227	1, // number of local dests
228	2, 2, // fifo depths
229	false, // RSP
230	false, // don't use local routing table
231	false ); // no broadcast
232
233	/////////////////////////////////////////////////////////////////////////////
234	std::ostringstream s_xbar_cla;
235	s_xbar_cla << "xbar_cla_" << x_id << "_" << y_id;
236	xbar_cla = new DspinLocalCrossbar<dspin_cmd_width>(
237	s_xbar_cla.str().c_str(),
238	mtd, // mapping table
239	x_id, y_id, // cluster coordinates
240	x_width, y_width, l_width,
241	1, // number of local sources
242	nb_procs, // number of local dests
243	2, 2, // fifo depths
244	true, // CMD
245	false, // don't use local routing table
246	false); // no broadcast
247
248	/////////////////////////////////////////////////////////////////////////////
249	std::ostringstream s_router_cmd;
250	s_router_cmd << "router_cmd_" << x_id << "_" << y_id;
251	router_cmd = new DspinRouter<dspin_cmd_width>(
252	s_router_cmd.str().c_str(),
253	x_id,y_id, // coordinate in the mesh
254	x_width, y_width, // x & y fields width
255	4,4); // input & output fifo depths
256
257	/////////////////////////////////////////////////////////////////////////////
258	std::ostringstream s_router_rsp;
259	s_router_rsp << "router_rsp_" << x_id << "_" << y_id;
260	router_rsp = new DspinRouter<dspin_rsp_width>(
261	s_router_rsp.str().c_str(),
262	x_id,y_id, // coordinates in mesh
263	x_width, y_width, // x & y fields width
264	4,4); // input & output fifo depths
265
266	/////////////////////////////////////////////////////////////////////////////
267	std::ostringstream s_router_m2p;
268	s_router_m2p << "router_m2p_" << x_id << "_" << y_id;
269	router_m2p = new DspinRouter<dspin_cmd_width>(
270	s_router_m2p.str().c_str(),
271	x_id,y_id, // coordinate in the mesh
272	x_width, y_width, // x & y fields width
273	4,4, // input & output fifo depths
274	true); // broadcast supported
275
276	/////////////////////////////////////////////////////////////////////////////
277	std::ostringstream s_router_p2m;
278	s_router_p2m << "router_p2m_" << x_id << "_" << y_id;
279	router_p2m = new DspinRouter<dspin_rsp_width>(
280	s_router_p2m.str().c_str(),
281	x_id,y_id, // coordinates in mesh
282	x_width, y_width, // x & y fields width
283	4,4); // input & output fifo depths
284
285	/////////////////////////////////////////////////////////////////////////////
286	std::ostringstream s_router_cla;
287	s_router_cla << "router_cla_" << x_id << "_" << y_id;
288	router_cla = new DspinRouter<dspin_cmd_width>(
289	s_router_cla.str().c_str(),
290	x_id,y_id, // coordinate in the mesh
291	x_width, y_width, // x & y fields width
292	4,4); // input & output fifo depths
293
294	// backup BDV and TTY peripherals in cluster(0,0)
295	bdev = NULL;
296	mtty = NULL;
297	if ((x_id == 0) and (y_id == 0))
298	{
299	if (not use_ramdisk)
300	{
301	/////////////////////////////////////////////
302	bdev = new VciBlockDeviceTsar<vci_param_int>(
303	"bdev",
304	mtd,
305	IntTab(cluster_xy, nb_procs),
306	IntTab(cluster_xy, tgtid_bdev),
307	disk_pathname,
308	512,
309	64 ); // burst size
310	}
311
312	/////////////////////////////////////////////
313	mtty = new VciMultiTty<vci_param_int>(
314	"mtty",
315	IntTab(cluster_xy, tgtid_mtty),
316	mtd,
317	"tty_backup", NULL );
318	}
319
320	std::cout << std::endl;
321
322	////////////////////////////////////
323	// Connections are defined here
324	////////////////////////////////////
325
326	//////////////////////// ROUTERS
327	router_cmd->p_clk (this->p_clk);
328	router_cmd->p_resetn (this->p_resetn);
329	router_rsp->p_clk (this->p_clk);
330	router_rsp->p_resetn (this->p_resetn);
331	router_m2p->p_clk (this->p_clk);
332	router_m2p->p_resetn (this->p_resetn);
333	router_p2m->p_clk (this->p_clk);
334	router_p2m->p_resetn (this->p_resetn);
335	router_cla->p_clk (this->p_clk);
336	router_cla->p_resetn (this->p_resetn);
337
338	// loop on N/S/E/W ports
339	for (size_t i = 0; i < 4; i++)
340	{
341	router_cmd->p_out[i] (this->p_cmd_out[i]);
342	router_cmd->p_in[i] (this->p_cmd_in[i]);
343
344	router_rsp->p_out[i] (this->p_rsp_out[i]);
345	router_rsp->p_in[i] (this->p_rsp_in[i]);
346
347	router_m2p->p_out[i] (this->p_m2p_out[i]);
348	router_m2p->p_in[i] (this->p_m2p_in[i]);
349
350	router_p2m->p_out[i] (this->p_p2m_out[i]);
351	router_p2m->p_in[i] (this->p_p2m_in[i]);
352
353	router_cla->p_out[i] (this->p_cla_out[i]);
354	router_cla->p_in[i] (this->p_cla_in[i]);
355	}
356
357	router_cmd->p_out[4] (signal_dspin_cmd_g2l_d);
358	router_cmd->p_in[4] (signal_dspin_cmd_l2g_d);
359
360	router_rsp->p_out[4] (signal_dspin_rsp_g2l_d);
361	router_rsp->p_in[4] (signal_dspin_rsp_l2g_d);
362
363	router_m2p->p_out[4] (signal_dspin_m2p_g2l_c);
364	router_m2p->p_in[4] (signal_dspin_m2p_l2g_c);
365
366	router_p2m->p_out[4] (signal_dspin_p2m_g2l_c);
367	router_p2m->p_in[4] (signal_dspin_p2m_l2g_c);
368
369	router_cla->p_out[4] (signal_dspin_clack_g2l_c);
370	router_cla->p_in[4] (signal_dspin_clack_l2g_c);
371
372	std::cout << " - routers connected" << std::endl;
373
374	///////////////////// CMD DSPIN local crossbar direct
375	xbar_cmd->p_clk (this->p_clk);
376	xbar_cmd->p_resetn (this->p_resetn);
377	xbar_cmd->p_initiator_to_up (signal_vci_l2g);
378	xbar_cmd->p_target_to_up (signal_vci_g2l);
379
380	xbar_cmd->p_to_target[tgtid_memc] (signal_vci_tgt_memc);
381	xbar_cmd->p_to_target[tgtid_xicu] (signal_vci_tgt_xicu);
382
383	for (size_t p = 0; p < nb_procs; p++)
384	xbar_cmd->p_to_initiator[p] (signal_vci_ini_proc[p]);
385
386	if ((x_id == 0) and (y_id == 0)) // cluster(0,0)
387	{
388	xbar_cmd->p_to_target[tgtid_mtty] (signal_vci_tgt_mtty);
389
390	if (not use_ramdisk)
391	{
392	xbar_cmd->p_to_target[tgtid_bdev] (signal_vci_tgt_bdev);
393	xbar_cmd->p_to_initiator[nb_procs] (signal_vci_ini_bdev);
394	}
395	}
396
397	wi_gate->p_clk (this->p_clk);
398	wi_gate->p_resetn (this->p_resetn);
399	wi_gate->p_vci (signal_vci_l2g);
400	wi_gate->p_dspin_cmd (signal_dspin_cmd_l2g_d);
401	wi_gate->p_dspin_rsp (signal_dspin_rsp_g2l_d);
402
403	wt_gate->p_clk (this->p_clk);
404	wt_gate->p_resetn (this->p_resetn);
405	wt_gate->p_vci (signal_vci_g2l);
406	wt_gate->p_dspin_cmd (signal_dspin_cmd_g2l_d);
407	wt_gate->p_dspin_rsp (signal_dspin_rsp_l2g_d);
408
409	std::cout << " - CMD & RSP Direct crossbar connected" << std::endl;
410
411	////////////////////// M2P DSPIN local crossbar coherence
412	xbar_m2p->p_clk (this->p_clk);
413	xbar_m2p->p_resetn (this->p_resetn);
414	xbar_m2p->p_global_out (signal_dspin_m2p_l2g_c);
415	xbar_m2p->p_global_in (signal_dspin_m2p_g2l_c);
416	xbar_m2p->p_local_in[0] (signal_dspin_m2p_memc);
417	for (size_t p = 0; p < nb_procs; p++)
418	xbar_m2p->p_local_out[p] (signal_dspin_m2p_proc[p]);
419
420	std::cout << " - M2P Coherence crossbar connected" << std::endl;
421
422	////////////////////////// P2M DSPIN local crossbar coherence
423	xbar_p2m->p_clk (this->p_clk);
424	xbar_p2m->p_resetn (this->p_resetn);
425	xbar_p2m->p_global_out (signal_dspin_p2m_l2g_c);
426	xbar_p2m->p_global_in (signal_dspin_p2m_g2l_c);
427	xbar_p2m->p_local_out[0] (signal_dspin_p2m_memc);
428	for (size_t p = 0; p < nb_procs; p++)
429	xbar_p2m->p_local_in[p] (signal_dspin_p2m_proc[p]);
430
431	std::cout << " - P2M Coherence crossbar connected" << std::endl;
432
433	////////////////////// CLACK DSPIN local crossbar coherence
434	xbar_cla->p_clk (this->p_clk);
435	xbar_cla->p_resetn (this->p_resetn);
436	xbar_cla->p_global_out (signal_dspin_clack_l2g_c);
437	xbar_cla->p_global_in (signal_dspin_clack_g2l_c);
438	xbar_cla->p_local_in[0] (signal_dspin_clack_memc);
439	for (size_t p = 0; p < nb_procs; p++)
440	xbar_cla->p_local_out[p] (signal_dspin_clack_proc[p]);
441
442	std::cout << " - CLA Coherence crossbar connected" << std::endl;
443
444	//////////////////////////////////// Processors
445	for (size_t p = 0; p < nb_procs; p++)
446	{
447	proc[p]->p_clk (this->p_clk);
448	proc[p]->p_resetn (this->p_resetn);
449	proc[p]->p_vci (signal_vci_ini_proc[p]);
450	proc[p]->p_dspin_m2p (signal_dspin_m2p_proc[p]);
451	proc[p]->p_dspin_p2m (signal_dspin_p2m_proc[p]);
452	proc[p]->p_dspin_clack (signal_dspin_clack_proc[p]);
453
454	for ( size_t j = 0 ; j < 6 ; j++)
455	{
456	if ( j < 4 ) proc[p]->p_irq[j] (signal_proc_irq[4*p + j]);
457	else proc[p]->p_irq[j] (signal_false);
458	}
459	}
460
461	std::cout << " - Processors connected" << std::endl;
462
463	///////////////////////////////////// XICU
464	xicu->p_clk (this->p_clk);
465	xicu->p_resetn (this->p_resetn);
466	xicu->p_vci (signal_vci_tgt_xicu);
467
468	for (size_t i = 0 ; i < 16 ; i++)
469	{
470	xicu->p_irq[i] (signal_proc_irq[i]);
471	}
472
473	for (size_t i = 0; i < 16; i++)
474	{
475	if ((x_id == 0) and (y_id == 0)) // cluster (0,0)
476	{
477	if (i == 8) xicu->p_hwi[i] (signal_irq_memc);
478	else if (i == 9 and not use_ramdisk) xicu->p_hwi[i] (signal_irq_bdev);
479	else if (i == 10) xicu->p_hwi[i] (signal_irq_mtty);
480	else xicu->p_hwi[i] (signal_false);
481	}
482	else // other clusters
483	{
484	if (i == 8) xicu->p_hwi[i] (signal_irq_memc);
485	else xicu->p_hwi[i] (signal_false);
486	}
487	}
488
489	std::cout << " - XICU connected" << std::endl;
490
491	//////////////////////////////////////////////// MEMC
492	memc->p_clk (this->p_clk);
493	memc->p_resetn (this->p_resetn);
494	memc->p_irq (signal_irq_memc);
495	memc->p_vci_ixr (signal_vci_xram);
496	memc->p_vci_tgt (signal_vci_tgt_memc);
497	memc->p_dspin_p2m (signal_dspin_p2m_memc);
498	memc->p_dspin_m2p (signal_dspin_m2p_memc);
499	memc->p_dspin_clack (signal_dspin_clack_memc);
500
501	std::cout << " - MEMC connected" << std::endl;
502
503	/////////////////////////////////////////////// XRAM
504	xram->p_clk (this->p_clk);
505	xram->p_resetn (this->p_resetn);
506	xram->p_vci (signal_vci_xram);
507
508	std::cout << " - XRAM connected" << std::endl;
509
510	/////////////////////////////// Extra Components in cluster(0,0)
511
512	if ((x_id == 0) and (y_id == 0))
513	{
514	if (not use_ramdisk)
515	{
516	// BDEV
517	bdev->p_clk (this->p_clk);
518	bdev->p_resetn (this->p_resetn);
519	bdev->p_irq (signal_irq_bdev);
520	bdev->p_vci_target (signal_vci_tgt_bdev);
521	bdev->p_vci_initiator (signal_vci_ini_bdev);
522
523	std::cout << " - BDEV connected" << std::endl;
524	}
525
526	// MTTY (single channel)
527	mtty->p_clk (this->p_clk);
528	mtty->p_resetn (this->p_resetn);
529	mtty->p_vci (signal_vci_tgt_mtty);
530	mtty->p_irq[0] (signal_irq_mtty);
531
532	std::cout << " - MTTY connected" << std::endl;
533	}
534	} // end constructor
535
536
537
538	template<size_t dspin_cmd_width,
539	size_t dspin_rsp_width,
540	typename vci_param_int,
541	typename vci_param_ext> TsarLetiCluster<dspin_cmd_width,
542	dspin_rsp_width,
543	vci_param_int,
544	vci_param_ext>::~TsarLetiCluster() {
545
546	dealloc_elems<DspinInput<dspin_cmd_width> > (p_cmd_in, 4);
547	dealloc_elems<DspinOutput<dspin_cmd_width> >(p_cmd_out, 4);
548
549	dealloc_elems<DspinInput<dspin_rsp_width> > (p_rsp_in, 4);
550	dealloc_elems<DspinOutput<dspin_rsp_width> >(p_rsp_out, 4);
551
552	dealloc_elems<DspinInput<dspin_cmd_width> > (p_m2p_in, 4);
553	dealloc_elems<DspinOutput<dspin_cmd_width> >(p_m2p_out, 4);
554
555	dealloc_elems<DspinInput<dspin_rsp_width> > (p_p2m_in, 4);
556	dealloc_elems<DspinOutput<dspin_rsp_width> >(p_p2m_out, 4);
557
558	dealloc_elems<DspinInput<dspin_cmd_width> > (p_cla_in, 4);
559	dealloc_elems<DspinOutput<dspin_cmd_width> >(p_cla_out, 4);
560
561	for (size_t p = 0; p < m_nprocs ; p++)
562	{
563	if ( proc[p] ) delete proc[p];
564	}
565
566	delete memc;
567	delete xram;
568	delete xicu;
569	delete xbar_cmd;
570	delete xbar_m2p;
571	delete xbar_p2m;
572	delete xbar_cla;
573	delete router_cmd;
574	delete router_rsp;
575	delete router_m2p;
576	delete router_p2m;
577	delete router_cla;
578	delete wi_gate;
579	delete wt_gate;
580
581	if ( bdev )
582	{
583	delete bdev;
584	}
585
586	if ( mtty )
587	{
588	delete mtty;
589	}
590	}
591
592
593	}}
594
595	// Local Variables:
596	// tab-width: 4
597	// c-basic-offset: 4
598	// c-file-offsets:((innamespace . 0)(inline-open . 0))
599	// indent-tabs-mode: nil
600	// End:
601
602	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
603
604
605

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source: trunk/platforms/tsar_generic_leti/tsar_leti_cluster/caba/source/src/tsar_leti_cluster.cpp

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