Context Navigation

source: trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp @ 508

Last change on this file since 508 was 508, checked in by meunier, 11 years ago
Added a destructor in TsarXbarCluster? Corrected a bug in the MemCache? req_distance function Improved the function print_trace in MemCache?
File size: 37.3 KB

Rev	Line
[345]	1	//////////////////////////////////////////////////////////////////////////////
[378]	2	// File: tsar_xbar_cluster.cpp
[428]	3	// Author: Alain Greiner
[345]	4	// Copyright: UPMC/LIP6
	5	// Date : march 2011
	6	// This program is released under the GNU public license
	7	//////////////////////////////////////////////////////////////////////////////
	8	// This file define a TSAR cluster architecture with virtual memory:
[428]	9	// - It uses two virtual_dspin_router as distributed global interconnect
	10	// - It uses four dspin_local_crossbar as local interconnect
[345]	11	// - It uses the vci_cc_vcache_wrapper
	12	// - It uses the vci_mem_cache
	13	// - It contains a private RAM with a variable latency to emulate the L3 cache
	14	// - It can contains 1, 2 or 4 processors
	15	// - Each processor has a private dma channel (vci_multi_dma)
	16	// - It uses the vci_xicu interrupt controller
[396]	17	// - The peripherals MTTY, BDEV, FBUF, MNIC and BROM are in cluster (0,0)
[428]	18	// - The Multi-TTY component controls up to 15 terminals.
[345]	19	// - Each Multi-DMA component controls up to 8 DMA channels.
	20	// - The DMA IRQs are connected to IRQ_IN[8]...IRQ_IN[15]
	21	// - The TTY IRQs are connected to IRQ_IN[16]...IRQ_IN[30]
	22	// - The BDEV IRQ is connected to IRQ_IN[31]
[428]	23	//////////////////////////////////////////////////////////////////////////////////
[345]	24
[378]	25	#include "../include/tsar_xbar_cluster.h"
[345]	26
[389]	27
[345]	28	namespace soclib {
	29	namespace caba {
	30
[396]	31	////////////////////////////////////////////////////////////////////////////////////
[428]	32	template<size_t dspin_cmd_width,
[396]	33	size_t dspin_rsp_width,
	34	typename vci_param_int,
	35	typename vci_param_ext> TsarXbarCluster<dspin_cmd_width,
	36	dspin_rsp_width,
	37	vci_param_int,
	38	vci_param_ext>::TsarXbarCluster(
	39	////////////////////////////////////////////////////////////////////////////////////
[345]	40	sc_module_name insname,
	41	size_t nb_procs,
	42	size_t nb_ttys,
	43	size_t nb_dmas,
	44	size_t x_id,
	45	size_t y_id,
	46	size_t cluster_id,
	47	const soclib::common::MappingTable &mtd,
[428]	48	const soclib::common::MappingTable &mtx,
[345]	49	size_t x_width,
	50	size_t y_width,
	51	size_t l_width,
	52	size_t tgtid_memc,
	53	size_t tgtid_xicu,
	54	size_t tgtid_mdma,
	55	size_t tgtid_fbuf,
	56	size_t tgtid_mtty,
	57	size_t tgtid_brom,
	58	size_t tgtid_mnic,
[475]	59	size_t tgtid_chbuf,
[345]	60	size_t tgtid_bdev,
	61	size_t memc_ways,
	62	size_t memc_sets,
	63	size_t l1_i_ways,
	64	size_t l1_i_sets,
	65	size_t l1_d_ways,
	66	size_t l1_d_sets,
	67	size_t xram_latency,
	68	bool io,
	69	size_t xfb,
	70	size_t yfb,
	71	char* disk_name,
	72	size_t block_size,
	73	size_t nic_channels,
	74	char* nic_rx_name,
	75	char* nic_tx_name,
	76	uint32_t nic_timeout,
[485]	77	size_t chbufdma_channels,
[345]	78	const Loader &loader,
	79	uint32_t frozen_cycles,
	80	uint32_t debug_start_cycle,
	81	bool memc_debug_ok,
	82	bool proc_debug_ok)
	83	: soclib::caba::BaseModule(insname),
	84	p_clk("clk"),
	85	p_resetn("resetn")
	86
	87	{
[508]	88
	89	n_procs = nb_procs;
	90
[345]	91	// Vectors of ports definition
[508]	92	p_cmd_in = alloc_elems<DspinInput<dspin_cmd_width> > ("p_cmd_in", 4, 3);
	93	p_cmd_out = alloc_elems<DspinOutput<dspin_cmd_width> > ("p_cmd_out", 4, 3);
	94	p_rsp_in = alloc_elems<DspinInput<dspin_rsp_width> > ("p_rsp_in", 4, 2);
	95	p_rsp_out = alloc_elems<DspinOutput<dspin_rsp_width> > ("p_rsp_out", 4, 2);
[345]	96
[396]	97	/////////////////////////////////////////////////////////////////////////////
[428]	98	// Components definition
[345]	99	/////////////////////////////////////////////////////////////////////////////
	100
	101	for (size_t p = 0; p < nb_procs; p++)
[428]	102	{
[345]	103	std::ostringstream sproc;
[396]	104	sproc << "proc_" << x_id << "_" << y_id << "_" << p;
	105	proc[p] = new VciCcVCacheWrapper<vci_param_int,
	106	dspin_cmd_width,
[428]	107	dspin_rsp_width,
[396]	108	GdbServer<Mips32ElIss> >(
[345]	109	sproc.str().c_str(),
[508]	110	cluster_id * nb_procs + p, // GLOBAL PROC_ID
[428]	111	mtd, // Mapping Table
[345]	112	IntTab(cluster_id,p), // SRCID
	113	(cluster_id << l_width) + p, // CC_GLOBAL_ID
	114	8, // ITLB ways
	115	8, // ITLB sets
	116	8, // DTLB ways
	117	8, // DTLB sets
[508]	118	l1_i_ways,l1_i_sets, 16, // ICACHE size
	119	l1_d_ways,l1_d_sets, 16, // DCACHE size
[345]	120	4, // WBUF nlines
	121	4, // WBUF nwords
	122	x_width,
	123	y_width,
	124	frozen_cycles, // max frozen cycles
	125	debug_start_cycle,
	126	proc_debug_ok);
	127
	128	std::ostringstream swip;
[435]	129	swip << "wi_proc_" << x_id << "_" << y_id << "_" << p;
[396]	130	wi_proc[p] = new VciDspinInitiatorWrapper<vci_param_int,
	131	dspin_cmd_width,
	132	dspin_rsp_width>(
[351]	133	swip.str().c_str(),
[363]	134	x_width + y_width + l_width);
[345]	135	}
	136
	137	/////////////////////////////////////////////////////////////////////////////
[396]	138	std::ostringstream smemc;
	139	smemc << "memc_" << x_id << "_" << y_id;
	140	memc = new VciMemCache<vci_param_int,
	141	vci_param_ext,
	142	dspin_rsp_width,
	143	dspin_cmd_width>(
	144	smemc.str().c_str(),
[345]	145	mtd, // Mapping Table direct space
	146	mtx, // Mapping Table external space
	147	IntTab(cluster_id), // SRCID external space
	148	IntTab(cluster_id, tgtid_memc), // TGTID direct space
	149	(cluster_id << l_width) + nb_procs, // CC_GLOBAL_ID
[504]	150	x_width, // Number of x bits in platform
	151	y_width, // Number of y bits in platform
[345]	152	memc_ways, memc_sets, 16, // CACHE SIZE
	153	3, // MAX NUMBER OF COPIES
	154	4096, // HEAP SIZE
	155	8, // TRANSACTION TABLE DEPTH
	156	8, // UPDATE TABLE DEPTH
[468]	157	8, // INVALIDATE TABLE DEPTH
[345]	158	debug_start_cycle,
[508]	159	memc_debug_ok);
[345]	160
[396]	161	wt_memc = new VciDspinTargetWrapper<vci_param_int,
	162	dspin_cmd_width,
	163	dspin_rsp_width>(
[379]	164	"wt_memc",
[363]	165	x_width + y_width + l_width);
[345]	166
	167	/////////////////////////////////////////////////////////////////////////////
[396]	168	std::ostringstream sxram;
	169	sxram << "xram_" << x_id << "_" << y_id;
	170	xram = new VciSimpleRam<vci_param_ext>(
	171	sxram.str().c_str(),
[345]	172	IntTab(cluster_id),
	173	mtx,
	174	loader,
	175	xram_latency);
[379]	176
[345]	177	/////////////////////////////////////////////////////////////////////////////
[396]	178	std::ostringstream sxicu;
	179	sxicu << "xicu_" << x_id << "_" << y_id;
	180	xicu = new VciXicu<vci_param_int>(
	181	sxicu.str().c_str(),
[345]	182	mtd, // mapping table
	183	IntTab(cluster_id, tgtid_xicu), // TGTID_D
	184	nb_procs, // number of timer IRQs
	185	32, // number of hard IRQs
[389]	186	32, // number of soft IRQs
[345]	187	nb_procs); // number of output IRQs
	188
[396]	189	wt_xicu = new VciDspinTargetWrapper<vci_param_int,
	190	dspin_cmd_width,
	191	dspin_rsp_width>(
[379]	192	"wt_xicu",
[363]	193	x_width + y_width + l_width);
[345]	194
	195	/////////////////////////////////////////////////////////////////////////////
[396]	196	std::ostringstream smdma;
	197	smdma << "mdma_" << x_id << "_" << y_id;
	198	mdma = new VciMultiDma<vci_param_int>(
	199	smdma.str().c_str(),
[345]	200	mtd,
	201	IntTab(cluster_id, nb_procs), // SRCID
	202	IntTab(cluster_id, tgtid_mdma), // TGTID
	203	64, // burst size
[379]	204	nb_dmas); // number of IRQs
[345]	205
[396]	206	wt_mdma = new VciDspinTargetWrapper<vci_param_int,
	207	dspin_cmd_width,
	208	dspin_rsp_width>(
[379]	209	"wt_mdma",
[363]	210	x_width + y_width + l_width);
[345]	211
[396]	212	wi_mdma = new VciDspinInitiatorWrapper<vci_param_int,
	213	dspin_cmd_width,
	214	dspin_rsp_width>(
[379]	215	"wi_mdma",
[363]	216	x_width + y_width + l_width);
[345]	217
	218	/////////////////////////////////////////////////////////////////////////////
	219	size_t nb_direct_initiators = nb_procs + 1;
	220	size_t nb_direct_targets = 3;
[508]	221	if (io)
[345]	222	{
[475]	223	nb_direct_initiators = nb_procs + 3;
	224	nb_direct_targets = 9;
[345]	225	}
	226
[396]	227	xbar_cmd_d = new DspinLocalCrossbar<dspin_cmd_width>(
[379]	228	"xbar_cmd_d",
[345]	229	mtd, // mapping table
	230	x_id, y_id, // cluster coordinates
	231	x_width, y_width, l_width,
	232	nb_direct_initiators, // number of local of sources
[435]	233	nb_direct_targets, // number of local dests
	234	2, 2, // fifo depths
	235	true, // CMD
	236	true, // use local routing table
	237	false ); // no broadcast
[345]	238
	239	/////////////////////////////////////////////////////////////////////////////
[396]	240	xbar_rsp_d = new DspinLocalCrossbar<dspin_rsp_width>(
[379]	241	"xbar_rsp_d",
[345]	242	mtd, // mapping table
	243	x_id, y_id, // cluster coordinates
	244	x_width, y_width, l_width,
[428]	245	nb_direct_targets, // number of local sources
[345]	246	nb_direct_initiators, // number of local dests
[435]	247	2, 2, // fifo depths
	248	false, // RSP
	249	false, // don't use local routing table
	250	false ); // no broadcast
[345]	251
	252	/////////////////////////////////////////////////////////////////////////////
[396]	253	xbar_m2p_c = new DspinLocalCrossbar<dspin_cmd_width>(
[379]	254	"xbar_m2p_c",
[345]	255	mtd, // mapping table
	256	x_id, y_id, // cluster coordinates
	257	x_width, y_width, l_width,
	258	1, // number of local sources
[435]	259	nb_procs, // number of local targets
[428]	260	2, 2, // fifo depths
[435]	261	true, // CMD
[345]	262	false, // don't use local routing table
[435]	263	true ); // broadcast
[345]	264
	265	/////////////////////////////////////////////////////////////////////////////
[396]	266	xbar_p2m_c = new DspinLocalCrossbar<dspin_rsp_width>(
[379]	267	"xbar_p2m_c",
[345]	268	mtd, // mapping table
	269	x_id, y_id, // cluster coordinates
[379]	270	x_width, y_width, 0, // l_width unused on p2m network
[345]	271	nb_procs, // number of local sources
	272	1, // number of local dests
[428]	273	2, 2, // fifo depths
[435]	274	false, // RSP
[345]	275	false, // don't use local routing table
[435]	276	false ); // no broadcast
[345]	277
	278	/////////////////////////////////////////////////////////////////////////////
[468]	279	xbar_clack_c = new DspinLocalCrossbar<dspin_cmd_width>(
	280	"xbar_clack_c",
	281	mtd, // mapping table
	282	x_id, y_id, // cluster coordinates
	283	x_width, y_width, l_width,
	284	1, // number of local sources
	285	nb_procs, // number of local targets
	286	1, 1, // fifo depths
	287	true, // CMD
	288	false, // don't use local routing table
	289	false); // broadcast
	290
	291	/////////////////////////////////////////////////////////////////////////////
[396]	292	router_cmd = new VirtualDspinRouter<dspin_cmd_width>(
[379]	293	"router_cmd",
[345]	294	x_id,y_id, // coordinate in the mesh
	295	x_width, y_width, // x & y fields width
[468]	296	3, // nb virtual channels
[345]	297	4,4); // input & output fifo depths
	298
	299	/////////////////////////////////////////////////////////////////////////////
[396]	300	router_rsp = new VirtualDspinRouter<dspin_rsp_width>(
[379]	301	"router_rsp",
[345]	302	x_id,y_id, // coordinates in mesh
	303	x_width, y_width, // x & y fields width
[465]	304	2, // nb virtual channels
[345]	305	4,4); // input & output fifo depths
	306
	307	// IO cluster components
[508]	308	if (io)
[345]	309	{
	310	/////////////////////////////////////////////
[435]	311	brom = new VciSimpleRom<vci_param_int>(
[396]	312	"brom",
	313	IntTab(cluster_id, tgtid_brom),
	314	mtd,
	315	loader);
[345]	316
[396]	317	wt_brom = new VciDspinTargetWrapper<vci_param_int,
	318	dspin_cmd_width,
	319	dspin_rsp_width>(
	320	"wt_brom",
[363]	321	x_width + y_width + l_width);
[345]	322
	323	/////////////////////////////////////////////
[396]	324	fbuf = new VciFrameBuffer<vci_param_int>(
	325	"fbuf",
	326	IntTab(cluster_id, tgtid_fbuf),
	327	mtd,
[428]	328	xfb, yfb);
[345]	329
[396]	330	wt_fbuf = new VciDspinTargetWrapper<vci_param_int,
	331	dspin_cmd_width,
	332	dspin_rsp_width>(
	333	"wt_fbuf",
[363]	334	x_width + y_width + l_width);
[345]	335
	336	/////////////////////////////////////////////
[396]	337	bdev = new VciBlockDeviceTsar<vci_param_int>(
	338	"bdev",
	339	mtd,
[508]	340	IntTab(cluster_id, nb_procs + 1),
[396]	341	IntTab(cluster_id, tgtid_bdev),
	342	disk_name,
	343	block_size,
	344	64); // burst size
[345]	345
[396]	346	wt_bdev = new VciDspinTargetWrapper<vci_param_int,
	347	dspin_cmd_width,
	348	dspin_rsp_width>(
	349	"wt_bdev",
[363]	350	x_width + y_width + l_width);
[396]	351
	352	wi_bdev = new VciDspinInitiatorWrapper<vci_param_int,
	353	dspin_cmd_width,
	354	dspin_rsp_width>(
	355	"wi_bdev",
[363]	356	x_width + y_width + l_width);
[345]	357
	358	/////////////////////////////////////////////
[475]	359	int mac = 0xBEEF0000;
[396]	360	mnic = new VciMultiNic<vci_param_int>(
	361	"mnic",
	362	IntTab(cluster_id, tgtid_mnic),
	363	mtd,
	364	nic_channels,
	365	nic_rx_name,
	366	nic_tx_name,
[475]	367	mac, // mac_4 address
	368	0xBABE ); // mac_2 address
[345]	369
[396]	370	wt_mnic = new VciDspinTargetWrapper<vci_param_int,
	371	dspin_cmd_width,
	372	dspin_rsp_width>(
	373	"wt_mnic",
[363]	374	x_width + y_width + l_width);
[345]	375
	376	/////////////////////////////////////////////
[475]	377	chbuf = new VciChbufDma<vci_param_int>(
	378	"chbuf_dma",
	379	mtd,
	380	IntTab(cluster_id, nb_procs + 2),
	381	IntTab(cluster_id, tgtid_chbuf),
	382	64,
[485]	383	chbufdma_channels);
[475]	384
	385	wt_chbuf = new VciDspinTargetWrapper<vci_param_int,
	386	dspin_cmd_width,
	387	dspin_rsp_width>(
	388	"wt_chbuf",
	389	x_width + y_width + l_width);
	390
	391	wi_chbuf = new VciDspinInitiatorWrapper<vci_param_int,
	392	dspin_cmd_width,
	393	dspin_rsp_width>(
	394	"wi_chbuf",
	395	x_width + y_width + l_width);
	396
	397	/////////////////////////////////////////////
[345]	398	std::vector<std::string> vect_names;
[508]	399	for (size_t tid = 0; tid < nb_ttys; tid++)
[345]	400	{
	401	std::ostringstream term_name;
	402	term_name << "term" << tid;
	403	vect_names.push_back(term_name.str().c_str());
	404	}
[396]	405	mtty = new VciMultiTty<vci_param_int>(
	406	"mtty",
	407	IntTab(cluster_id, tgtid_mtty),
[428]	408	mtd,
[396]	409	vect_names);
[345]	410
[396]	411	wt_mtty = new VciDspinTargetWrapper<vci_param_int,
	412	dspin_cmd_width,
	413	dspin_rsp_width>(
	414	"wt_mtty",
[363]	415	x_width + y_width + l_width);
[345]	416	}
	417
	418	////////////////////////////////////
	419	// Connections are defined here
	420	////////////////////////////////////
	421
	422	//////////////////////// CMD ROUTER and RSP ROUTER
	423	router_cmd->p_clk (this->p_clk);
	424	router_cmd->p_resetn (this->p_resetn);
	425	router_rsp->p_clk (this->p_clk);
	426	router_rsp->p_resetn (this->p_resetn);
[465]	427
[508]	428	for (int i = 0; i < 4; i++)
[345]	429	{
[468]	430	for (int k = 0; k < 3; k++)
[345]	431	{
[465]	432	router_cmd->p_out[i][k] (this->p_cmd_out[i][k]);
	433	router_cmd->p_in[i][k] (this->p_cmd_in[i][k]);
[468]	434	}
	435
	436	for (int k = 0; k < 2; k++)
	437	{
[465]	438	router_rsp->p_out[i][k] (this->p_rsp_out[i][k]);
	439	router_rsp->p_in[i][k] (this->p_rsp_in[i][k]);
[345]	440	}
	441	}
	442
[465]	443	router_cmd->p_out[4][0] (signal_dspin_cmd_g2l_d);
	444	router_cmd->p_out[4][1] (signal_dspin_m2p_g2l_c);
[468]	445	router_cmd->p_out[4][2] (signal_dspin_clack_g2l_c);
[465]	446	router_cmd->p_in[4][0] (signal_dspin_cmd_l2g_d);
	447	router_cmd->p_in[4][1] (signal_dspin_m2p_l2g_c);
[468]	448	router_cmd->p_in[4][2] (signal_dspin_clack_l2g_c);
[345]	449
[465]	450	router_rsp->p_out[4][0] (signal_dspin_rsp_g2l_d);
	451	router_rsp->p_out[4][1] (signal_dspin_p2m_g2l_c);
	452	router_rsp->p_in[4][0] (signal_dspin_rsp_l2g_d);
	453	router_rsp->p_in[4][1] (signal_dspin_p2m_l2g_c);
[345]	454
[468]	455
[345]	456	std::cout << " - CMD & RSP routers connected" << std::endl;
	457
	458	///////////////////// CMD DSPIN local crossbar direct
	459	xbar_cmd_d->p_clk (this->p_clk);
	460	xbar_cmd_d->p_resetn (this->p_resetn);
	461	xbar_cmd_d->p_global_out (signal_dspin_cmd_l2g_d);
	462	xbar_cmd_d->p_global_in (signal_dspin_cmd_g2l_d);
	463
	464	xbar_cmd_d->p_local_out[tgtid_memc] (signal_dspin_cmd_memc_t);
	465	xbar_cmd_d->p_local_out[tgtid_xicu] (signal_dspin_cmd_xicu_t);
	466	xbar_cmd_d->p_local_out[tgtid_mdma] (signal_dspin_cmd_mdma_t);
	467
	468	xbar_cmd_d->p_local_in[nb_procs] (signal_dspin_cmd_mdma_i);
	469
	470	for (size_t p = 0; p < nb_procs; p++)
	471	xbar_cmd_d->p_local_in[p] (signal_dspin_cmd_proc_i[p]);
	472
[508]	473	if (io)
[345]	474	{
	475	xbar_cmd_d->p_local_out[tgtid_mtty] (signal_dspin_cmd_mtty_t);
	476	xbar_cmd_d->p_local_out[tgtid_brom] (signal_dspin_cmd_brom_t);
	477	xbar_cmd_d->p_local_out[tgtid_bdev] (signal_dspin_cmd_bdev_t);
	478	xbar_cmd_d->p_local_out[tgtid_fbuf] (signal_dspin_cmd_fbuf_t);
	479	xbar_cmd_d->p_local_out[tgtid_mnic] (signal_dspin_cmd_mnic_t);
[508]	480	xbar_cmd_d->p_local_out[tgtid_chbuf] (signal_dspin_cmd_chbuf_t);
[345]	481
[508]	482	xbar_cmd_d->p_local_in[nb_procs + 1] (signal_dspin_cmd_bdev_i);
	483	xbar_cmd_d->p_local_in[nb_procs + 2] (signal_dspin_cmd_chbuf_i);
[345]	484	}
	485
	486	std::cout << " - Command Direct crossbar connected" << std::endl;
	487
	488	//////////////////////// RSP DSPIN local crossbar direct
	489	xbar_rsp_d->p_clk (this->p_clk);
	490	xbar_rsp_d->p_resetn (this->p_resetn);
	491	xbar_rsp_d->p_global_out (signal_dspin_rsp_l2g_d);
	492	xbar_rsp_d->p_global_in (signal_dspin_rsp_g2l_d);
	493
	494	xbar_rsp_d->p_local_in[tgtid_memc] (signal_dspin_rsp_memc_t);
	495	xbar_rsp_d->p_local_in[tgtid_xicu] (signal_dspin_rsp_xicu_t);
	496	xbar_rsp_d->p_local_in[tgtid_mdma] (signal_dspin_rsp_mdma_t);
	497
	498	xbar_rsp_d->p_local_out[nb_procs] (signal_dspin_rsp_mdma_i);
	499
	500	for (size_t p = 0; p < nb_procs; p++)
	501	xbar_rsp_d->p_local_out[p] (signal_dspin_rsp_proc_i[p]);
	502
[508]	503	if (io)
[345]	504	{
	505	xbar_rsp_d->p_local_in[tgtid_mtty] (signal_dspin_rsp_mtty_t);
	506	xbar_rsp_d->p_local_in[tgtid_brom] (signal_dspin_rsp_brom_t);
	507	xbar_rsp_d->p_local_in[tgtid_bdev] (signal_dspin_rsp_bdev_t);
	508	xbar_rsp_d->p_local_in[tgtid_fbuf] (signal_dspin_rsp_fbuf_t);
	509	xbar_rsp_d->p_local_in[tgtid_mnic] (signal_dspin_rsp_mnic_t);
[508]	510	xbar_rsp_d->p_local_in[tgtid_chbuf] (signal_dspin_rsp_chbuf_t);
[345]	511
[508]	512	xbar_rsp_d->p_local_out[nb_procs + 1] (signal_dspin_rsp_bdev_i);
	513	xbar_rsp_d->p_local_out[nb_procs + 2] (signal_dspin_rsp_chbuf_i);
[345]	514	}
	515
	516	std::cout << " - Response Direct crossbar connected" << std::endl;
	517
	518	////////////////////// M2P DSPIN local crossbar coherence
	519	xbar_m2p_c->p_clk (this->p_clk);
	520	xbar_m2p_c->p_resetn (this->p_resetn);
	521	xbar_m2p_c->p_global_out (signal_dspin_m2p_l2g_c);
	522	xbar_m2p_c->p_global_in (signal_dspin_m2p_g2l_c);
[360]	523	xbar_m2p_c->p_local_in[0] (signal_dspin_m2p_memc);
[428]	524	for (size_t p = 0; p < nb_procs; p++)
[345]	525	xbar_m2p_c->p_local_out[p] (signal_dspin_m2p_proc[p]);
	526
	527	std::cout << " - M2P Coherence crossbar connected" << std::endl;
	528
[468]	529	////////////////////// CLACK DSPIN local crossbar coherence
	530	xbar_clack_c->p_clk (this->p_clk);
	531	xbar_clack_c->p_resetn (this->p_resetn);
	532	xbar_clack_c->p_global_out (signal_dspin_clack_l2g_c);
	533	xbar_clack_c->p_global_in (signal_dspin_clack_g2l_c);
	534	xbar_clack_c->p_local_in[0] (signal_dspin_clack_memc);
	535	for (size_t p = 0; p < nb_procs; p++)
[508]	536	xbar_clack_c->p_local_out[p] (signal_dspin_clack_proc[p]);
[468]	537
	538	std::cout << " - Clack Coherence crossbar connected" << std::endl;
	539
[345]	540	////////////////////////// P2M DSPIN local crossbar coherence
	541	xbar_p2m_c->p_clk (this->p_clk);
	542	xbar_p2m_c->p_resetn (this->p_resetn);
	543	xbar_p2m_c->p_global_out (signal_dspin_p2m_l2g_c);
	544	xbar_p2m_c->p_global_in (signal_dspin_p2m_g2l_c);
[360]	545	xbar_p2m_c->p_local_out[0] (signal_dspin_p2m_memc);
[428]	546	for (size_t p = 0; p < nb_procs; p++)
[345]	547	xbar_p2m_c->p_local_in[p] (signal_dspin_p2m_proc[p]);
	548
	549	std::cout << " - P2M Coherence crossbar connected" << std::endl;
	550
	551
	552	//////////////////////////////////// Processors
	553	for (size_t p = 0; p < nb_procs; p++)
	554	{
	555	proc[p]->p_clk (this->p_clk);
	556	proc[p]->p_resetn (this->p_resetn);
	557	proc[p]->p_vci (signal_vci_ini_proc[p]);
[468]	558	proc[p]->p_dspin_m2p (signal_dspin_m2p_proc[p]);
	559	proc[p]->p_dspin_p2m (signal_dspin_p2m_proc[p]);
	560	proc[p]->p_dspin_clack (signal_dspin_clack_proc[p]);
[345]	561	proc[p]->p_irq[0] (signal_proc_it[p]);
	562	for ( size_t j = 1 ; j < 6 ; j++)
	563	{
	564	proc[p]->p_irq[j] (signal_false);
	565	}
	566
	567	wi_proc[p]->p_clk (this->p_clk);
	568	wi_proc[p]->p_resetn (this->p_resetn);
	569	wi_proc[p]->p_dspin_cmd (signal_dspin_cmd_proc_i[p]);
	570	wi_proc[p]->p_dspin_rsp (signal_dspin_rsp_proc_i[p]);
	571	wi_proc[p]->p_vci (signal_vci_ini_proc[p]);
	572	}
	573
	574	std::cout << " - Processors connected" << std::endl;
	575
	576	///////////////////////////////////// XICU
[428]	577	xicu->p_clk (this->p_clk);
	578	xicu->p_resetn (this->p_resetn);
	579	xicu->p_vci (signal_vci_tgt_xicu);
[508]	580	for (size_t p = 0; p < nb_procs; p++)
[345]	581	{
[428]	582	xicu->p_irq[p] (signal_proc_it[p]);
[345]	583	}
[508]	584	for (size_t i = 0; i < 32; i++)
[345]	585	{
[508]	586	if (io) // I/O cluster
[345]	587	{
	588	if (i < 8) xicu->p_hwi[i] (signal_false);
[508]	589	else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i - 8]);
[345]	590	else if (i < 16) xicu->p_hwi[i] (signal_false);
[508]	591	else if (i < (16 + nb_ttys)) xicu->p_hwi[i] (signal_irq_mtty[i - 16]);
[428]	592	else if (i < 31) xicu->p_hwi[i] (signal_false);
[345]	593	else xicu->p_hwi[i] (signal_irq_bdev);
	594	}
	595	else // other clusters
	596	{
	597	if (i < 8) xicu->p_hwi[i] (signal_false);
[508]	598	else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i - 8]);
[428]	599	else xicu->p_hwi[i] (signal_false);
[345]	600	}
	601	}
	602
	603	// wrapper XICU
[360]	604	wt_xicu->p_clk (this->p_clk);
	605	wt_xicu->p_resetn (this->p_resetn);
	606	wt_xicu->p_dspin_cmd (signal_dspin_cmd_xicu_t);
	607	wt_xicu->p_dspin_rsp (signal_dspin_rsp_xicu_t);
	608	wt_xicu->p_vci (signal_vci_tgt_xicu);
[345]	609
	610	std::cout << " - XICU connected" << std::endl;
	611
	612	//////////////////////////////////////////////// MEMC
[428]	613	memc->p_clk (this->p_clk);
	614	memc->p_resetn (this->p_resetn);
	615	memc->p_vci_ixr (signal_vci_xram);
	616	memc->p_vci_tgt (signal_vci_tgt_memc);
[468]	617	memc->p_dspin_p2m (signal_dspin_p2m_memc);
	618	memc->p_dspin_m2p (signal_dspin_m2p_memc);
	619	memc->p_dspin_clack (signal_dspin_clack_memc);
[345]	620
	621	// wrapper MEMC
[360]	622	wt_memc->p_clk (this->p_clk);
	623	wt_memc->p_resetn (this->p_resetn);
	624	wt_memc->p_dspin_cmd (signal_dspin_cmd_memc_t);
	625	wt_memc->p_dspin_rsp (signal_dspin_rsp_memc_t);
	626	wt_memc->p_vci (signal_vci_tgt_memc);
[345]	627
	628	std::cout << " - MEMC connected" << std::endl;
	629
	630	/////////////////////////////////////////////// XRAM
[428]	631	xram->p_clk (this->p_clk);
	632	xram->p_resetn (this->p_resetn);
	633	xram->p_vci (signal_vci_xram);
[345]	634
	635	std::cout << " - XRAM connected" << std::endl;
	636
[360]	637	////////////////////////////////////////////// MDMA
[428]	638	mdma->p_clk (this->p_clk);
	639	mdma->p_resetn (this->p_resetn);
	640	mdma->p_vci_target (signal_vci_tgt_mdma);
	641	mdma->p_vci_initiator (signal_vci_ini_mdma);
[508]	642	for (size_t i = 0; i < nb_dmas; i++)
[345]	643	mdma->p_irq[i] (signal_irq_mdma[i]);
	644
[360]	645	// wrapper tgt MDMA
	646	wt_mdma->p_clk (this->p_clk);
	647	wt_mdma->p_resetn (this->p_resetn);
	648	wt_mdma->p_dspin_cmd (signal_dspin_cmd_mdma_t);
	649	wt_mdma->p_dspin_rsp (signal_dspin_rsp_mdma_t);
	650	wt_mdma->p_vci (signal_vci_tgt_mdma);
	651
	652	// wrapper ini MDMA
	653	wi_mdma->p_clk (this->p_clk);
	654	wi_mdma->p_resetn (this->p_resetn);
	655	wi_mdma->p_dspin_cmd (signal_dspin_cmd_mdma_i);
	656	wi_mdma->p_dspin_rsp (signal_dspin_rsp_mdma_i);
	657	wi_mdma->p_vci (signal_vci_ini_mdma);
	658
[345]	659	std::cout << " - MDMA connected" << std::endl;
	660
[428]	661	/////////////////////////////// Components in I/O cluster
[345]	662
[508]	663	if (io)
[428]	664	{
	665	// BDEV
	666	bdev->p_clk (this->p_clk);
[345]	667	bdev->p_resetn (this->p_resetn);
	668	bdev->p_irq (signal_irq_bdev);
	669	bdev->p_vci_target (signal_vci_tgt_bdev);
	670	bdev->p_vci_initiator (signal_vci_ini_bdev);
	671
[360]	672	// wrapper tgt BDEV
	673	wt_bdev->p_clk (this->p_clk);
	674	wt_bdev->p_resetn (this->p_resetn);
	675	wt_bdev->p_dspin_cmd (signal_dspin_cmd_bdev_t);
	676	wt_bdev->p_dspin_rsp (signal_dspin_rsp_bdev_t);
	677	wt_bdev->p_vci (signal_vci_tgt_bdev);
	678
	679	// wrapper ini BDEV
	680	wi_bdev->p_clk (this->p_clk);
	681	wi_bdev->p_resetn (this->p_resetn);
	682	wi_bdev->p_dspin_cmd (signal_dspin_cmd_bdev_i);
	683	wi_bdev->p_dspin_rsp (signal_dspin_rsp_bdev_i);
	684	wi_bdev->p_vci (signal_vci_ini_bdev);
	685
[345]	686	std::cout << " - BDEV connected" << std::endl;
	687
	688	// FBUF
	689	fbuf->p_clk (this->p_clk);
	690	fbuf->p_resetn (this->p_resetn);
	691	fbuf->p_vci (signal_vci_tgt_fbuf);
	692
[360]	693	// wrapper tgt FBUF
	694	wt_fbuf->p_clk (this->p_clk);
	695	wt_fbuf->p_resetn (this->p_resetn);
	696	wt_fbuf->p_dspin_cmd (signal_dspin_cmd_fbuf_t);
	697	wt_fbuf->p_dspin_rsp (signal_dspin_rsp_fbuf_t);
	698	wt_fbuf->p_vci (signal_vci_tgt_fbuf);
	699
[345]	700	std::cout << " - FBUF connected" << std::endl;
	701
	702	// MNIC
	703	mnic->p_clk (this->p_clk);
	704	mnic->p_resetn (this->p_resetn);
	705	mnic->p_vci (signal_vci_tgt_mnic);
[508]	706	for (size_t i = 0; i < nic_channels; i++)
[345]	707	{
	708	mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]);
	709	mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]);
	710	}
	711
[360]	712	// wrapper tgt MNIC
	713	wt_mnic->p_clk (this->p_clk);
	714	wt_mnic->p_resetn (this->p_resetn);
	715	wt_mnic->p_dspin_cmd (signal_dspin_cmd_mnic_t);
	716	wt_mnic->p_dspin_rsp (signal_dspin_rsp_mnic_t);
	717	wt_mnic->p_vci (signal_vci_tgt_mnic);
	718
[345]	719	std::cout << " - MNIC connected" << std::endl;
	720
[475]	721	// CHBUF
	722	chbuf->p_clk (this->p_clk);
	723	chbuf->p_resetn (this->p_resetn);
	724	chbuf->p_vci_target (signal_vci_tgt_chbuf);
	725	chbuf->p_vci_initiator (signal_vci_ini_chbuf);
[508]	726	for (size_t i = 0; i < chbufdma_channels; i++)
[475]	727	{
	728	chbuf->p_irq[i] (signal_irq_chbuf[i]);
	729	}
	730
	731	// wrapper tgt CHBUF
	732	wt_chbuf->p_clk (this->p_clk);
	733	wt_chbuf->p_resetn (this->p_resetn);
	734	wt_chbuf->p_dspin_cmd (signal_dspin_cmd_chbuf_t);
	735	wt_chbuf->p_dspin_rsp (signal_dspin_rsp_chbuf_t);
	736	wt_chbuf->p_vci (signal_vci_tgt_chbuf);
	737
	738	// wrapper ini CHBUF
	739	wi_chbuf->p_clk (this->p_clk);
	740	wi_chbuf->p_resetn (this->p_resetn);
	741	wi_chbuf->p_dspin_cmd (signal_dspin_cmd_chbuf_i);
	742	wi_chbuf->p_dspin_rsp (signal_dspin_rsp_chbuf_i);
	743	wi_chbuf->p_vci (signal_vci_ini_chbuf);
	744
	745	std::cout << " - CHBUF connected" << std::endl;
	746
[345]	747	// BROM
	748	brom->p_clk (this->p_clk);
	749	brom->p_resetn (this->p_resetn);
	750	brom->p_vci (signal_vci_tgt_brom);
	751
[360]	752	// wrapper tgt BROM
	753	wt_brom->p_clk (this->p_clk);
	754	wt_brom->p_resetn (this->p_resetn);
	755	wt_brom->p_dspin_cmd (signal_dspin_cmd_brom_t);
	756	wt_brom->p_dspin_rsp (signal_dspin_rsp_brom_t);
	757	wt_brom->p_vci (signal_vci_tgt_brom);
	758
[345]	759	std::cout << " - BROM connected" << std::endl;
	760
	761	// MTTY
	762	mtty->p_clk (this->p_clk);
	763	mtty->p_resetn (this->p_resetn);
	764	mtty->p_vci (signal_vci_tgt_mtty);
[508]	765	for (size_t i = 0; i < nb_ttys; i++)
[345]	766	{
[428]	767	mtty->p_irq[i] (signal_irq_mtty[i]);
[345]	768	}
	769
[360]	770	// wrapper tgt MTTY
	771	wt_mtty->p_clk (this->p_clk);
	772	wt_mtty->p_resetn (this->p_resetn);
	773	wt_mtty->p_dspin_cmd (signal_dspin_cmd_mtty_t);
	774	wt_mtty->p_dspin_rsp (signal_dspin_rsp_mtty_t);
	775	wt_mtty->p_vci (signal_vci_tgt_mtty);
	776
[345]	777	std::cout << " - MTTY connected" << std::endl;
	778	}
	779	} // end constructor
	780
[508]	781
	782
	783	template<size_t dspin_cmd_width,
	784	size_t dspin_rsp_width,
	785	typename vci_param_int,
	786	typename vci_param_ext> TsarXbarCluster<dspin_cmd_width,
	787	dspin_rsp_width,
	788	vci_param_int,
	789	vci_param_ext>::~TsarXbarCluster() {
	790
	791	for (size_t p = 0; p < n_procs; p++)
	792	{
	793	delete proc[p];
	794	delete wi_proc[p];
	795	}
	796
	797	delete memc;
	798	delete wt_memc;
	799	delete xram;
	800	delete xicu;
	801	delete wt_xicu;
	802	delete mdma;
	803	delete wt_mdma;
	804	delete wi_mdma;
	805	delete xbar_cmd_d;
	806	delete xbar_rsp_d;
	807	delete xbar_m2p_c;
	808	delete xbar_p2m_c;
	809	delete xbar_clack_c;
	810	delete router_cmd;
	811	delete router_rsp;
	812	if (brom != NULL)
	813	{
	814	delete brom;
	815	delete wt_brom;
	816	delete fbuf;
	817	delete wt_fbuf;
	818	delete bdev;
	819	delete wt_bdev;
	820	delete wi_bdev;
	821	delete mnic;
	822	delete wt_mnic;
	823	delete chbuf;
	824	delete wt_chbuf;
	825	delete wi_chbuf;
	826	delete mtty;
	827	delete wt_mtty;
	828	}
	829	}
	830
	831
[396]	832	}}
[345]	833
	834	// Local Variables:
[508]	835	// tab-width: 4
	836	// c-basic-offset: 4
[345]	837	// c-file-offsets:((innamespace . 0)(inline-open . 0))
	838	// indent-tabs-mode: nil
	839	// End:
	840
[508]	841	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
[345]	842
	843
	844

Note: See TracBrowser for help on using the repository browser.

Download in other formats:

Project-Id-Version: Trac 0.12
Report-Msgid-Bugs-To: trac-dev@googlegroups.com
POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
Last-Translator: Jeroen Ruigrok van der Werven <asmodai@in-nomine.org>
Language: en_US
Language-Team: en_US <trac-dev@googlegroups.com>
Plural-Forms: nplurals=2; plural=(n != 1)
MIME-Version: 1.0
Content-Type: text/plain; charset=utf-8
Content-Transfer-Encoding: 8bit
Generated-By: Babel 2.8.0