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tsar_xbar_cluster.cpp @ 1048

Last change on this file since 1048 was 1048, checked in by meunier, 7 years ago
Update of tsar_xbar_cluster (scripts and openmp support)
File size: 33.7 KB

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1	//////////////////////////////////////////////////////////////////////////////
2	// File: tsar_xbar_cluster.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : march 2011
6	// This program is released under the GNU public license
7	//////////////////////////////////////////////////////////////////////////////
8	// This file define a TSAR cluster architecture with virtual memory:
9	// - It uses two virtual_dspin_router as distributed global interconnect
10	// - It uses four dspin_local_crossbar as local interconnect
11	// - It uses the vci_cc_vcache_wrapper
12	// - It uses the vci_mem_cache
13	// - It contains a private RAM with a variable latency to emulate the L3 cache
14	// - It can contains 1, 2 or 4 processors
15	// - Each processor has a private dma channel (vci_multi_dma)
16	// - It uses the vci_xicu interrupt controller
17	// - The peripherals MTTY, BDEV, FBUF, MNIC and BROM are in cluster (0,0)
18	// - The Multi-TTY component controls up to 15 terminals.
19	// - Each Multi-DMA component controls up to 8 DMA channels.
20	// - The DMA IRQs are connected to IRQ_IN[8]...IRQ_IN[15]
21	// - The TTY IRQs are connected to IRQ_IN[16]...IRQ_IN[30]
22	// - The BDEV IRQ is connected to IRQ_IN[31]
23	//////////////////////////////////////////////////////////////////////////////////
24
25	#include "../include/tsar_xbar_cluster.h"
26
27
28	namespace soclib {
29	namespace caba {
30
31	////////////////////////////////////////////////////////////////////////////////////
32	template<size_t dspin_cmd_width,
33	size_t dspin_rsp_width,
34	typename vci_param_int,
35	typename vci_param_ext> TsarXbarCluster<dspin_cmd_width,
36	dspin_rsp_width,
37	vci_param_int,
38	vci_param_ext>::TsarXbarCluster(
39	////////////////////////////////////////////////////////////////////////////////////
40	sc_module_name insname,
41	size_t nb_procs,
42	size_t nb_ttys,
43	size_t nb_dmas,
44	size_t x_id,
45	size_t y_id,
46	size_t cluster_id,
47	const soclib::common::MappingTable &mtd,
48	const soclib::common::MappingTable &mtx,
49	size_t x_width,
50	size_t y_width,
51	size_t l_width,
52	size_t p_width,
53	size_t tgtid_memc,
54	size_t tgtid_xicu,
55	size_t tgtid_mdma,
56	size_t tgtid_fbuf,
57	size_t tgtid_mtty,
58	size_t tgtid_brom,
59	size_t tgtid_mnic,
60	size_t tgtid_chbuf,
61	size_t tgtid_bdev,
62	size_t tgtid_simh,
63	size_t memc_ways,
64	size_t memc_sets,
65	size_t l1_i_ways,
66	size_t l1_i_sets,
67	size_t l1_d_ways,
68	size_t l1_d_sets,
69	size_t irq_per_processor,
70	size_t xram_latency,
71	bool io,
72	size_t xfb,
73	size_t yfb,
74	char* disk_name,
75	size_t block_size,
76	size_t nic_channels,
77	char* nic_rx_name,
78	char* nic_tx_name,
79	uint32_t nic_timeout,
80	size_t chbufdma_channels,
81	const Loader & loader,
82	uint32_t frozen_cycles,
83	uint32_t debug_start_cycle,
84	bool memc_debug_ok,
85	bool proc_debug_ok)
86	: soclib::caba::BaseModule(insname),
87	p_clk("clk"),
88	p_resetn("resetn") {
89
90	n_procs = nb_procs;
91
92	/////////////////////////////////////////////////////////////////////////////
93	// Vectors of ports definition and allocation
94	/////////////////////////////////////////////////////////////////////////////
95
96	p_cmd_in = alloc_elems<DspinInput<dspin_cmd_width> > ("p_cmd_in", 4);
97	p_cmd_out = alloc_elems<DspinOutput<dspin_cmd_width> > ("p_cmd_out", 4);
98
99	p_rsp_in = alloc_elems<DspinInput<dspin_rsp_width> > ("p_rsp_in", 4);
100	p_rsp_out = alloc_elems<DspinOutput<dspin_rsp_width> > ("p_rsp_out", 4);
101
102	p_m2p_in = alloc_elems<DspinInput<dspin_cmd_width> > ("p_m2p_in", 4);
103	p_m2p_out = alloc_elems<DspinOutput<dspin_cmd_width> > ("p_m2p_out", 4);
104
105	p_p2m_in = alloc_elems<DspinInput<dspin_rsp_width> > ("p_p2m_in", 4);
106	p_p2m_out = alloc_elems<DspinOutput<dspin_rsp_width> > ("p_p2m_out", 4);
107
108	p_cla_in = alloc_elems<DspinInput<dspin_cmd_width> > ("p_cla_in", 4);
109	p_cla_out = alloc_elems<DspinOutput<dspin_cmd_width> > ("p_cla_out", 4);
110
111	/////////////////////////////////////////////////////////////////////////////
112	// Components definition
113	/////////////////////////////////////////////////////////////////////////////
114
115	for (size_t p = 0; p < nb_procs; p++) {
116	std::ostringstream sproc;
117	sproc << "proc_" << x_id << "_" << y_id << "_" << p;
118	proc[p] = new VciCcVCacheWrapper<vci_param_int,
119	dspin_cmd_width,
120	dspin_rsp_width,
121	GdbServer<Mips32ElIss> >(
122	sproc.str().c_str(),
123	(cluster_id << p_width) + p, // GLOBAL PROC_ID
124	mtd, // Mapping Table
125	IntTab(cluster_id, p), // SRCID
126	(cluster_id << l_width) + p, // CC_GLOBAL_ID
127	8, // ITLB ways
128	8, // ITLB sets
129	8, // DTLB ways
130	8, // DTLB sets
131	l1_i_ways,l1_i_sets, 16, // ICACHE size
132	l1_d_ways,l1_d_sets, 16, // DCACHE size
133	4, // WBUF nlines
134	4, // WBUF nwords
135	x_width,
136	y_width,
137	frozen_cycles, // max frozen cycles
138	debug_start_cycle,
139	proc_debug_ok);
140
141	}
142
143	/////////////////////////////////////////////////////////////////////////////
144	std::ostringstream smemc;
145	smemc << "memc_" << x_id << "_" << y_id;
146	memc = new VciMemCache<vci_param_int,
147	vci_param_ext,
148	dspin_rsp_width,
149	dspin_cmd_width>(
150	smemc.str().c_str(),
151	mtd, // Mapping Table direct space
152	mtx, // Mapping Table external space
153	IntTab(cluster_id), // SRCID external space
154	IntTab(cluster_id, tgtid_memc), // TGTID direct space
155	x_width, // Number of x bits in platform
156	y_width, // Number of y bits in platform
157	memc_ways, memc_sets, 16, // CACHE SIZE
158	4, // MAX NUMBER OF COPIES
159	4096, // HEAP SIZE
160	8, // TRANSACTION TABLE DEPTH
161	8, // UPDATE TABLE DEPTH
162	8, // INVALIDATE TABLE DEPTH
163	debug_start_cycle,
164	memc_debug_ok);
165
166
167	/////////////////////////////////////////////////////////////////////////////
168	std::ostringstream sxram;
169	sxram << "xram_" << x_id << "_" << y_id;
170	xram = new VciSimpleRam<vci_param_ext>(
171	sxram.str().c_str(),
172	IntTab(cluster_id),
173	mtx,
174	loader,
175	xram_latency);
176
177	/////////////////////////////////////////////////////////////////////////////
178	std::ostringstream sxicu;
179	sxicu << "xicu_" << x_id << "_" << y_id;
180	xicu = new VciXicu<vci_param_int>(
181	sxicu.str().c_str(),
182	mtd, // mapping table
183	IntTab(cluster_id, tgtid_xicu), // TGTID_D
184	nb_procs, // number of timer IRQs
185	32, // number of hard IRQs
186	32, // number of soft IRQs
187	nb_procs * irq_per_processor); // number of output IRQs
188
189
190	/////////////////////////////////////////////////////////////////////////////
191	std::ostringstream smdma;
192	smdma << "mdma_" << x_id << "_" << y_id;
193	mdma = new VciMultiDma<vci_param_int>(
194	smdma.str().c_str(),
195	mtd,
196	IntTab(cluster_id, nb_procs), // SRCID
197	IntTab(cluster_id, tgtid_mdma), // TGTID
198	64, // burst size
199	nb_dmas); // number of IRQs
200
201
202	/////////////////////////////////////////////////////////////////////////////
203	size_t nb_direct_initiators = nb_procs + 1;
204	size_t nb_direct_targets = 3;
205	if (io) {
206	nb_direct_initiators = nb_procs + 3;
207	nb_direct_targets = 10;
208	}
209
210	std::ostringstream sxbar;
211	sxbar << "xbar_" << x_id << "_" << y_id;
212	xbar_d = new VciLocalCrossbar<vci_param_int>(
213	sxbar.str().c_str(),
214	mtd, // mapping table
215	//x_id, y_id, // cluster coordinates
216	cluster_id,
217	nb_direct_initiators, // number of local of sources
218	nb_direct_targets, // number of local dests
219	tgtid_memc); // Default target
220
221	////////////// vci_dspin wrappers
222	std::ostringstream swtxbar;
223	swtxbar << "wt_xbar_" << x_id << "_" << y_id;
224	wt_xbar_d = new VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>(
225	swtxbar.str().c_str(),
226	x_width + y_width + l_width);
227
228	std::ostringstream swixbar;
229	swixbar << "wi_xbar_" << x_id << "_" << y_id;
230	wi_xbar_d = new VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>(
231	swixbar.str().c_str(),
232	x_width + y_width + l_width );
233
234	/////////////////////////////////////////////////////////////////////////////
235	xbar_m2p_c = new DspinLocalCrossbar<dspin_cmd_width>(
236	"xbar_m2p_c",
237	mtd, // mapping table
238	x_id, y_id, // cluster coordinates
239	x_width, y_width, l_width,
240	1, // number of local sources
241	nb_procs, // number of local targets
242	2, 2, // fifo depths
243	true, // CMD
244	false, // don't use local routing table
245	true ); // broadcast
246
247	/////////////////////////////////////////////////////////////////////////////
248	xbar_p2m_c = new DspinLocalCrossbar<dspin_rsp_width>(
249	"xbar_p2m_c",
250	mtd, // mapping table
251	x_id, y_id, // cluster coordinates
252	x_width, y_width, 0, // l_width unused on p2m network
253	nb_procs, // number of local sources
254	1, // number of local dests
255	2, 2, // fifo depths
256	false, // RSP
257	false, // don't use local routing table
258	false ); // no broadcast
259
260	/////////////////////////////////////////////////////////////////////////////
261	xbar_clack_c = new DspinLocalCrossbar<dspin_cmd_width>(
262	"xbar_clack_c",
263	mtd, // mapping table
264	x_id, y_id, // cluster coordinates
265	x_width, y_width, l_width,
266	1, // number of local sources
267	nb_procs, // number of local targets
268	1, 1, // fifo depths
269	true, // CMD
270	false, // don't use local routing table
271	false); // broadcast
272
273	/////////////////////////////////////////////////////////////////////////////
274	std::ostringstream s_router_cmd;
275	s_router_cmd << "router_cmd_" << x_id << "_" << y_id;
276	router_cmd = new DspinRouter<dspin_cmd_width>(
277	s_router_cmd.str().c_str(),
278	x_id,y_id, // coordinate in the mesh
279	x_width, y_width, // x & y fields width
280	4,4); // input & output fifo depths
281
282	/////////////////////////////////////////////////////////////////////////////
283	std::ostringstream s_router_rsp;
284	s_router_rsp << "router_rsp_" << x_id << "_" << y_id;
285	router_rsp = new DspinRouter<dspin_rsp_width>(
286	s_router_rsp.str().c_str(),
287	x_id,y_id, // coordinates in mesh
288	x_width, y_width, // x & y fields width
289	4,4); // input & output fifo depths
290
291	/////////////////////////////////////////////////////////////////////////////
292	std::ostringstream s_router_m2p;
293	s_router_m2p << "router_m2p_" << x_id << "_" << y_id;
294	router_m2p = new DspinRouter<dspin_cmd_width>(
295	s_router_m2p.str().c_str(),
296	x_id,y_id, // coordinate in the mesh
297	x_width, y_width, // x & y fields width
298	4,4, // input & output fifo depths
299	true); // broadcast supported
300
301	/////////////////////////////////////////////////////////////////////////////
302	std::ostringstream s_router_p2m;
303	s_router_p2m << "router_p2m_" << x_id << "_" << y_id;
304	router_p2m = new DspinRouter<dspin_rsp_width>(
305	s_router_p2m.str().c_str(),
306	x_id,y_id, // coordinates in mesh
307	x_width, y_width, // x & y fields width
308	4,4); // input & output fifo depths
309
310	/////////////////////////////////////////////////////////////////////////////
311	std::ostringstream s_router_cla;
312	s_router_cla << "router_cla_" << x_id << "_" << y_id;
313	router_cla = new DspinRouter<dspin_cmd_width>(
314	s_router_cla.str().c_str(),
315	x_id,y_id, // coordinate in the mesh
316	x_width, y_width, // x & y fields width
317	4,4); // input & output fifo depths
318
319	// IO cluster components
320	if (io) {
321	/////////////////////////////////////////////
322	brom = new VciSimpleRom<vci_param_int>(
323	"brom",
324	IntTab(cluster_id, tgtid_brom),
325	mtd,
326	loader);
327
328	/////////////////////////////////////////////
329	fbuf = new VciFrameBuffer<vci_param_int>(
330	"fbuf",
331	IntTab(cluster_id, tgtid_fbuf),
332	mtd,
333	xfb, yfb);
334
335	/////////////////////////////////////////////
336	bdev = new VciBlockDeviceTsar<vci_param_int>(
337	"bdev",
338	mtd,
339	IntTab(cluster_id, nb_procs + 1),
340	IntTab(cluster_id, tgtid_bdev),
341	disk_name,
342	block_size,
343	64); // burst size
344
345	mnic = new VciMultiNic<vci_param_int>(
346	"mnic",
347	IntTab(cluster_id, tgtid_mnic),
348	mtd,
349	nic_channels,
350	0, // mac_4 address
351	0, // mac_2 address
352	1, // NIC_MODE_SYNTHESIS
353	12); // INTER_FRAME_GAP
354
355
356
357	/////////////////////////////////////////////
358	chbuf = new VciChbufDma<vci_param_int>(
359	"chbuf_dma",
360	mtd,
361	IntTab(cluster_id, nb_procs + 2),
362	IntTab(cluster_id, tgtid_chbuf),
363	64,
364	chbufdma_channels);
365
366	/////////////////////////////////////////////
367	std::vector<std::string> vect_names;
368	for (size_t tid = 0; tid < nb_ttys; tid++) {
369	std::ostringstream term_name;
370	term_name << "term" << tid;
371	vect_names.push_back(term_name.str().c_str());
372	}
373	mtty = new VciMultiTty<vci_param_int>(
374	"mtty",
375	IntTab(cluster_id, tgtid_mtty),
376	mtd,
377	vect_names);
378
379	simhelper = new VciSimhelper<vci_param_int>(
380	"sim_helper",
381	IntTab(cluster_id, tgtid_simh),
382	mtd);
383	}
384
385	////////////////////////////////////
386	// Connections are defined here
387	////////////////////////////////////
388
389	//////////////////////// ROUTERS
390	router_cmd->p_clk (this->p_clk);
391	router_cmd->p_resetn (this->p_resetn);
392	router_rsp->p_clk (this->p_clk);
393	router_rsp->p_resetn (this->p_resetn);
394	router_m2p->p_clk (this->p_clk);
395	router_m2p->p_resetn (this->p_resetn);
396	router_p2m->p_clk (this->p_clk);
397	router_p2m->p_resetn (this->p_resetn);
398	router_cla->p_clk (this->p_clk);
399	router_cla->p_resetn (this->p_resetn);
400
401	// loop on N/S/E/W ports
402	for (size_t i = 0; i < 4; i++) {
403	router_cmd->p_out[i] (this->p_cmd_out[i]);
404	router_cmd->p_in[i] (this->p_cmd_in[i]);
405
406	router_rsp->p_out[i] (this->p_rsp_out[i]);
407	router_rsp->p_in[i] (this->p_rsp_in[i]);
408
409	router_m2p->p_out[i] (this->p_m2p_out[i]);
410	router_m2p->p_in[i] (this->p_m2p_in[i]);
411
412	router_p2m->p_out[i] (this->p_p2m_out[i]);
413	router_p2m->p_in[i] (this->p_p2m_in[i]);
414
415	router_cla->p_out[i] (this->p_cla_out[i]);
416	router_cla->p_in[i] (this->p_cla_in[i]);
417	}
418
419	router_cmd->p_out[4] (signal_dspin_cmd_g2l_d);
420	router_cmd->p_in[4] (signal_dspin_cmd_l2g_d);
421
422	router_rsp->p_out[4] (signal_dspin_rsp_g2l_d);
423	router_rsp->p_in[4] (signal_dspin_rsp_l2g_d);
424
425	router_m2p->p_out[4] (signal_dspin_m2p_g2l_c);
426	router_m2p->p_in[4] (signal_dspin_m2p_l2g_c);
427
428	router_p2m->p_out[4] (signal_dspin_p2m_g2l_c);
429	router_p2m->p_in[4] (signal_dspin_p2m_l2g_c);
430
431	router_cla->p_out[4] (signal_dspin_clack_g2l_c);
432	router_cla->p_in[4] (signal_dspin_clack_l2g_c);
433
434	std::cout << " - routers connected" << std::endl;
435
436	wi_xbar_d->p_clk (this->p_clk);
437	wi_xbar_d->p_resetn (this->p_resetn);
438	wi_xbar_d->p_vci (signal_vci_l2g_d);
439	wi_xbar_d->p_dspin_cmd (signal_dspin_cmd_l2g_d);
440	wi_xbar_d->p_dspin_rsp (signal_dspin_rsp_g2l_d);
441
442	std::cout << " - Wrapper Ini VCI2DSPIN Direct connected" << std::endl;
443
444	wt_xbar_d->p_clk (this->p_clk);
445	wt_xbar_d->p_resetn (this->p_resetn);
446	wt_xbar_d->p_vci (signal_vci_g2l_d);
447	wt_xbar_d->p_dspin_cmd (signal_dspin_cmd_g2l_d);
448	wt_xbar_d->p_dspin_rsp (signal_dspin_rsp_l2g_d);
449
450	std::cout << " - Wrapper Tgt VCI2DSPIN Direct connected" << std::endl;
451
452	///////////////////// CMD VCI local crossbar direct
453	xbar_d->p_clk (this->p_clk);
454	xbar_d->p_resetn (this->p_resetn);
455	xbar_d->p_target_to_up (signal_vci_g2l_d);
456	xbar_d->p_initiator_to_up (signal_vci_l2g_d);
457
458	xbar_d->p_to_target[tgtid_memc] (signal_vci_tgt_memc);
459	xbar_d->p_to_target[tgtid_xicu] (signal_vci_tgt_xicu);
460	xbar_d->p_to_target[tgtid_mdma] (signal_vci_tgt_mdma);
461
462	xbar_d->p_to_initiator[nb_procs] (signal_vci_ini_mdma);
463
464	for (size_t p = 0; p < nb_procs; p++) {
465	xbar_d->p_to_initiator[p] (signal_vci_ini_proc[p]);
466	}
467
468	if (io) {
469	xbar_d->p_to_target[tgtid_mtty] (signal_vci_tgt_mtty);
470	xbar_d->p_to_target[tgtid_brom] (signal_vci_tgt_brom);
471	xbar_d->p_to_target[tgtid_bdev] (signal_vci_tgt_bdev);
472	xbar_d->p_to_target[tgtid_fbuf] (signal_vci_tgt_fbuf);
473	xbar_d->p_to_target[tgtid_mnic] (signal_vci_tgt_mnic);
474	xbar_d->p_to_target[tgtid_chbuf] (signal_vci_tgt_chbuf);
475	xbar_d->p_to_target[tgtid_simh] (signal_vci_tgt_simh);
476
477	xbar_d->p_to_initiator[nb_procs + 1] (signal_vci_ini_bdev);
478	xbar_d->p_to_initiator[nb_procs + 2] (signal_vci_ini_chbuf);
479	}
480
481	std::cout << " - Direct crossbar connected" << std::endl;
482
483	////////////////////// M2P DSPIN local crossbar coherence
484	xbar_m2p_c->p_clk (this->p_clk);
485	xbar_m2p_c->p_resetn (this->p_resetn);
486	xbar_m2p_c->p_global_out (signal_dspin_m2p_l2g_c);
487	xbar_m2p_c->p_global_in (signal_dspin_m2p_g2l_c);
488	xbar_m2p_c->p_local_in[0] (signal_dspin_m2p_memc);
489	for (size_t p = 0; p < nb_procs; p++) {
490	xbar_m2p_c->p_local_out[p] (signal_dspin_m2p_proc[p]);
491	}
492
493	std::cout << " - M2P Coherence crossbar connected" << std::endl;
494
495	////////////////////// CLACK DSPIN local crossbar coherence
496	xbar_clack_c->p_clk (this->p_clk);
497	xbar_clack_c->p_resetn (this->p_resetn);
498	xbar_clack_c->p_global_out (signal_dspin_clack_l2g_c);
499	xbar_clack_c->p_global_in (signal_dspin_clack_g2l_c);
500	xbar_clack_c->p_local_in[0] (signal_dspin_clack_memc);
501	for (size_t p = 0; p < nb_procs; p++) {
502	xbar_clack_c->p_local_out[p] (signal_dspin_clack_proc[p]);
503	}
504
505	std::cout << " - Clack Coherence crossbar connected" << std::endl;
506
507	////////////////////////// P2M DSPIN local crossbar coherence
508	xbar_p2m_c->p_clk (this->p_clk);
509	xbar_p2m_c->p_resetn (this->p_resetn);
510	xbar_p2m_c->p_global_out (signal_dspin_p2m_l2g_c);
511	xbar_p2m_c->p_global_in (signal_dspin_p2m_g2l_c);
512	xbar_p2m_c->p_local_out[0] (signal_dspin_p2m_memc);
513	for (size_t p = 0; p < nb_procs; p++) {
514	xbar_p2m_c->p_local_in[p] (signal_dspin_p2m_proc[p]);
515	}
516
517	std::cout << " - P2M Coherence crossbar connected" << std::endl;
518
519
520	//////////////////////////////////// Processors
521	for (size_t p = 0; p < nb_procs; p++) {
522	proc[p]->p_clk (this->p_clk);
523	proc[p]->p_resetn (this->p_resetn);
524	proc[p]->p_vci (signal_vci_ini_proc[p]);
525	proc[p]->p_dspin_m2p (signal_dspin_m2p_proc[p]);
526	proc[p]->p_dspin_p2m (signal_dspin_p2m_proc[p]);
527	proc[p]->p_dspin_clack (signal_dspin_clack_proc[p]);
528
529	for ( size_t i = 0; i < irq_per_processor; i++) {
530	proc[p]->p_irq[i] (signal_proc_it[p*irq_per_processor + i]);
531	}
532	for ( size_t j = irq_per_processor; j < 6; j++) {
533	// 6 = number of irqs in the MIPS
534	proc[p]->p_irq[j] (signal_false);
535	}
536
537	}
538
539	std::cout << " - Processors connected" << std::endl;
540
541	///////////////////////////////////// XICU
542	xicu->p_clk (this->p_clk);
543	xicu->p_resetn (this->p_resetn);
544	xicu->p_vci (signal_vci_tgt_xicu);
545	for (size_t p = 0; p < nb_procs * irq_per_processor; p++) {
546	xicu->p_irq[p] (signal_proc_it[p]);
547	}
548	for (size_t i = 0; i < 32; i++) {
549	if (io) {
550	// I/O cluster
551	if (i < 8) xicu->p_hwi[i] (signal_false);
552	else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i - 8]);
553	else if (i < 16) xicu->p_hwi[i] (signal_false);
554	else if (i < (16 + nb_ttys)) xicu->p_hwi[i] (signal_irq_mtty[i - 16]);
555	else if (i < 30) xicu->p_hwi[i] (signal_false);
556	else if (i < 31) xicu->p_hwi[i] (signal_irq_memc);
557	else xicu->p_hwi[i] (signal_irq_bdev);
558	}
559	else {
560	// other clusters
561	if (i < 8) xicu->p_hwi[i] (signal_false);
562	else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i - 8]);
563	else if (i < 30) xicu->p_hwi[i] (signal_false);
564	else if (i < 31) xicu->p_hwi[i] (signal_irq_memc);
565	else xicu->p_hwi[i] (signal_false);
566	}
567	}
568
569	std::cout << " - XICU connected" << std::endl;
570
571	//////////////////////////////////////////////// MEMC
572	memc->p_clk (this->p_clk);
573	memc->p_resetn (this->p_resetn);
574	memc->p_irq (signal_irq_memc);
575	memc->p_vci_ixr (signal_vci_xram);
576	memc->p_vci_tgt (signal_vci_tgt_memc);
577	memc->p_dspin_p2m (signal_dspin_p2m_memc);
578	memc->p_dspin_m2p (signal_dspin_m2p_memc);
579	memc->p_dspin_clack (signal_dspin_clack_memc);
580
581	std::cout << " - MEMC connected" << std::endl;
582
583	/////////////////////////////////////////////// XRAM
584	xram->p_clk (this->p_clk);
585	xram->p_resetn (this->p_resetn);
586	xram->p_vci (signal_vci_xram);
587
588	std::cout << " - XRAM connected" << std::endl;
589
590	////////////////////////////////////////////// MDMA
591	mdma->p_clk (this->p_clk);
592	mdma->p_resetn (this->p_resetn);
593	mdma->p_vci_target (signal_vci_tgt_mdma);
594	mdma->p_vci_initiator (signal_vci_ini_mdma);
595	for (size_t i = 0; i < nb_dmas; i++) {
596	mdma->p_irq[i] (signal_irq_mdma[i]);
597	}
598
599	std::cout << " - MDMA connected" << std::endl;
600
601	/////////////////////////////// Components in I/O cluster
602
603	if (io) {
604	// BDEV
605	bdev->p_clk (this->p_clk);
606	bdev->p_resetn (this->p_resetn);
607	bdev->p_irq (signal_irq_bdev);
608	bdev->p_vci_target (signal_vci_tgt_bdev);
609	bdev->p_vci_initiator (signal_vci_ini_bdev);
610
611	std::cout << " - BDEV connected" << std::endl;
612
613	// FBUF
614	fbuf->p_clk (this->p_clk);
615	fbuf->p_resetn (this->p_resetn);
616	fbuf->p_vci (signal_vci_tgt_fbuf);
617
618	std::cout << " - FBUF connected" << std::endl;
619
620	// MNIC
621	mnic->p_clk (this->p_clk);
622	mnic->p_resetn (this->p_resetn);
623	mnic->p_vci (signal_vci_tgt_mnic);
624	for (size_t i = 0; i < nic_channels; i++) {
625	mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]);
626	mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]);
627	}
628
629	std::cout << " - MNIC connected" << std::endl;
630
631	// CHBUF
632	chbuf->p_clk (this->p_clk);
633	chbuf->p_resetn (this->p_resetn);
634	chbuf->p_vci_target (signal_vci_tgt_chbuf);
635	chbuf->p_vci_initiator (signal_vci_ini_chbuf);
636	for (size_t i = 0; i < chbufdma_channels; i++) {
637	chbuf->p_irq[i] (signal_irq_chbuf[i]);
638	}
639
640	std::cout << " - CHBUF connected" << std::endl;
641
642	// BROM
643	brom->p_clk (this->p_clk);
644	brom->p_resetn (this->p_resetn);
645	brom->p_vci (signal_vci_tgt_brom);
646
647	std::cout << " - BROM connected" << std::endl;
648
649	// MTTY
650	mtty->p_clk (this->p_clk);
651	mtty->p_resetn (this->p_resetn);
652	mtty->p_vci (signal_vci_tgt_mtty);
653	for (size_t i = 0; i < nb_ttys; i++) {
654	mtty->p_irq[i] (signal_irq_mtty[i]);
655	}
656
657	std::cout << " - MTTY connected" << std::endl;
658
659
660	// Sim Helper
661	simhelper->p_clk (this->p_clk);
662	simhelper->p_resetn (this->p_resetn);
663	simhelper->p_vci (signal_vci_tgt_simh);
664
665	std::cout << " - SIMH connected" << std::endl;
666	}
667	} // end constructor
668
669
670
671	template<size_t dspin_cmd_width,
672	size_t dspin_rsp_width,
673	typename vci_param_int,
674	typename vci_param_ext> TsarXbarCluster<dspin_cmd_width,
675	dspin_rsp_width,
676	vci_param_int,
677	vci_param_ext>::~TsarXbarCluster() {
678
679	dealloc_elems<DspinInput<dspin_cmd_width> > (p_cmd_in, 4);
680	dealloc_elems<DspinOutput<dspin_cmd_width> >(p_cmd_out, 4);
681
682	dealloc_elems<DspinInput<dspin_rsp_width> > (p_rsp_in, 4);
683	dealloc_elems<DspinOutput<dspin_rsp_width> >(p_rsp_out, 4);
684
685	dealloc_elems<DspinInput<dspin_cmd_width> > (p_m2p_in, 4);
686	dealloc_elems<DspinOutput<dspin_cmd_width> >(p_m2p_out, 4);
687
688	dealloc_elems<DspinInput<dspin_rsp_width> > (p_p2m_in, 4);
689	dealloc_elems<DspinOutput<dspin_rsp_width> >(p_p2m_out, 4);
690
691	dealloc_elems<DspinInput<dspin_cmd_width> > (p_cla_in, 4);
692	dealloc_elems<DspinOutput<dspin_cmd_width> >(p_cla_out, 4);
693
694	for (size_t p = 0; p < n_procs; p++) {
695	delete proc[p];
696	}
697
698	delete memc;
699	delete xram;
700	delete xicu;
701	delete mdma;
702	delete xbar_d;
703	delete wt_xbar_d;
704	delete wi_xbar_d;
705	delete xbar_m2p_c;
706	delete xbar_p2m_c;
707	delete xbar_clack_c;
708	delete router_cmd;
709	delete router_rsp;
710	delete router_m2p;
711	delete router_p2m;
712	delete router_cla;
713	if (brom != NULL) {
714	delete brom;
715	delete fbuf;
716	delete bdev;
717	delete mnic;
718	delete chbuf;
719	delete mtty;
720	delete simhelper;
721	}
722	}
723
724
725	template<size_t dspin_cmd_width,
726	size_t dspin_rsp_width,
727	typename vci_param_int,
728	typename vci_param_ext>
729	void TsarXbarCluster<dspin_cmd_width,
730	dspin_rsp_width,
731	vci_param_int,
732	vci_param_ext>::trace(sc_core::sc_trace_file * tf, const std::string & name) {
733
734	#define __trace(x) sc_core::sc_trace(tf, x, name + "_" + #x)
735	__trace(signal_vci_l2g_d);
736	__trace(signal_vci_g2l_d);
737	__trace(signal_vci_tgt_memc);
738	__trace(signal_vci_tgt_xicu);
739	__trace(signal_vci_tgt_mdma);
740	__trace(signal_vci_ini_mdma);
741
742	for (size_t p = 0; p < n_procs; p++) {
743	std::ostringstream signame;
744	signame << "vci_ini_proc_" << p;
745	sc_core::sc_trace(tf, signal_vci_ini_proc[p], signame.str());
746	}
747	__trace(signal_vci_tgt_mtty);
748	__trace(signal_vci_tgt_brom);
749	__trace(signal_vci_tgt_bdev);
750	__trace(signal_vci_tgt_fbuf);
751	__trace(signal_vci_tgt_simh);
752	__trace(signal_vci_ini_bdev);
753	__trace(signal_vci_tgt_memc);
754	__trace(signal_vci_xram);
755	#undef trace
756
757	}
758
759	}}
760
761	// Local Variables:
762	// tab-width: 4
763	// c-basic-offset: 4
764	// c-file-offsets:((innamespace . 0)(inline-open . 0))
765	// indent-tabs-mode: nil
766	// End:
767
768	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
769

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source: trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp @ 1048

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