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tsar_xbar_cluster.cpp @ 468

Last change on this file since 468 was 468, checked in by cfuguet, 11 years ago

Merging vci_mem_cache from branches/v5 to trunk [441-467]

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r441 | cfuguet | 2013-07-17 10:54:07 +0200 (Wed, 17 Jul 2013) | 14 lines

Modifications in branches/v5/vci_mem_cache:

Changing name of CC DSPIN ports: + p_dspin_in => p_dspin_p2m + p_dspin_out => p_dspin_m2p

Splitting the Update Table in two tables: + UPT (Update Table): Stores the MULTI-UPDATE transactions + IVT (Invalidate Table): Stores the MULTI/BROADCAST INVALIDATE

transactions

Each table has its own allocator FSM: r_alloc_upt and r_alloc_ivt

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r442 | cfuguet | 2013-07-17 12:13:51 +0200 (Wed, 17 Jul 2013) | 13 lines

Modifications in branches/v5/modules/vci_mem_cache:

Introducing third port for the CLACK network.
CLEANUP FSM is no more a CC_SEND FSM client.
CLEANUP FSM controls directly the p_dspin_clack port

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r445 | cfuguet | 2013-07-18 10:49:36 +0200 (Thu, 18 Jul 2013) | 7 lines

Bugfix in vci_mem_cache:

Adding missing "strings" for print_trace() function
Adding alloc_ivt fsm (Invalidate Table) in the

print_trace() function

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r455 | cfuguet | 2013-07-19 10:16:17 +0200 (Fri, 19 Jul 2013) | 8 lines

Merged

/trunk/modules/vci_mem_cache:449 with
/branches/v5/modules/vci_mem_cache:446.

This merge introduces into the branch the last modifications concerning
the VCI memory cache configuration interface

Merging vci_cc_vcache_wrapper from branches/v5 to trunk [444-467]

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r444 | cfuguet | 2013-07-17 14:46:46 +0200 (Wed, 17 Jul 2013) | 7 lines

Modifications in branches/v5/modules/vci_cc_vcache_wrapper:

Renaming FROM_MC DSPIN flits fields in M2P
Renaming FROM_L1 DSPIN flits fields in P2M
Renaming CLEANUP_ACK DSPIN flits fields in CLACK

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r446 | cfuguet | 2013-07-18 11:37:47 +0200 (Thu, 18 Jul 2013) | 13 lines

Modifications in vci_cc_vcache_wrapper:

Merging the states DCACHE/ICACHE_CC_BROADCAST and DCACHE/ICACHE_CC_INVAL. This is because, the BROADCAST INVALIDATE and the MULTICAST INVALIDATE are both acknowledged by a CLEANUP.

Adding third port for the clack coherence network.

Renaming the port dspin_in to dspin_m2p and the port dspin_out to dspin_p2m

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r454 | haoliu | 2013-07-19 10:15:13 +0200 (Fri, 19 Jul 2013) | 2 lines

modified CC_RECEIVE FSM and CC_CHECK FSM (icache and dcache) for new
version V5

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r461 | cfuguet | 2013-07-19 15:49:43 +0200 (Fri, 19 Jul 2013) | 9 lines

Bugfix in vci_cc_vcache_wrapper:

In the states DCACHE/ICACHE CC_UPDT the FSM returns to the state CC_CHECK only when the cc_send_req is occupied.

We must not return to the CC_CHECK state if not ROK of the
DATA FIFO because the counter word counter will be reset.

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r462 | cfuguet | 2013-07-19 16:26:26 +0200 (Fri, 19 Jul 2013) | 8 lines

Modification in vci_cc_vcache_wrapper:

Optimization in DCACHE/ICACHE CC_CHECK state. We can handle a CLACK and a CC request if the latter does a MISS match. This is because the CC request doing MISS match does not need to access the directory

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r463 | cfuguet | 2013-07-19 16:52:06 +0200 (Fri, 19 Jul 2013) | 12 lines

Modification in vci_cc_vcache_wrapper:

Optimization in DCACHE/ICACHE CC_CHECK state. If pending request to CC_SEND, we wait in the CC_CHECK state. Doing this, during the wait, we can handle incoming CLACK avoiding any deadlock situation.

The states CC_UPDT and CC_INVAL do not need to test anymore if
there is a pending request to CC_SEND.

Merging tsar_generic_xbar from branches/v5 to trunk [447-467]

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r447 | cfuguet | 2013-07-18 16:12:05 +0200 (Thu, 18 Jul 2013) | 8 lines

Adding tsar_generic_xbar platform in branches/v5/platforms:

This platform contains a third local crossbar interconnect for the CLACK network.

It works only in a monocluster topology

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r448 | cfuguet | 2013-07-18 17:51:18 +0200 (Thu, 18 Jul 2013) | 9 lines

Modification in branches/v5/platforms/tsar_generic_xbar:

Adding a DSPIN router to the platform to allow the inter-cluster communication for the CLACK commands.

With this modification, the tsar_generic_xbar platform can be used
for multi-cluster simulations

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r466 | cfuguet | 2013-07-23 17:01:49 +0200 (Tue, 23 Jul 2013) | 9 lines

Modifications in branches/v5 vci_mem_cache:

Replacing the third router CLACK by a third virtual channel in the new virtual_dspin_router supporting several virtual channels.

The third channel has been added in the COMMAND router.

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r467 | cfuguet | 2013-07-23 17:23:13 +0200 (Tue, 23 Jul 2013) | 5 lines

Modifications in branches/v5 tsar_generic_xbar:

Adding preprocessor conditional statements for ALMOS support

Merging dspin_dhccp_param from branches/v5 to trunk [377-467]

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r442 | cfuguet | 2013-07-17 12:13:51 +0200 (Wed, 17 Jul 2013) | 13 lines

Modifications in branches/v5/communication/dspin_dhccp_param:

Renaming FROM_MC fields in M2P
Renaming FROM_L1 fields in P2M
Renaming CLEANUP_ACK fields in CLACK

File size: 33.6 KB

Line
1	//////////////////////////////////////////////////////////////////////////////
2	// File: tsar_xbar_cluster.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : march 2011
6	// This program is released under the GNU public license
7	//////////////////////////////////////////////////////////////////////////////
8	// This file define a TSAR cluster architecture with virtual memory:
9	// - It uses two virtual_dspin_router as distributed global interconnect
10	// - It uses four dspin_local_crossbar as local interconnect
11	// - It uses the vci_cc_vcache_wrapper
12	// - It uses the vci_mem_cache
13	// - It contains a private RAM with a variable latency to emulate the L3 cache
14	// - It can contains 1, 2 or 4 processors
15	// - Each processor has a private dma channel (vci_multi_dma)
16	// - It uses the vci_xicu interrupt controller
17	// - The peripherals MTTY, BDEV, FBUF, MNIC and BROM are in cluster (0,0)
18	// - The Multi-TTY component controls up to 15 terminals.
19	// - Each Multi-DMA component controls up to 8 DMA channels.
20	// - The DMA IRQs are connected to IRQ_IN[8]...IRQ_IN[15]
21	// - The TTY IRQs are connected to IRQ_IN[16]...IRQ_IN[30]
22	// - The BDEV IRQ is connected to IRQ_IN[31]
23	//////////////////////////////////////////////////////////////////////////////////
24
25	#include "../include/tsar_xbar_cluster.h"
26
27
28	namespace soclib {
29	namespace caba {
30
31	////////////////////////////////////////////////////////////////////////////////////
32	template<size_t dspin_cmd_width,
33	size_t dspin_rsp_width,
34	typename vci_param_int,
35	typename vci_param_ext> TsarXbarCluster<dspin_cmd_width,
36	dspin_rsp_width,
37	vci_param_int,
38	vci_param_ext>::TsarXbarCluster(
39	////////////////////////////////////////////////////////////////////////////////////
40	sc_module_name insname,
41	size_t nb_procs,
42	size_t nb_ttys,
43	size_t nb_dmas,
44	size_t x_id,
45	size_t y_id,
46	size_t cluster_id,
47	const soclib::common::MappingTable &mtd,
48	const soclib::common::MappingTable &mtx,
49	size_t x_width,
50	size_t y_width,
51	size_t l_width,
52	size_t tgtid_memc,
53	size_t tgtid_xicu,
54	size_t tgtid_mdma,
55	size_t tgtid_fbuf,
56	size_t tgtid_mtty,
57	size_t tgtid_brom,
58	size_t tgtid_mnic,
59	size_t tgtid_bdev,
60	size_t memc_ways,
61	size_t memc_sets,
62	size_t l1_i_ways,
63	size_t l1_i_sets,
64	size_t l1_d_ways,
65	size_t l1_d_sets,
66	size_t xram_latency,
67	bool io,
68	size_t xfb,
69	size_t yfb,
70	char* disk_name,
71	size_t block_size,
72	size_t nic_channels,
73	char* nic_rx_name,
74	char* nic_tx_name,
75	uint32_t nic_timeout,
76	const Loader &loader,
77	uint32_t frozen_cycles,
78	uint32_t debug_start_cycle,
79	bool memc_debug_ok,
80	bool proc_debug_ok)
81	: soclib::caba::BaseModule(insname),
82	p_clk("clk"),
83	p_resetn("resetn")
84
85	{
86	// Vectors of ports definition
87	p_cmd_in = alloc_elems<DspinInput<dspin_cmd_width> >("p_cmd_in", 4, 3);
88	p_cmd_out = alloc_elems<DspinOutput<dspin_cmd_width> >("p_cmd_out", 4, 3);
89	p_rsp_in = alloc_elems<DspinInput<dspin_rsp_width> >("p_rsp_in", 4, 2);
90	p_rsp_out = alloc_elems<DspinOutput<dspin_rsp_width> >("p_rsp_out", 4, 2);
91
92	/////////////////////////////////////////////////////////////////////////////
93	// Components definition
94	/////////////////////////////////////////////////////////////////////////////
95
96	for (size_t p = 0; p < nb_procs; p++)
97	{
98	std::ostringstream sproc;
99	sproc << "proc_" << x_id << "_" << y_id << "_" << p;
100	proc[p] = new VciCcVCacheWrapper<vci_param_int,
101	dspin_cmd_width,
102	dspin_rsp_width,
103	GdbServer<Mips32ElIss> >(
104	sproc.str().c_str(),
105	cluster_id*nb_procs + p, // GLOBAL PROC_ID
106	mtd, // Mapping Table
107	IntTab(cluster_id,p), // SRCID
108	(cluster_id << l_width) + p, // CC_GLOBAL_ID
109	8, // ITLB ways
110	8, // ITLB sets
111	8, // DTLB ways
112	8, // DTLB sets
113	l1_i_ways,l1_i_sets,16, // ICACHE size
114	l1_d_ways,l1_d_sets,16, // DCACHE size
115	4, // WBUF nlines
116	4, // WBUF nwords
117	x_width,
118	y_width,
119	frozen_cycles, // max frozen cycles
120	debug_start_cycle,
121	proc_debug_ok);
122
123	std::ostringstream swip;
124	swip << "wi_proc_" << x_id << "_" << y_id << "_" << p;
125	wi_proc[p] = new VciDspinInitiatorWrapper<vci_param_int,
126	dspin_cmd_width,
127	dspin_rsp_width>(
128	swip.str().c_str(),
129	x_width + y_width + l_width);
130	}
131
132	/////////////////////////////////////////////////////////////////////////////
133	std::ostringstream smemc;
134	smemc << "memc_" << x_id << "_" << y_id;
135	memc = new VciMemCache<vci_param_int,
136	vci_param_ext,
137	dspin_rsp_width,
138	dspin_cmd_width>(
139	smemc.str().c_str(),
140	mtd, // Mapping Table direct space
141	mtx, // Mapping Table external space
142	IntTab(cluster_id), // SRCID external space
143	IntTab(cluster_id, tgtid_memc), // TGTID direct space
144	(cluster_id << l_width) + nb_procs, // CC_GLOBAL_ID
145	memc_ways, memc_sets, 16, // CACHE SIZE
146	3, // MAX NUMBER OF COPIES
147	4096, // HEAP SIZE
148	8, // TRANSACTION TABLE DEPTH
149	8, // UPDATE TABLE DEPTH
150	8, // INVALIDATE TABLE DEPTH
151	debug_start_cycle,
152	memc_debug_ok );
153
154	wt_memc = new VciDspinTargetWrapper<vci_param_int,
155	dspin_cmd_width,
156	dspin_rsp_width>(
157	"wt_memc",
158	x_width + y_width + l_width);
159
160	/////////////////////////////////////////////////////////////////////////////
161	std::ostringstream sxram;
162	sxram << "xram_" << x_id << "_" << y_id;
163	xram = new VciSimpleRam<vci_param_ext>(
164	sxram.str().c_str(),
165	IntTab(cluster_id),
166	mtx,
167	loader,
168	xram_latency);
169
170	/////////////////////////////////////////////////////////////////////////////
171	std::ostringstream sxicu;
172	sxicu << "xicu_" << x_id << "_" << y_id;
173	xicu = new VciXicu<vci_param_int>(
174	sxicu.str().c_str(),
175	mtd, // mapping table
176	IntTab(cluster_id, tgtid_xicu), // TGTID_D
177	nb_procs, // number of timer IRQs
178	32, // number of hard IRQs
179	32, // number of soft IRQs
180	nb_procs); // number of output IRQs
181
182	wt_xicu = new VciDspinTargetWrapper<vci_param_int,
183	dspin_cmd_width,
184	dspin_rsp_width>(
185	"wt_xicu",
186	x_width + y_width + l_width);
187
188	/////////////////////////////////////////////////////////////////////////////
189	std::ostringstream smdma;
190	smdma << "mdma_" << x_id << "_" << y_id;
191	mdma = new VciMultiDma<vci_param_int>(
192	smdma.str().c_str(),
193	mtd,
194	IntTab(cluster_id, nb_procs), // SRCID
195	IntTab(cluster_id, tgtid_mdma), // TGTID
196	64, // burst size
197	nb_dmas); // number of IRQs
198
199	wt_mdma = new VciDspinTargetWrapper<vci_param_int,
200	dspin_cmd_width,
201	dspin_rsp_width>(
202	"wt_mdma",
203	x_width + y_width + l_width);
204
205	wi_mdma = new VciDspinInitiatorWrapper<vci_param_int,
206	dspin_cmd_width,
207	dspin_rsp_width>(
208	"wi_mdma",
209	x_width + y_width + l_width);
210
211	/////////////////////////////////////////////////////////////////////////////
212	size_t nb_direct_initiators = nb_procs + 1;
213	size_t nb_direct_targets = 3;
214	if ( io )
215	{
216	nb_direct_initiators = nb_procs + 2;
217	nb_direct_targets = 8;
218	}
219
220	xbar_cmd_d = new DspinLocalCrossbar<dspin_cmd_width>(
221	"xbar_cmd_d",
222	mtd, // mapping table
223	x_id, y_id, // cluster coordinates
224	x_width, y_width, l_width,
225	nb_direct_initiators, // number of local of sources
226	nb_direct_targets, // number of local dests
227	2, 2, // fifo depths
228	true, // CMD
229	true, // use local routing table
230	false ); // no broadcast
231
232	/////////////////////////////////////////////////////////////////////////////
233	xbar_rsp_d = new DspinLocalCrossbar<dspin_rsp_width>(
234	"xbar_rsp_d",
235	mtd, // mapping table
236	x_id, y_id, // cluster coordinates
237	x_width, y_width, l_width,
238	nb_direct_targets, // number of local sources
239	nb_direct_initiators, // number of local dests
240	2, 2, // fifo depths
241	false, // RSP
242	false, // don't use local routing table
243	false ); // no broadcast
244
245	/////////////////////////////////////////////////////////////////////////////
246	xbar_m2p_c = new DspinLocalCrossbar<dspin_cmd_width>(
247	"xbar_m2p_c",
248	mtd, // mapping table
249	x_id, y_id, // cluster coordinates
250	x_width, y_width, l_width,
251	1, // number of local sources
252	nb_procs, // number of local targets
253	2, 2, // fifo depths
254	true, // CMD
255	false, // don't use local routing table
256	true ); // broadcast
257
258	/////////////////////////////////////////////////////////////////////////////
259	xbar_p2m_c = new DspinLocalCrossbar<dspin_rsp_width>(
260	"xbar_p2m_c",
261	mtd, // mapping table
262	x_id, y_id, // cluster coordinates
263	x_width, y_width, 0, // l_width unused on p2m network
264	nb_procs, // number of local sources
265	1, // number of local dests
266	2, 2, // fifo depths
267	false, // RSP
268	false, // don't use local routing table
269	false ); // no broadcast
270
271	/////////////////////////////////////////////////////////////////////////////
272	xbar_clack_c = new DspinLocalCrossbar<dspin_cmd_width>(
273	"xbar_clack_c",
274	mtd, // mapping table
275	x_id, y_id, // cluster coordinates
276	x_width, y_width, l_width,
277	1, // number of local sources
278	nb_procs, // number of local targets
279	1, 1, // fifo depths
280	true, // CMD
281	false, // don't use local routing table
282	false); // broadcast
283
284	/////////////////////////////////////////////////////////////////////////////
285	router_cmd = new VirtualDspinRouter<dspin_cmd_width>(
286	"router_cmd",
287	x_id,y_id, // coordinate in the mesh
288	x_width, y_width, // x & y fields width
289	3, // nb virtual channels
290	4,4); // input & output fifo depths
291
292	/////////////////////////////////////////////////////////////////////////////
293	router_rsp = new VirtualDspinRouter<dspin_rsp_width>(
294	"router_rsp",
295	x_id,y_id, // coordinates in mesh
296	x_width, y_width, // x & y fields width
297	2, // nb virtual channels
298	4,4); // input & output fifo depths
299
300	// IO cluster components
301	if ( io )
302	{
303	/////////////////////////////////////////////
304	brom = new VciSimpleRom<vci_param_int>(
305	"brom",
306	IntTab(cluster_id, tgtid_brom),
307	mtd,
308	loader);
309
310	wt_brom = new VciDspinTargetWrapper<vci_param_int,
311	dspin_cmd_width,
312	dspin_rsp_width>(
313	"wt_brom",
314	x_width + y_width + l_width);
315
316	/////////////////////////////////////////////
317	fbuf = new VciFrameBuffer<vci_param_int>(
318	"fbuf",
319	IntTab(cluster_id, tgtid_fbuf),
320	mtd,
321	xfb, yfb);
322
323	wt_fbuf = new VciDspinTargetWrapper<vci_param_int,
324	dspin_cmd_width,
325	dspin_rsp_width>(
326	"wt_fbuf",
327	x_width + y_width + l_width);
328
329	/////////////////////////////////////////////
330	bdev = new VciBlockDeviceTsar<vci_param_int>(
331	"bdev",
332	mtd,
333	IntTab(cluster_id, nb_procs+1),
334	IntTab(cluster_id, tgtid_bdev),
335	disk_name,
336	block_size,
337	64); // burst size
338
339	wt_bdev = new VciDspinTargetWrapper<vci_param_int,
340	dspin_cmd_width,
341	dspin_rsp_width>(
342	"wt_bdev",
343	x_width + y_width + l_width);
344
345	wi_bdev = new VciDspinInitiatorWrapper<vci_param_int,
346	dspin_cmd_width,
347	dspin_rsp_width>(
348	"wi_bdev",
349	x_width + y_width + l_width);
350
351	/////////////////////////////////////////////
352	mnic = new VciMultiNic<vci_param_int>(
353	"mnic",
354	IntTab(cluster_id, tgtid_mnic),
355	mtd,
356	nic_channels,
357	nic_rx_name,
358	nic_tx_name,
359	0, // mac_4 address
360	0 ); // mac_2 address
361
362	wt_mnic = new VciDspinTargetWrapper<vci_param_int,
363	dspin_cmd_width,
364	dspin_rsp_width>(
365	"wt_mnic",
366	x_width + y_width + l_width);
367
368	/////////////////////////////////////////////
369	std::vector<std::string> vect_names;
370	for( size_t tid = 0 ; tid < (nb_ttys) ; tid++ )
371	{
372	std::ostringstream term_name;
373	term_name << "term" << tid;
374	vect_names.push_back(term_name.str().c_str());
375	}
376	mtty = new VciMultiTty<vci_param_int>(
377	"mtty",
378	IntTab(cluster_id, tgtid_mtty),
379	mtd,
380	vect_names);
381
382	wt_mtty = new VciDspinTargetWrapper<vci_param_int,
383	dspin_cmd_width,
384	dspin_rsp_width>(
385	"wt_mtty",
386	x_width + y_width + l_width);
387	}
388
389	////////////////////////////////////
390	// Connections are defined here
391	////////////////////////////////////
392
393	//////////////////////// CMD ROUTER and RSP ROUTER
394	router_cmd->p_clk (this->p_clk);
395	router_cmd->p_resetn (this->p_resetn);
396	router_rsp->p_clk (this->p_clk);
397	router_rsp->p_resetn (this->p_resetn);
398
399	for(int i = 0; i < 4; i++)
400	{
401	for (int k = 0; k < 3; k++)
402	{
403	router_cmd->p_out[i][k] (this->p_cmd_out[i][k]);
404	router_cmd->p_in[i][k] (this->p_cmd_in[i][k]);
405	}
406
407	for (int k = 0; k < 2; k++)
408	{
409	router_rsp->p_out[i][k] (this->p_rsp_out[i][k]);
410	router_rsp->p_in[i][k] (this->p_rsp_in[i][k]);
411	}
412	}
413
414	router_cmd->p_out[4][0] (signal_dspin_cmd_g2l_d);
415	router_cmd->p_out[4][1] (signal_dspin_m2p_g2l_c);
416	router_cmd->p_out[4][2] (signal_dspin_clack_g2l_c);
417	router_cmd->p_in[4][0] (signal_dspin_cmd_l2g_d);
418	router_cmd->p_in[4][1] (signal_dspin_m2p_l2g_c);
419	router_cmd->p_in[4][2] (signal_dspin_clack_l2g_c);
420
421	router_rsp->p_out[4][0] (signal_dspin_rsp_g2l_d);
422	router_rsp->p_out[4][1] (signal_dspin_p2m_g2l_c);
423	router_rsp->p_in[4][0] (signal_dspin_rsp_l2g_d);
424	router_rsp->p_in[4][1] (signal_dspin_p2m_l2g_c);
425
426
427	std::cout << " - CMD & RSP routers connected" << std::endl;
428
429	///////////////////// CMD DSPIN local crossbar direct
430	xbar_cmd_d->p_clk (this->p_clk);
431	xbar_cmd_d->p_resetn (this->p_resetn);
432	xbar_cmd_d->p_global_out (signal_dspin_cmd_l2g_d);
433	xbar_cmd_d->p_global_in (signal_dspin_cmd_g2l_d);
434
435	xbar_cmd_d->p_local_out[tgtid_memc] (signal_dspin_cmd_memc_t);
436	xbar_cmd_d->p_local_out[tgtid_xicu] (signal_dspin_cmd_xicu_t);
437	xbar_cmd_d->p_local_out[tgtid_mdma] (signal_dspin_cmd_mdma_t);
438
439	xbar_cmd_d->p_local_in[nb_procs] (signal_dspin_cmd_mdma_i);
440
441	for (size_t p = 0; p < nb_procs; p++)
442	xbar_cmd_d->p_local_in[p] (signal_dspin_cmd_proc_i[p]);
443
444	if ( io )
445	{
446	xbar_cmd_d->p_local_out[tgtid_mtty] (signal_dspin_cmd_mtty_t);
447	xbar_cmd_d->p_local_out[tgtid_brom] (signal_dspin_cmd_brom_t);
448	xbar_cmd_d->p_local_out[tgtid_bdev] (signal_dspin_cmd_bdev_t);
449	xbar_cmd_d->p_local_out[tgtid_fbuf] (signal_dspin_cmd_fbuf_t);
450	xbar_cmd_d->p_local_out[tgtid_mnic] (signal_dspin_cmd_mnic_t);
451
452	xbar_cmd_d->p_local_in[nb_procs+1] (signal_dspin_cmd_bdev_i);
453	}
454
455	std::cout << " - Command Direct crossbar connected" << std::endl;
456
457	//////////////////////// RSP DSPIN local crossbar direct
458	xbar_rsp_d->p_clk (this->p_clk);
459	xbar_rsp_d->p_resetn (this->p_resetn);
460	xbar_rsp_d->p_global_out (signal_dspin_rsp_l2g_d);
461	xbar_rsp_d->p_global_in (signal_dspin_rsp_g2l_d);
462
463	xbar_rsp_d->p_local_in[tgtid_memc] (signal_dspin_rsp_memc_t);
464	xbar_rsp_d->p_local_in[tgtid_xicu] (signal_dspin_rsp_xicu_t);
465	xbar_rsp_d->p_local_in[tgtid_mdma] (signal_dspin_rsp_mdma_t);
466
467	xbar_rsp_d->p_local_out[nb_procs] (signal_dspin_rsp_mdma_i);
468
469	for (size_t p = 0; p < nb_procs; p++)
470	xbar_rsp_d->p_local_out[p] (signal_dspin_rsp_proc_i[p]);
471
472	if ( io )
473	{
474	xbar_rsp_d->p_local_in[tgtid_mtty] (signal_dspin_rsp_mtty_t);
475	xbar_rsp_d->p_local_in[tgtid_brom] (signal_dspin_rsp_brom_t);
476	xbar_rsp_d->p_local_in[tgtid_bdev] (signal_dspin_rsp_bdev_t);
477	xbar_rsp_d->p_local_in[tgtid_fbuf] (signal_dspin_rsp_fbuf_t);
478	xbar_rsp_d->p_local_in[tgtid_mnic] (signal_dspin_rsp_mnic_t);
479
480	xbar_rsp_d->p_local_out[nb_procs+1] (signal_dspin_rsp_bdev_i);
481	}
482
483	std::cout << " - Response Direct crossbar connected" << std::endl;
484
485	////////////////////// M2P DSPIN local crossbar coherence
486	xbar_m2p_c->p_clk (this->p_clk);
487	xbar_m2p_c->p_resetn (this->p_resetn);
488	xbar_m2p_c->p_global_out (signal_dspin_m2p_l2g_c);
489	xbar_m2p_c->p_global_in (signal_dspin_m2p_g2l_c);
490	xbar_m2p_c->p_local_in[0] (signal_dspin_m2p_memc);
491	for (size_t p = 0; p < nb_procs; p++)
492	xbar_m2p_c->p_local_out[p] (signal_dspin_m2p_proc[p]);
493
494	std::cout << " - M2P Coherence crossbar connected" << std::endl;
495
496	////////////////////// CLACK DSPIN local crossbar coherence
497	xbar_clack_c->p_clk (this->p_clk);
498	xbar_clack_c->p_resetn (this->p_resetn);
499	xbar_clack_c->p_global_out (signal_dspin_clack_l2g_c);
500	xbar_clack_c->p_global_in (signal_dspin_clack_g2l_c);
501	xbar_clack_c->p_local_in[0] (signal_dspin_clack_memc);
502	for (size_t p = 0; p < nb_procs; p++)
503	xbar_clack_c->p_local_out[p] (signal_dspin_clack_proc[p]);
504
505	std::cout << " - Clack Coherence crossbar connected" << std::endl;
506
507	////////////////////////// P2M DSPIN local crossbar coherence
508	xbar_p2m_c->p_clk (this->p_clk);
509	xbar_p2m_c->p_resetn (this->p_resetn);
510	xbar_p2m_c->p_global_out (signal_dspin_p2m_l2g_c);
511	xbar_p2m_c->p_global_in (signal_dspin_p2m_g2l_c);
512	xbar_p2m_c->p_local_out[0] (signal_dspin_p2m_memc);
513	for (size_t p = 0; p < nb_procs; p++)
514	xbar_p2m_c->p_local_in[p] (signal_dspin_p2m_proc[p]);
515
516	std::cout << " - P2M Coherence crossbar connected" << std::endl;
517
518
519	//////////////////////////////////// Processors
520	for (size_t p = 0; p < nb_procs; p++)
521	{
522	proc[p]->p_clk (this->p_clk);
523	proc[p]->p_resetn (this->p_resetn);
524	proc[p]->p_vci (signal_vci_ini_proc[p]);
525	proc[p]->p_dspin_m2p (signal_dspin_m2p_proc[p]);
526	proc[p]->p_dspin_p2m (signal_dspin_p2m_proc[p]);
527	proc[p]->p_dspin_clack (signal_dspin_clack_proc[p]);
528	proc[p]->p_irq[0] (signal_proc_it[p]);
529	for ( size_t j = 1 ; j < 6 ; j++)
530	{
531	proc[p]->p_irq[j] (signal_false);
532	}
533
534	wi_proc[p]->p_clk (this->p_clk);
535	wi_proc[p]->p_resetn (this->p_resetn);
536	wi_proc[p]->p_dspin_cmd (signal_dspin_cmd_proc_i[p]);
537	wi_proc[p]->p_dspin_rsp (signal_dspin_rsp_proc_i[p]);
538	wi_proc[p]->p_vci (signal_vci_ini_proc[p]);
539	}
540
541	std::cout << " - Processors connected" << std::endl;
542
543	///////////////////////////////////// XICU
544	xicu->p_clk (this->p_clk);
545	xicu->p_resetn (this->p_resetn);
546	xicu->p_vci (signal_vci_tgt_xicu);
547	for ( size_t p=0 ; p<nb_procs ; p++)
548	{
549	xicu->p_irq[p] (signal_proc_it[p]);
550	}
551	for ( size_t i=0 ; i<32 ; i++)
552	{
553	if ( io ) // I/O cluster
554	{
555	if (i < 8) xicu->p_hwi[i] (signal_false);
556	else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i-8]);
557	else if (i < 16) xicu->p_hwi[i] (signal_false);
558	else if (i < (16 + nb_ttys)) xicu->p_hwi[i] (signal_irq_mtty[i-16]);
559	else if (i < 31) xicu->p_hwi[i] (signal_false);
560	else xicu->p_hwi[i] (signal_irq_bdev);
561	}
562	else // other clusters
563	{
564	if (i < 8) xicu->p_hwi[i] (signal_false);
565	else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i-8]);
566	else xicu->p_hwi[i] (signal_false);
567	}
568	}
569
570	// wrapper XICU
571	wt_xicu->p_clk (this->p_clk);
572	wt_xicu->p_resetn (this->p_resetn);
573	wt_xicu->p_dspin_cmd (signal_dspin_cmd_xicu_t);
574	wt_xicu->p_dspin_rsp (signal_dspin_rsp_xicu_t);
575	wt_xicu->p_vci (signal_vci_tgt_xicu);
576
577	std::cout << " - XICU connected" << std::endl;
578
579	//////////////////////////////////////////////// MEMC
580	memc->p_clk (this->p_clk);
581	memc->p_resetn (this->p_resetn);
582	memc->p_vci_ixr (signal_vci_xram);
583	memc->p_vci_tgt (signal_vci_tgt_memc);
584	memc->p_dspin_p2m (signal_dspin_p2m_memc);
585	memc->p_dspin_m2p (signal_dspin_m2p_memc);
586	memc->p_dspin_clack (signal_dspin_clack_memc);
587
588	// wrapper MEMC
589	wt_memc->p_clk (this->p_clk);
590	wt_memc->p_resetn (this->p_resetn);
591	wt_memc->p_dspin_cmd (signal_dspin_cmd_memc_t);
592	wt_memc->p_dspin_rsp (signal_dspin_rsp_memc_t);
593	wt_memc->p_vci (signal_vci_tgt_memc);
594
595	std::cout << " - MEMC connected" << std::endl;
596
597	/////////////////////////////////////////////// XRAM
598	xram->p_clk (this->p_clk);
599	xram->p_resetn (this->p_resetn);
600	xram->p_vci (signal_vci_xram);
601
602	std::cout << " - XRAM connected" << std::endl;
603
604	////////////////////////////////////////////// MDMA
605	mdma->p_clk (this->p_clk);
606	mdma->p_resetn (this->p_resetn);
607	mdma->p_vci_target (signal_vci_tgt_mdma);
608	mdma->p_vci_initiator (signal_vci_ini_mdma);
609	for (size_t i=0 ; i<nb_dmas ; i++)
610	mdma->p_irq[i] (signal_irq_mdma[i]);
611
612	// wrapper tgt MDMA
613	wt_mdma->p_clk (this->p_clk);
614	wt_mdma->p_resetn (this->p_resetn);
615	wt_mdma->p_dspin_cmd (signal_dspin_cmd_mdma_t);
616	wt_mdma->p_dspin_rsp (signal_dspin_rsp_mdma_t);
617	wt_mdma->p_vci (signal_vci_tgt_mdma);
618
619	// wrapper ini MDMA
620	wi_mdma->p_clk (this->p_clk);
621	wi_mdma->p_resetn (this->p_resetn);
622	wi_mdma->p_dspin_cmd (signal_dspin_cmd_mdma_i);
623	wi_mdma->p_dspin_rsp (signal_dspin_rsp_mdma_i);
624	wi_mdma->p_vci (signal_vci_ini_mdma);
625
626	std::cout << " - MDMA connected" << std::endl;
627
628	/////////////////////////////// Components in I/O cluster
629
630	if ( io )
631	{
632	// BDEV
633	bdev->p_clk (this->p_clk);
634	bdev->p_resetn (this->p_resetn);
635	bdev->p_irq (signal_irq_bdev);
636	bdev->p_vci_target (signal_vci_tgt_bdev);
637	bdev->p_vci_initiator (signal_vci_ini_bdev);
638
639	// wrapper tgt BDEV
640	wt_bdev->p_clk (this->p_clk);
641	wt_bdev->p_resetn (this->p_resetn);
642	wt_bdev->p_dspin_cmd (signal_dspin_cmd_bdev_t);
643	wt_bdev->p_dspin_rsp (signal_dspin_rsp_bdev_t);
644	wt_bdev->p_vci (signal_vci_tgt_bdev);
645
646	// wrapper ini BDEV
647	wi_bdev->p_clk (this->p_clk);
648	wi_bdev->p_resetn (this->p_resetn);
649	wi_bdev->p_dspin_cmd (signal_dspin_cmd_bdev_i);
650	wi_bdev->p_dspin_rsp (signal_dspin_rsp_bdev_i);
651	wi_bdev->p_vci (signal_vci_ini_bdev);
652
653	std::cout << " - BDEV connected" << std::endl;
654
655	// FBUF
656	fbuf->p_clk (this->p_clk);
657	fbuf->p_resetn (this->p_resetn);
658	fbuf->p_vci (signal_vci_tgt_fbuf);
659
660	// wrapper tgt FBUF
661	wt_fbuf->p_clk (this->p_clk);
662	wt_fbuf->p_resetn (this->p_resetn);
663	wt_fbuf->p_dspin_cmd (signal_dspin_cmd_fbuf_t);
664	wt_fbuf->p_dspin_rsp (signal_dspin_rsp_fbuf_t);
665	wt_fbuf->p_vci (signal_vci_tgt_fbuf);
666
667	std::cout << " - FBUF connected" << std::endl;
668
669	// MNIC
670	mnic->p_clk (this->p_clk);
671	mnic->p_resetn (this->p_resetn);
672	mnic->p_vci (signal_vci_tgt_mnic);
673	for ( size_t i=0 ; i<nic_channels ; i++ )
674	{
675	mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]);
676	mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]);
677	}
678
679	// wrapper tgt MNIC
680	wt_mnic->p_clk (this->p_clk);
681	wt_mnic->p_resetn (this->p_resetn);
682	wt_mnic->p_dspin_cmd (signal_dspin_cmd_mnic_t);
683	wt_mnic->p_dspin_rsp (signal_dspin_rsp_mnic_t);
684	wt_mnic->p_vci (signal_vci_tgt_mnic);
685
686	std::cout << " - MNIC connected" << std::endl;
687
688	// BROM
689	brom->p_clk (this->p_clk);
690	brom->p_resetn (this->p_resetn);
691	brom->p_vci (signal_vci_tgt_brom);
692
693	// wrapper tgt BROM
694	wt_brom->p_clk (this->p_clk);
695	wt_brom->p_resetn (this->p_resetn);
696	wt_brom->p_dspin_cmd (signal_dspin_cmd_brom_t);
697	wt_brom->p_dspin_rsp (signal_dspin_rsp_brom_t);
698	wt_brom->p_vci (signal_vci_tgt_brom);
699
700	std::cout << " - BROM connected" << std::endl;
701
702	// MTTY
703	mtty->p_clk (this->p_clk);
704	mtty->p_resetn (this->p_resetn);
705	mtty->p_vci (signal_vci_tgt_mtty);
706	for ( size_t i=0 ; i<nb_ttys ; i++ )
707	{
708	mtty->p_irq[i] (signal_irq_mtty[i]);
709	}
710
711	// wrapper tgt MTTY
712	wt_mtty->p_clk (this->p_clk);
713	wt_mtty->p_resetn (this->p_resetn);
714	wt_mtty->p_dspin_cmd (signal_dspin_cmd_mtty_t);
715	wt_mtty->p_dspin_rsp (signal_dspin_rsp_mtty_t);
716	wt_mtty->p_vci (signal_vci_tgt_mtty);
717
718	std::cout << " - MTTY connected" << std::endl;
719	}
720	} // end constructor
721
722	}}
723
724	// Local Variables:
725	// tab-width: 3
726	// c-basic-offset: 3
727	// c-file-offsets:((innamespace . 0)(inline-open . 0))
728	// indent-tabs-mode: nil
729	// End:
730
731	// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
732
733
734

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source: trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp @ 468

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