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source: trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp @ 547

Last change on this file since 547 was 547, checked in by meunier, 11 years ago
Rajout du Sim Helper dans la plateforme tsar_generic_xbar.
File size: 39.1 KB

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1	//////////////////////////////////////////////////////////////////////////////
2	// File: tsar_xbar_cluster.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : march 2011
6	// This program is released under the GNU public license
7	//////////////////////////////////////////////////////////////////////////////
8	// This file define a TSAR cluster architecture with virtual memory:
9	// - It uses two virtual_dspin_router as distributed global interconnect
10	// - It uses four dspin_local_crossbar as local interconnect
11	// - It uses the vci_cc_vcache_wrapper
12	// - It uses the vci_mem_cache
13	// - It contains a private RAM with a variable latency to emulate the L3 cache
14	// - It can contains 1, 2 or 4 processors
15	// - Each processor has a private dma channel (vci_multi_dma)
16	// - It uses the vci_xicu interrupt controller
17	// - The peripherals MTTY, BDEV, FBUF, MNIC and BROM are in cluster (0,0)
18	// - The Multi-TTY component controls up to 15 terminals.
19	// - Each Multi-DMA component controls up to 8 DMA channels.
20	// - The DMA IRQs are connected to IRQ_IN[8]...IRQ_IN[15]
21	// - The TTY IRQs are connected to IRQ_IN[16]...IRQ_IN[30]
22	// - The BDEV IRQ is connected to IRQ_IN[31]
23	//////////////////////////////////////////////////////////////////////////////////
24
25	#include "../include/tsar_xbar_cluster.h"
26
27
28	namespace soclib {
29	namespace caba {
30
31	////////////////////////////////////////////////////////////////////////////////////
32	template<size_t dspin_cmd_width,
33	size_t dspin_rsp_width,
34	typename vci_param_int,
35	typename vci_param_ext> TsarXbarCluster<dspin_cmd_width,
36	dspin_rsp_width,
37	vci_param_int,
38	vci_param_ext>::TsarXbarCluster(
39	////////////////////////////////////////////////////////////////////////////////////
40	sc_module_name insname,
41	size_t nb_procs,
42	size_t nb_ttys,
43	size_t nb_dmas,
44	size_t x_id,
45	size_t y_id,
46	size_t cluster_id,
47	const soclib::common::MappingTable &mtd,
48	const soclib::common::MappingTable &mtx,
49	size_t x_width,
50	size_t y_width,
51	size_t l_width,
52	size_t tgtid_memc,
53	size_t tgtid_xicu,
54	size_t tgtid_mdma,
55	size_t tgtid_fbuf,
56	size_t tgtid_mtty,
57	size_t tgtid_brom,
58	size_t tgtid_mnic,
59	size_t tgtid_chbuf,
60	size_t tgtid_bdev,
61	size_t tgtid_simh,
62	size_t memc_ways,
63	size_t memc_sets,
64	size_t l1_i_ways,
65	size_t l1_i_sets,
66	size_t l1_d_ways,
67	size_t l1_d_sets,
68	size_t xram_latency,
69	bool io,
70	size_t xfb,
71	size_t yfb,
72	char* disk_name,
73	size_t block_size,
74	size_t nic_channels,
75	char* nic_rx_name,
76	char* nic_tx_name,
77	uint32_t nic_timeout,
78	size_t chbufdma_channels,
79	const Loader &loader,
80	uint32_t frozen_cycles,
81	uint32_t debug_start_cycle,
82	bool memc_debug_ok,
83	bool proc_debug_ok)
84	: soclib::caba::BaseModule(insname),
85	p_clk("clk"),
86	p_resetn("resetn")
87
88	{
89
90	n_procs = nb_procs;
91
92	// Vectors of ports definition
93	p_cmd_in = alloc_elems<DspinInput<dspin_cmd_width> > ("p_cmd_in", 4, 3);
94	p_cmd_out = alloc_elems<DspinOutput<dspin_cmd_width> > ("p_cmd_out", 4, 3);
95	p_rsp_in = alloc_elems<DspinInput<dspin_rsp_width> > ("p_rsp_in", 4, 2);
96	p_rsp_out = alloc_elems<DspinOutput<dspin_rsp_width> > ("p_rsp_out", 4, 2);
97
98	/////////////////////////////////////////////////////////////////////////////
99	// Components definition
100	/////////////////////////////////////////////////////////////////////////////
101
102	for (size_t p = 0; p < nb_procs; p++)
103	{
104	std::ostringstream sproc;
105	sproc << "proc_" << x_id << "_" << y_id << "_" << p;
106	proc[p] = new VciCcVCacheWrapper<vci_param_int,
107	dspin_cmd_width,
108	dspin_rsp_width,
109	GdbServer<Mips32ElIss> >(
110	sproc.str().c_str(),
111	cluster_id * nb_procs + p, // GLOBAL PROC_ID
112	mtd, // Mapping Table
113	IntTab(cluster_id,p), // SRCID
114	(cluster_id << l_width) + p, // CC_GLOBAL_ID
115	8, // ITLB ways
116	8, // ITLB sets
117	8, // DTLB ways
118	8, // DTLB sets
119	l1_i_ways,l1_i_sets, 16, // ICACHE size
120	l1_d_ways,l1_d_sets, 16, // DCACHE size
121	4, // WBUF nlines
122	4, // WBUF nwords
123	x_width,
124	y_width,
125	frozen_cycles, // max frozen cycles
126	debug_start_cycle,
127	proc_debug_ok);
128
129	std::ostringstream swip;
130	swip << "wi_proc_" << x_id << "_" << y_id << "_" << p;
131	wi_proc[p] = new VciDspinInitiatorWrapper<vci_param_int,
132	dspin_cmd_width,
133	dspin_rsp_width>(
134	swip.str().c_str(),
135	x_width + y_width + l_width);
136	}
137
138	/////////////////////////////////////////////////////////////////////////////
139	std::ostringstream smemc;
140	smemc << "memc_" << x_id << "_" << y_id;
141	memc = new VciMemCache<vci_param_int,
142	vci_param_ext,
143	dspin_rsp_width,
144	dspin_cmd_width>(
145	smemc.str().c_str(),
146	mtd, // Mapping Table direct space
147	mtx, // Mapping Table external space
148	IntTab(cluster_id), // SRCID external space
149	IntTab(cluster_id, tgtid_memc), // TGTID direct space
150	(cluster_id << l_width) + nb_procs, // CC_GLOBAL_ID
151	x_width, // Number of x bits in platform
152	y_width, // Number of y bits in platform
153	memc_ways, memc_sets, 16, // CACHE SIZE
154	3, // MAX NUMBER OF COPIES
155	4096, // HEAP SIZE
156	8, // TRANSACTION TABLE DEPTH
157	8, // UPDATE TABLE DEPTH
158	8, // INVALIDATE TABLE DEPTH
159	debug_start_cycle,
160	memc_debug_ok);
161
162	wt_memc = new VciDspinTargetWrapper<vci_param_int,
163	dspin_cmd_width,
164	dspin_rsp_width>(
165	"wt_memc",
166	x_width + y_width + l_width);
167
168	/////////////////////////////////////////////////////////////////////////////
169	std::ostringstream sxram;
170	sxram << "xram_" << x_id << "_" << y_id;
171	xram = new VciSimpleRam<vci_param_ext>(
172	sxram.str().c_str(),
173	IntTab(cluster_id),
174	mtx,
175	loader,
176	xram_latency);
177
178	/////////////////////////////////////////////////////////////////////////////
179	std::ostringstream sxicu;
180	sxicu << "xicu_" << x_id << "_" << y_id;
181	xicu = new VciXicu<vci_param_int>(
182	sxicu.str().c_str(),
183	mtd, // mapping table
184	IntTab(cluster_id, tgtid_xicu), // TGTID_D
185	nb_procs, // number of timer IRQs
186	32, // number of hard IRQs
187	32, // number of soft IRQs
188	nb_procs); // number of output IRQs
189
190	wt_xicu = new VciDspinTargetWrapper<vci_param_int,
191	dspin_cmd_width,
192	dspin_rsp_width>(
193	"wt_xicu",
194	x_width + y_width + l_width);
195
196	/////////////////////////////////////////////////////////////////////////////
197	std::ostringstream smdma;
198	smdma << "mdma_" << x_id << "_" << y_id;
199	mdma = new VciMultiDma<vci_param_int>(
200	smdma.str().c_str(),
201	mtd,
202	IntTab(cluster_id, nb_procs), // SRCID
203	IntTab(cluster_id, tgtid_mdma), // TGTID
204	64, // burst size
205	nb_dmas); // number of IRQs
206
207	wt_mdma = new VciDspinTargetWrapper<vci_param_int,
208	dspin_cmd_width,
209	dspin_rsp_width>(
210	"wt_mdma",
211	x_width + y_width + l_width);
212
213	wi_mdma = new VciDspinInitiatorWrapper<vci_param_int,
214	dspin_cmd_width,
215	dspin_rsp_width>(
216	"wi_mdma",
217	x_width + y_width + l_width);
218
219	/////////////////////////////////////////////////////////////////////////////
220	size_t nb_direct_initiators = nb_procs + 1;
221	size_t nb_direct_targets = 3;
222	if (io)
223	{
224	nb_direct_initiators = nb_procs + 3;
225	nb_direct_targets = 10;
226	}
227
228	xbar_cmd_d = new DspinLocalCrossbar<dspin_cmd_width>(
229	"xbar_cmd_d",
230	mtd, // mapping table
231	x_id, y_id, // cluster coordinates
232	x_width, y_width, l_width,
233	nb_direct_initiators, // number of local of sources
234	nb_direct_targets, // number of local dests
235	2, 2, // fifo depths
236	true, // CMD
237	true, // use local routing table
238	false ); // no broadcast
239
240	/////////////////////////////////////////////////////////////////////////////
241	xbar_rsp_d = new DspinLocalCrossbar<dspin_rsp_width>(
242	"xbar_rsp_d",
243	mtd, // mapping table
244	x_id, y_id, // cluster coordinates
245	x_width, y_width, l_width,
246	nb_direct_targets, // number of local sources
247	nb_direct_initiators, // number of local dests
248	2, 2, // fifo depths
249	false, // RSP
250	false, // don't use local routing table
251	false ); // no broadcast
252
253	/////////////////////////////////////////////////////////////////////////////
254	xbar_m2p_c = new DspinLocalCrossbar<dspin_cmd_width>(
255	"xbar_m2p_c",
256	mtd, // mapping table
257	x_id, y_id, // cluster coordinates
258	x_width, y_width, l_width,
259	1, // number of local sources
260	nb_procs, // number of local targets
261	2, 2, // fifo depths
262	true, // CMD
263	false, // don't use local routing table
264	true ); // broadcast
265
266	/////////////////////////////////////////////////////////////////////////////
267	xbar_p2m_c = new DspinLocalCrossbar<dspin_rsp_width>(
268	"xbar_p2m_c",
269	mtd, // mapping table
270	x_id, y_id, // cluster coordinates
271	x_width, y_width, 0, // l_width unused on p2m network
272	nb_procs, // number of local sources
273	1, // number of local dests
274	2, 2, // fifo depths
275	false, // RSP
276	false, // don't use local routing table
277	false ); // no broadcast
278
279	/////////////////////////////////////////////////////////////////////////////
280	xbar_clack_c = new DspinLocalCrossbar<dspin_cmd_width>(
281	"xbar_clack_c",
282	mtd, // mapping table
283	x_id, y_id, // cluster coordinates
284	x_width, y_width, l_width,
285	1, // number of local sources
286	nb_procs, // number of local targets
287	1, 1, // fifo depths
288	true, // CMD
289	false, // don't use local routing table
290	false); // broadcast
291
292	/////////////////////////////////////////////////////////////////////////////
293	router_cmd = new VirtualDspinRouter<dspin_cmd_width>(
294	"router_cmd",
295	x_id,y_id, // coordinate in the mesh
296	x_width, y_width, // x & y fields width
297	3, // nb virtual channels
298	4,4); // input & output fifo depths
299
300	/////////////////////////////////////////////////////////////////////////////
301	router_rsp = new VirtualDspinRouter<dspin_rsp_width>(
302	"router_rsp",
303	x_id,y_id, // coordinates in mesh
304	x_width, y_width, // x & y fields width
305	2, // nb virtual channels
306	4,4); // input & output fifo depths
307
308	// IO cluster components
309	if (io)
310	{
311	/////////////////////////////////////////////
312	brom = new VciSimpleRom<vci_param_int>(
313	"brom",
314	IntTab(cluster_id, tgtid_brom),
315	mtd,
316	loader);
317
318	wt_brom = new VciDspinTargetWrapper<vci_param_int,
319	dspin_cmd_width,
320	dspin_rsp_width>(
321	"wt_brom",
322	x_width + y_width + l_width);
323
324	/////////////////////////////////////////////
325	fbuf = new VciFrameBuffer<vci_param_int>(
326	"fbuf",
327	IntTab(cluster_id, tgtid_fbuf),
328	mtd,
329	xfb, yfb);
330
331	wt_fbuf = new VciDspinTargetWrapper<vci_param_int,
332	dspin_cmd_width,
333	dspin_rsp_width>(
334	"wt_fbuf",
335	x_width + y_width + l_width);
336
337	/////////////////////////////////////////////
338	bdev = new VciBlockDeviceTsar<vci_param_int>(
339	"bdev",
340	mtd,
341	IntTab(cluster_id, nb_procs + 1),
342	IntTab(cluster_id, tgtid_bdev),
343	disk_name,
344	block_size,
345	64); // burst size
346
347	wt_bdev = new VciDspinTargetWrapper<vci_param_int,
348	dspin_cmd_width,
349	dspin_rsp_width>(
350	"wt_bdev",
351	x_width + y_width + l_width);
352
353	wi_bdev = new VciDspinInitiatorWrapper<vci_param_int,
354	dspin_cmd_width,
355	dspin_rsp_width>(
356	"wi_bdev",
357	x_width + y_width + l_width);
358
359	/////////////////////////////////////////////
360	// Commented for almos; we don't want the nic; replaced by a rom
361	//int mac = 0xBEEF0000;
362	//mnic = new VciMultiNic<vci_param_int>(
363	// "mnic",
364	// IntTab(cluster_id, tgtid_mnic),
365	// mtd,
366	// nic_channels,
367	// nic_rx_name,
368	// nic_tx_name,
369	// mac, // mac_4 address
370	// 0xBABE ); // mac_2 address
371	mnic = new VciSimpleRom<vci_param_int>(
372	"mnic",
373	IntTab(cluster_id, tgtid_mnic),
374	mtd,
375	loader);
376
377	wt_mnic = new VciDspinTargetWrapper<vci_param_int,
378	dspin_cmd_width,
379	dspin_rsp_width>(
380	"wt_mnic",
381	x_width + y_width + l_width);
382
383	/////////////////////////////////////////////
384	chbuf = new VciChbufDma<vci_param_int>(
385	"chbuf_dma",
386	mtd,
387	IntTab(cluster_id, nb_procs + 2),
388	IntTab(cluster_id, tgtid_chbuf),
389	64,
390	chbufdma_channels);
391
392	wt_chbuf = new VciDspinTargetWrapper<vci_param_int,
393	dspin_cmd_width,
394	dspin_rsp_width>(
395	"wt_chbuf",
396	x_width + y_width + l_width);
397
398	wi_chbuf = new VciDspinInitiatorWrapper<vci_param_int,
399	dspin_cmd_width,
400	dspin_rsp_width>(
401	"wi_chbuf",
402	x_width + y_width + l_width);
403
404	/////////////////////////////////////////////
405	std::vector<std::string> vect_names;
406	for (size_t tid = 0; tid < nb_ttys; tid++)
407	{
408	std::ostringstream term_name;
409	term_name << "term" << tid;
410	vect_names.push_back(term_name.str().c_str());
411	}
412	mtty = new VciMultiTty<vci_param_int>(
413	"mtty",
414	IntTab(cluster_id, tgtid_mtty),
415	mtd,
416	vect_names);
417
418	wt_mtty = new VciDspinTargetWrapper<vci_param_int,
419	dspin_cmd_width,
420	dspin_rsp_width>(
421	"wt_mtty",
422	x_width + y_width + l_width);
423
424	simhelper = new VciSimhelper<vci_param_int>(
425	"sim_helper",
426	IntTab(cluster_id, tgtid_simh),
427	mtd);
428
429	wt_simhelper = new VciDspinTargetWrapper<vci_param_int,
430	dspin_cmd_width,
431	dspin_rsp_width>(
432	"wt_simhelper",
433	x_width + y_width + l_width);
434	}
435
436	////////////////////////////////////
437	// Connections are defined here
438	////////////////////////////////////
439
440	//////////////////////// CMD ROUTER and RSP ROUTER
441	router_cmd->p_clk (this->p_clk);
442	router_cmd->p_resetn (this->p_resetn);
443	router_rsp->p_clk (this->p_clk);
444	router_rsp->p_resetn (this->p_resetn);
445
446	for (int i = 0; i < 4; i++)
447	{
448	for (int k = 0; k < 3; k++)
449	{
450	router_cmd->p_out[i][k] (this->p_cmd_out[i][k]);
451	router_cmd->p_in[i][k] (this->p_cmd_in[i][k]);
452	}
453
454	for (int k = 0; k < 2; k++)
455	{
456	router_rsp->p_out[i][k] (this->p_rsp_out[i][k]);
457	router_rsp->p_in[i][k] (this->p_rsp_in[i][k]);
458	}
459	}
460
461	router_cmd->p_out[4][0] (signal_dspin_cmd_g2l_d);
462	router_cmd->p_out[4][1] (signal_dspin_m2p_g2l_c);
463	router_cmd->p_out[4][2] (signal_dspin_clack_g2l_c);
464	router_cmd->p_in[4][0] (signal_dspin_cmd_l2g_d);
465	router_cmd->p_in[4][1] (signal_dspin_m2p_l2g_c);
466	router_cmd->p_in[4][2] (signal_dspin_clack_l2g_c);
467
468	router_rsp->p_out[4][0] (signal_dspin_rsp_g2l_d);
469	router_rsp->p_out[4][1] (signal_dspin_p2m_g2l_c);
470	router_rsp->p_in[4][0] (signal_dspin_rsp_l2g_d);
471	router_rsp->p_in[4][1] (signal_dspin_p2m_l2g_c);
472
473
474	std::cout << " - CMD & RSP routers connected" << std::endl;
475
476	///////////////////// CMD DSPIN local crossbar direct
477	xbar_cmd_d->p_clk (this->p_clk);
478	xbar_cmd_d->p_resetn (this->p_resetn);
479	xbar_cmd_d->p_global_out (signal_dspin_cmd_l2g_d);
480	xbar_cmd_d->p_global_in (signal_dspin_cmd_g2l_d);
481
482	xbar_cmd_d->p_local_out[tgtid_memc] (signal_dspin_cmd_memc_t);
483	xbar_cmd_d->p_local_out[tgtid_xicu] (signal_dspin_cmd_xicu_t);
484	xbar_cmd_d->p_local_out[tgtid_mdma] (signal_dspin_cmd_mdma_t);
485
486	xbar_cmd_d->p_local_in[nb_procs] (signal_dspin_cmd_mdma_i);
487
488	for (size_t p = 0; p < nb_procs; p++)
489	xbar_cmd_d->p_local_in[p] (signal_dspin_cmd_proc_i[p]);
490
491	if (io)
492	{
493	xbar_cmd_d->p_local_out[tgtid_mtty] (signal_dspin_cmd_mtty_t);
494	xbar_cmd_d->p_local_out[tgtid_brom] (signal_dspin_cmd_brom_t);
495	xbar_cmd_d->p_local_out[tgtid_bdev] (signal_dspin_cmd_bdev_t);
496	xbar_cmd_d->p_local_out[tgtid_fbuf] (signal_dspin_cmd_fbuf_t);
497	xbar_cmd_d->p_local_out[tgtid_mnic] (signal_dspin_cmd_mnic_t);
498	xbar_cmd_d->p_local_out[tgtid_chbuf] (signal_dspin_cmd_chbuf_t);
499	xbar_cmd_d->p_local_out[tgtid_simh] (signal_dspin_cmd_simh_t);
500
501	xbar_cmd_d->p_local_in[nb_procs + 1] (signal_dspin_cmd_bdev_i);
502	xbar_cmd_d->p_local_in[nb_procs + 2] (signal_dspin_cmd_chbuf_i);
503	}
504
505	std::cout << " - Command Direct crossbar connected" << std::endl;
506
507	//////////////////////// RSP DSPIN local crossbar direct
508	xbar_rsp_d->p_clk (this->p_clk);
509	xbar_rsp_d->p_resetn (this->p_resetn);
510	xbar_rsp_d->p_global_out (signal_dspin_rsp_l2g_d);
511	xbar_rsp_d->p_global_in (signal_dspin_rsp_g2l_d);
512
513	xbar_rsp_d->p_local_in[tgtid_memc] (signal_dspin_rsp_memc_t);
514	xbar_rsp_d->p_local_in[tgtid_xicu] (signal_dspin_rsp_xicu_t);
515	xbar_rsp_d->p_local_in[tgtid_mdma] (signal_dspin_rsp_mdma_t);
516
517	xbar_rsp_d->p_local_out[nb_procs] (signal_dspin_rsp_mdma_i);
518
519	for (size_t p = 0; p < nb_procs; p++)
520	xbar_rsp_d->p_local_out[p] (signal_dspin_rsp_proc_i[p]);
521
522	if (io)
523	{
524	xbar_rsp_d->p_local_in[tgtid_mtty] (signal_dspin_rsp_mtty_t);
525	xbar_rsp_d->p_local_in[tgtid_brom] (signal_dspin_rsp_brom_t);
526	xbar_rsp_d->p_local_in[tgtid_bdev] (signal_dspin_rsp_bdev_t);
527	xbar_rsp_d->p_local_in[tgtid_fbuf] (signal_dspin_rsp_fbuf_t);
528	xbar_rsp_d->p_local_in[tgtid_mnic] (signal_dspin_rsp_mnic_t);
529	xbar_rsp_d->p_local_in[tgtid_chbuf] (signal_dspin_rsp_chbuf_t);
530	xbar_rsp_d->p_local_in[tgtid_simh] (signal_dspin_rsp_simh_t);
531
532	xbar_rsp_d->p_local_out[nb_procs + 1] (signal_dspin_rsp_bdev_i);
533	xbar_rsp_d->p_local_out[nb_procs + 2] (signal_dspin_rsp_chbuf_i);
534	}
535
536	std::cout << " - Response Direct crossbar connected" << std::endl;
537
538	////////////////////// M2P DSPIN local crossbar coherence
539	xbar_m2p_c->p_clk (this->p_clk);
540	xbar_m2p_c->p_resetn (this->p_resetn);
541	xbar_m2p_c->p_global_out (signal_dspin_m2p_l2g_c);
542	xbar_m2p_c->p_global_in (signal_dspin_m2p_g2l_c);
543	xbar_m2p_c->p_local_in[0] (signal_dspin_m2p_memc);
544	for (size_t p = 0; p < nb_procs; p++)
545	xbar_m2p_c->p_local_out[p] (signal_dspin_m2p_proc[p]);
546
547	std::cout << " - M2P Coherence crossbar connected" << std::endl;
548
549	////////////////////// CLACK DSPIN local crossbar coherence
550	xbar_clack_c->p_clk (this->p_clk);
551	xbar_clack_c->p_resetn (this->p_resetn);
552	xbar_clack_c->p_global_out (signal_dspin_clack_l2g_c);
553	xbar_clack_c->p_global_in (signal_dspin_clack_g2l_c);
554	xbar_clack_c->p_local_in[0] (signal_dspin_clack_memc);
555	for (size_t p = 0; p < nb_procs; p++)
556	xbar_clack_c->p_local_out[p] (signal_dspin_clack_proc[p]);
557
558	std::cout << " - Clack Coherence crossbar connected" << std::endl;
559
560	////////////////////////// P2M DSPIN local crossbar coherence
561	xbar_p2m_c->p_clk (this->p_clk);
562	xbar_p2m_c->p_resetn (this->p_resetn);
563	xbar_p2m_c->p_global_out (signal_dspin_p2m_l2g_c);
564	xbar_p2m_c->p_global_in (signal_dspin_p2m_g2l_c);
565	xbar_p2m_c->p_local_out[0] (signal_dspin_p2m_memc);
566	for (size_t p = 0; p < nb_procs; p++)
567	xbar_p2m_c->p_local_in[p] (signal_dspin_p2m_proc[p]);
568
569	std::cout << " - P2M Coherence crossbar connected" << std::endl;
570
571
572	//////////////////////////////////// Processors
573	for (size_t p = 0; p < nb_procs; p++)
574	{
575	proc[p]->p_clk (this->p_clk);
576	proc[p]->p_resetn (this->p_resetn);
577	proc[p]->p_vci (signal_vci_ini_proc[p]);
578	proc[p]->p_dspin_m2p (signal_dspin_m2p_proc[p]);
579	proc[p]->p_dspin_p2m (signal_dspin_p2m_proc[p]);
580	proc[p]->p_dspin_clack (signal_dspin_clack_proc[p]);
581	proc[p]->p_irq[0] (signal_proc_it[p]);
582	for ( size_t j = 1 ; j < 6 ; j++)
583	{
584	proc[p]->p_irq[j] (signal_false);
585	}
586
587	wi_proc[p]->p_clk (this->p_clk);
588	wi_proc[p]->p_resetn (this->p_resetn);
589	wi_proc[p]->p_dspin_cmd (signal_dspin_cmd_proc_i[p]);
590	wi_proc[p]->p_dspin_rsp (signal_dspin_rsp_proc_i[p]);
591	wi_proc[p]->p_vci (signal_vci_ini_proc[p]);
592	}
593
594	std::cout << " - Processors connected" << std::endl;
595
596	///////////////////////////////////// XICU
597	xicu->p_clk (this->p_clk);
598	xicu->p_resetn (this->p_resetn);
599	xicu->p_vci (signal_vci_tgt_xicu);
600	for (size_t p = 0; p < nb_procs; p++)
601	{
602	xicu->p_irq[p] (signal_proc_it[p]);
603	}
604	for (size_t i = 0; i < 32; i++)
605	{
606	if (io) // I/O cluster
607	{
608	if (i < 8) xicu->p_hwi[i] (signal_false);
609	else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i - 8]);
610	else if (i < 16) xicu->p_hwi[i] (signal_false);
611	else if (i < (16 + nb_ttys)) xicu->p_hwi[i] (signal_irq_mtty[i - 16]);
612	else if (i < 31) xicu->p_hwi[i] (signal_false);
613	else xicu->p_hwi[i] (signal_irq_bdev);
614	}
615	else // other clusters
616	{
617	if (i < 8) xicu->p_hwi[i] (signal_false);
618	else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i - 8]);
619	else xicu->p_hwi[i] (signal_false);
620	}
621	}
622
623	// wrapper XICU
624	wt_xicu->p_clk (this->p_clk);
625	wt_xicu->p_resetn (this->p_resetn);
626	wt_xicu->p_dspin_cmd (signal_dspin_cmd_xicu_t);
627	wt_xicu->p_dspin_rsp (signal_dspin_rsp_xicu_t);
628	wt_xicu->p_vci (signal_vci_tgt_xicu);
629
630	std::cout << " - XICU connected" << std::endl;
631
632	//////////////////////////////////////////////// MEMC
633	memc->p_clk (this->p_clk);
634	memc->p_resetn (this->p_resetn);
635	memc->p_vci_ixr (signal_vci_xram);
636	memc->p_vci_tgt (signal_vci_tgt_memc);
637	memc->p_dspin_p2m (signal_dspin_p2m_memc);
638	memc->p_dspin_m2p (signal_dspin_m2p_memc);
639	memc->p_dspin_clack (signal_dspin_clack_memc);
640
641	// wrapper MEMC
642	wt_memc->p_clk (this->p_clk);
643	wt_memc->p_resetn (this->p_resetn);
644	wt_memc->p_dspin_cmd (signal_dspin_cmd_memc_t);
645	wt_memc->p_dspin_rsp (signal_dspin_rsp_memc_t);
646	wt_memc->p_vci (signal_vci_tgt_memc);
647
648	std::cout << " - MEMC connected" << std::endl;
649
650	/////////////////////////////////////////////// XRAM
651	xram->p_clk (this->p_clk);
652	xram->p_resetn (this->p_resetn);
653	xram->p_vci (signal_vci_xram);
654
655	std::cout << " - XRAM connected" << std::endl;
656
657	////////////////////////////////////////////// MDMA
658	mdma->p_clk (this->p_clk);
659	mdma->p_resetn (this->p_resetn);
660	mdma->p_vci_target (signal_vci_tgt_mdma);
661	mdma->p_vci_initiator (signal_vci_ini_mdma);
662	for (size_t i = 0; i < nb_dmas; i++)
663	mdma->p_irq[i] (signal_irq_mdma[i]);
664
665	// wrapper tgt MDMA
666	wt_mdma->p_clk (this->p_clk);
667	wt_mdma->p_resetn (this->p_resetn);
668	wt_mdma->p_dspin_cmd (signal_dspin_cmd_mdma_t);
669	wt_mdma->p_dspin_rsp (signal_dspin_rsp_mdma_t);
670	wt_mdma->p_vci (signal_vci_tgt_mdma);
671
672	// wrapper ini MDMA
673	wi_mdma->p_clk (this->p_clk);
674	wi_mdma->p_resetn (this->p_resetn);
675	wi_mdma->p_dspin_cmd (signal_dspin_cmd_mdma_i);
676	wi_mdma->p_dspin_rsp (signal_dspin_rsp_mdma_i);
677	wi_mdma->p_vci (signal_vci_ini_mdma);
678
679	std::cout << " - MDMA connected" << std::endl;
680
681	/////////////////////////////// Components in I/O cluster
682
683	if (io)
684	{
685	// BDEV
686	bdev->p_clk (this->p_clk);
687	bdev->p_resetn (this->p_resetn);
688	bdev->p_irq (signal_irq_bdev);
689	bdev->p_vci_target (signal_vci_tgt_bdev);
690	bdev->p_vci_initiator (signal_vci_ini_bdev);
691
692	// wrapper tgt BDEV
693	wt_bdev->p_clk (this->p_clk);
694	wt_bdev->p_resetn (this->p_resetn);
695	wt_bdev->p_dspin_cmd (signal_dspin_cmd_bdev_t);
696	wt_bdev->p_dspin_rsp (signal_dspin_rsp_bdev_t);
697	wt_bdev->p_vci (signal_vci_tgt_bdev);
698
699	// wrapper ini BDEV
700	wi_bdev->p_clk (this->p_clk);
701	wi_bdev->p_resetn (this->p_resetn);
702	wi_bdev->p_dspin_cmd (signal_dspin_cmd_bdev_i);
703	wi_bdev->p_dspin_rsp (signal_dspin_rsp_bdev_i);
704	wi_bdev->p_vci (signal_vci_ini_bdev);
705
706	std::cout << " - BDEV connected" << std::endl;
707
708	// FBUF
709	fbuf->p_clk (this->p_clk);
710	fbuf->p_resetn (this->p_resetn);
711	fbuf->p_vci (signal_vci_tgt_fbuf);
712
713	// wrapper tgt FBUF
714	wt_fbuf->p_clk (this->p_clk);
715	wt_fbuf->p_resetn (this->p_resetn);
716	wt_fbuf->p_dspin_cmd (signal_dspin_cmd_fbuf_t);
717	wt_fbuf->p_dspin_rsp (signal_dspin_rsp_fbuf_t);
718	wt_fbuf->p_vci (signal_vci_tgt_fbuf);
719
720	std::cout << " - FBUF connected" << std::endl;
721
722	// MNIC
723	mnic->p_clk (this->p_clk);
724	mnic->p_resetn (this->p_resetn);
725	mnic->p_vci (signal_vci_tgt_mnic);
726	for (size_t i = 0; i < nic_channels; i++)
727	{
728	//mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]);
729	//mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]);
730	}
731
732	// wrapper tgt MNIC
733	wt_mnic->p_clk (this->p_clk);
734	wt_mnic->p_resetn (this->p_resetn);
735	wt_mnic->p_dspin_cmd (signal_dspin_cmd_mnic_t);
736	wt_mnic->p_dspin_rsp (signal_dspin_rsp_mnic_t);
737	wt_mnic->p_vci (signal_vci_tgt_mnic);
738
739	std::cout << " - MNIC connected" << std::endl;
740
741	// CHBUF
742	chbuf->p_clk (this->p_clk);
743	chbuf->p_resetn (this->p_resetn);
744	chbuf->p_vci_target (signal_vci_tgt_chbuf);
745	chbuf->p_vci_initiator (signal_vci_ini_chbuf);
746	for (size_t i = 0; i < chbufdma_channels; i++)
747	{
748	chbuf->p_irq[i] (signal_irq_chbuf[i]);
749	}
750
751	// wrapper tgt CHBUF
752	wt_chbuf->p_clk (this->p_clk);
753	wt_chbuf->p_resetn (this->p_resetn);
754	wt_chbuf->p_dspin_cmd (signal_dspin_cmd_chbuf_t);
755	wt_chbuf->p_dspin_rsp (signal_dspin_rsp_chbuf_t);
756	wt_chbuf->p_vci (signal_vci_tgt_chbuf);
757
758	// wrapper ini CHBUF
759	wi_chbuf->p_clk (this->p_clk);
760	wi_chbuf->p_resetn (this->p_resetn);
761	wi_chbuf->p_dspin_cmd (signal_dspin_cmd_chbuf_i);
762	wi_chbuf->p_dspin_rsp (signal_dspin_rsp_chbuf_i);
763	wi_chbuf->p_vci (signal_vci_ini_chbuf);
764
765	std::cout << " - CHBUF connected" << std::endl;
766
767	// BROM
768	brom->p_clk (this->p_clk);
769	brom->p_resetn (this->p_resetn);
770	brom->p_vci (signal_vci_tgt_brom);
771
772	// wrapper tgt BROM
773	wt_brom->p_clk (this->p_clk);
774	wt_brom->p_resetn (this->p_resetn);
775	wt_brom->p_dspin_cmd (signal_dspin_cmd_brom_t);
776	wt_brom->p_dspin_rsp (signal_dspin_rsp_brom_t);
777	wt_brom->p_vci (signal_vci_tgt_brom);
778
779	std::cout << " - BROM connected" << std::endl;
780
781	// MTTY
782	mtty->p_clk (this->p_clk);
783	mtty->p_resetn (this->p_resetn);
784	mtty->p_vci (signal_vci_tgt_mtty);
785	for (size_t i = 0; i < nb_ttys; i++)
786	{
787	mtty->p_irq[i] (signal_irq_mtty[i]);
788	}
789
790	// wrapper tgt MTTY
791	wt_mtty->p_clk (this->p_clk);
792	wt_mtty->p_resetn (this->p_resetn);
793	wt_mtty->p_dspin_cmd (signal_dspin_cmd_mtty_t);
794	wt_mtty->p_dspin_rsp (signal_dspin_rsp_mtty_t);
795	wt_mtty->p_vci (signal_vci_tgt_mtty);
796
797
798	// Sim Helper
799	simhelper->p_clk (this->p_clk);
800	simhelper->p_resetn (this->p_resetn);
801	simhelper->p_vci (signal_vci_tgt_simh);
802
803	// wrapper tgt Sim Helper
804	wt_simhelper->p_clk (this->p_clk);
805	wt_simhelper->p_resetn (this->p_resetn);
806	wt_simhelper->p_dspin_cmd (signal_dspin_cmd_simh_t);
807	wt_simhelper->p_dspin_rsp (signal_dspin_rsp_simh_t);
808	wt_simhelper->p_vci (signal_vci_tgt_simh);
809
810	std::cout << " - MTTY connected" << std::endl;
811	}
812	} // end constructor
813
814
815
816	template<size_t dspin_cmd_width,
817	size_t dspin_rsp_width,
818	typename vci_param_int,
819	typename vci_param_ext> TsarXbarCluster<dspin_cmd_width,
820	dspin_rsp_width,
821	vci_param_int,
822	vci_param_ext>::~TsarXbarCluster() {
823
824	dealloc_elems<DspinInput<dspin_cmd_width> > (p_cmd_in, 4, 3);
825	dealloc_elems<DspinOutput<dspin_cmd_width> >(p_cmd_out, 4, 3);
826	dealloc_elems<DspinInput<dspin_rsp_width> > (p_rsp_in, 4, 2);
827	dealloc_elems<DspinOutput<dspin_rsp_width> >(p_rsp_out, 4, 2);
828
829	for (size_t p = 0; p < n_procs; p++)
830	{
831	delete proc[p];
832	delete wi_proc[p];
833	}
834
835	delete memc;
836	delete wt_memc;
837	delete xram;
838	delete xicu;
839	delete wt_xicu;
840	delete mdma;
841	delete wt_mdma;
842	delete wi_mdma;
843	delete xbar_cmd_d;
844	delete xbar_rsp_d;
845	delete xbar_m2p_c;
846	delete xbar_p2m_c;
847	delete xbar_clack_c;
848	delete router_cmd;
849	delete router_rsp;
850	if (brom != NULL)
851	{
852	delete brom;
853	delete wt_brom;
854	delete fbuf;
855	delete wt_fbuf;
856	delete bdev;
857	delete wt_bdev;
858	delete wi_bdev;
859	delete mnic;
860	delete wt_mnic;
861	delete chbuf;
862	delete wt_chbuf;
863	delete wi_chbuf;
864	delete mtty;
865	delete wt_mtty;
866	delete simhelper;
867	delete wt_simhelper;
868	}
869	}
870
871
872	}}
873
874	// Local Variables:
875	// tab-width: 4
876	// c-basic-offset: 4
877	// c-file-offsets:((innamespace . 0)(inline-open . 0))
878	// indent-tabs-mode: nil
879	// End:
880
881	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
882
883
884

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Project-Id-Version: Trac 0.12
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