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source: trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp @ 548

Last change on this file since 548 was 548, checked in by meunier, 11 years ago
Last commit contained unwanted local modifications; reverting them.
File size: 38.7 KB

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1	//////////////////////////////////////////////////////////////////////////////
2	// File: tsar_xbar_cluster.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : march 2011
6	// This program is released under the GNU public license
7	//////////////////////////////////////////////////////////////////////////////
8	// This file define a TSAR cluster architecture with virtual memory:
9	// - It uses two virtual_dspin_router as distributed global interconnect
10	// - It uses four dspin_local_crossbar as local interconnect
11	// - It uses the vci_cc_vcache_wrapper
12	// - It uses the vci_mem_cache
13	// - It contains a private RAM with a variable latency to emulate the L3 cache
14	// - It can contains 1, 2 or 4 processors
15	// - Each processor has a private dma channel (vci_multi_dma)
16	// - It uses the vci_xicu interrupt controller
17	// - The peripherals MTTY, BDEV, FBUF, MNIC and BROM are in cluster (0,0)
18	// - The Multi-TTY component controls up to 15 terminals.
19	// - Each Multi-DMA component controls up to 8 DMA channels.
20	// - The DMA IRQs are connected to IRQ_IN[8]...IRQ_IN[15]
21	// - The TTY IRQs are connected to IRQ_IN[16]...IRQ_IN[30]
22	// - The BDEV IRQ is connected to IRQ_IN[31]
23	//////////////////////////////////////////////////////////////////////////////////
24
25	#include "../include/tsar_xbar_cluster.h"
26
27
28	namespace soclib {
29	namespace caba {
30
31	////////////////////////////////////////////////////////////////////////////////////
32	template<size_t dspin_cmd_width,
33	size_t dspin_rsp_width,
34	typename vci_param_int,
35	typename vci_param_ext> TsarXbarCluster<dspin_cmd_width,
36	dspin_rsp_width,
37	vci_param_int,
38	vci_param_ext>::TsarXbarCluster(
39	////////////////////////////////////////////////////////////////////////////////////
40	sc_module_name insname,
41	size_t nb_procs,
42	size_t nb_ttys,
43	size_t nb_dmas,
44	size_t x_id,
45	size_t y_id,
46	size_t cluster_id,
47	const soclib::common::MappingTable &mtd,
48	const soclib::common::MappingTable &mtx,
49	size_t x_width,
50	size_t y_width,
51	size_t l_width,
52	size_t tgtid_memc,
53	size_t tgtid_xicu,
54	size_t tgtid_mdma,
55	size_t tgtid_fbuf,
56	size_t tgtid_mtty,
57	size_t tgtid_brom,
58	size_t tgtid_mnic,
59	size_t tgtid_chbuf,
60	size_t tgtid_bdev,
61	size_t tgtid_simh,
62	size_t memc_ways,
63	size_t memc_sets,
64	size_t l1_i_ways,
65	size_t l1_i_sets,
66	size_t l1_d_ways,
67	size_t l1_d_sets,
68	size_t xram_latency,
69	bool io,
70	size_t xfb,
71	size_t yfb,
72	char* disk_name,
73	size_t block_size,
74	size_t nic_channels,
75	char* nic_rx_name,
76	char* nic_tx_name,
77	uint32_t nic_timeout,
78	size_t chbufdma_channels,
79	const Loader &loader,
80	uint32_t frozen_cycles,
81	uint32_t debug_start_cycle,
82	bool memc_debug_ok,
83	bool proc_debug_ok)
84	: soclib::caba::BaseModule(insname),
85	p_clk("clk"),
86	p_resetn("resetn")
87
88	{
89
90	n_procs = nb_procs;
91
92	// Vectors of ports definition
93	p_cmd_in = alloc_elems<DspinInput<dspin_cmd_width> > ("p_cmd_in", 4, 3);
94	p_cmd_out = alloc_elems<DspinOutput<dspin_cmd_width> > ("p_cmd_out", 4, 3);
95	p_rsp_in = alloc_elems<DspinInput<dspin_rsp_width> > ("p_rsp_in", 4, 2);
96	p_rsp_out = alloc_elems<DspinOutput<dspin_rsp_width> > ("p_rsp_out", 4, 2);
97
98	/////////////////////////////////////////////////////////////////////////////
99	// Components definition
100	/////////////////////////////////////////////////////////////////////////////
101
102	for (size_t p = 0; p < nb_procs; p++)
103	{
104	std::ostringstream sproc;
105	sproc << "proc_" << x_id << "_" << y_id << "_" << p;
106	proc[p] = new VciCcVCacheWrapper<vci_param_int,
107	dspin_cmd_width,
108	dspin_rsp_width,
109	GdbServer<Mips32ElIss> >(
110	sproc.str().c_str(),
111	cluster_id * nb_procs + p, // GLOBAL PROC_ID
112	mtd, // Mapping Table
113	IntTab(cluster_id,p), // SRCID
114	(cluster_id << l_width) + p, // CC_GLOBAL_ID
115	8, // ITLB ways
116	8, // ITLB sets
117	8, // DTLB ways
118	8, // DTLB sets
119	l1_i_ways,l1_i_sets, 16, // ICACHE size
120	l1_d_ways,l1_d_sets, 16, // DCACHE size
121	4, // WBUF nlines
122	4, // WBUF nwords
123	x_width,
124	y_width,
125	frozen_cycles, // max frozen cycles
126	debug_start_cycle,
127	proc_debug_ok);
128
129	std::ostringstream swip;
130	swip << "wi_proc_" << x_id << "_" << y_id << "_" << p;
131	wi_proc[p] = new VciDspinInitiatorWrapper<vci_param_int,
132	dspin_cmd_width,
133	dspin_rsp_width>(
134	swip.str().c_str(),
135	x_width + y_width + l_width);
136	}
137
138	/////////////////////////////////////////////////////////////////////////////
139	std::ostringstream smemc;
140	smemc << "memc_" << x_id << "_" << y_id;
141	memc = new VciMemCache<vci_param_int,
142	vci_param_ext,
143	dspin_rsp_width,
144	dspin_cmd_width>(
145	smemc.str().c_str(),
146	mtd, // Mapping Table direct space
147	mtx, // Mapping Table external space
148	IntTab(cluster_id), // SRCID external space
149	IntTab(cluster_id, tgtid_memc), // TGTID direct space
150	(cluster_id << l_width) + nb_procs, // CC_GLOBAL_ID
151	x_width, // Number of x bits in platform
152	y_width, // Number of y bits in platform
153	memc_ways, memc_sets, 16, // CACHE SIZE
154	3, // MAX NUMBER OF COPIES
155	4096, // HEAP SIZE
156	8, // TRANSACTION TABLE DEPTH
157	8, // UPDATE TABLE DEPTH
158	8, // INVALIDATE TABLE DEPTH
159	debug_start_cycle,
160	memc_debug_ok);
161
162	wt_memc = new VciDspinTargetWrapper<vci_param_int,
163	dspin_cmd_width,
164	dspin_rsp_width>(
165	"wt_memc",
166	x_width + y_width + l_width);
167
168	/////////////////////////////////////////////////////////////////////////////
169	std::ostringstream sxram;
170	sxram << "xram_" << x_id << "_" << y_id;
171	xram = new VciSimpleRam<vci_param_ext>(
172	sxram.str().c_str(),
173	IntTab(cluster_id),
174	mtx,
175	loader,
176	xram_latency);
177
178	/////////////////////////////////////////////////////////////////////////////
179	std::ostringstream sxicu;
180	sxicu << "xicu_" << x_id << "_" << y_id;
181	xicu = new VciXicu<vci_param_int>(
182	sxicu.str().c_str(),
183	mtd, // mapping table
184	IntTab(cluster_id, tgtid_xicu), // TGTID_D
185	nb_procs, // number of timer IRQs
186	32, // number of hard IRQs
187	32, // number of soft IRQs
188	nb_procs); // number of output IRQs
189
190	wt_xicu = new VciDspinTargetWrapper<vci_param_int,
191	dspin_cmd_width,
192	dspin_rsp_width>(
193	"wt_xicu",
194	x_width + y_width + l_width);
195
196	/////////////////////////////////////////////////////////////////////////////
197	std::ostringstream smdma;
198	smdma << "mdma_" << x_id << "_" << y_id;
199	mdma = new VciMultiDma<vci_param_int>(
200	smdma.str().c_str(),
201	mtd,
202	IntTab(cluster_id, nb_procs), // SRCID
203	IntTab(cluster_id, tgtid_mdma), // TGTID
204	64, // burst size
205	nb_dmas); // number of IRQs
206
207	wt_mdma = new VciDspinTargetWrapper<vci_param_int,
208	dspin_cmd_width,
209	dspin_rsp_width>(
210	"wt_mdma",
211	x_width + y_width + l_width);
212
213	wi_mdma = new VciDspinInitiatorWrapper<vci_param_int,
214	dspin_cmd_width,
215	dspin_rsp_width>(
216	"wi_mdma",
217	x_width + y_width + l_width);
218
219	/////////////////////////////////////////////////////////////////////////////
220	size_t nb_direct_initiators = nb_procs + 1;
221	size_t nb_direct_targets = 3;
222	if (io)
223	{
224	nb_direct_initiators = nb_procs + 3;
225	nb_direct_targets = 10;
226	}
227
228	xbar_cmd_d = new DspinLocalCrossbar<dspin_cmd_width>(
229	"xbar_cmd_d",
230	mtd, // mapping table
231	x_id, y_id, // cluster coordinates
232	x_width, y_width, l_width,
233	nb_direct_initiators, // number of local of sources
234	nb_direct_targets, // number of local dests
235	2, 2, // fifo depths
236	true, // CMD
237	true, // use local routing table
238	false ); // no broadcast
239
240	/////////////////////////////////////////////////////////////////////////////
241	xbar_rsp_d = new DspinLocalCrossbar<dspin_rsp_width>(
242	"xbar_rsp_d",
243	mtd, // mapping table
244	x_id, y_id, // cluster coordinates
245	x_width, y_width, l_width,
246	nb_direct_targets, // number of local sources
247	nb_direct_initiators, // number of local dests
248	2, 2, // fifo depths
249	false, // RSP
250	false, // don't use local routing table
251	false ); // no broadcast
252
253	/////////////////////////////////////////////////////////////////////////////
254	xbar_m2p_c = new DspinLocalCrossbar<dspin_cmd_width>(
255	"xbar_m2p_c",
256	mtd, // mapping table
257	x_id, y_id, // cluster coordinates
258	x_width, y_width, l_width,
259	1, // number of local sources
260	nb_procs, // number of local targets
261	2, 2, // fifo depths
262	true, // CMD
263	false, // don't use local routing table
264	true ); // broadcast
265
266	/////////////////////////////////////////////////////////////////////////////
267	xbar_p2m_c = new DspinLocalCrossbar<dspin_rsp_width>(
268	"xbar_p2m_c",
269	mtd, // mapping table
270	x_id, y_id, // cluster coordinates
271	x_width, y_width, 0, // l_width unused on p2m network
272	nb_procs, // number of local sources
273	1, // number of local dests
274	2, 2, // fifo depths
275	false, // RSP
276	false, // don't use local routing table
277	false ); // no broadcast
278
279	/////////////////////////////////////////////////////////////////////////////
280	xbar_clack_c = new DspinLocalCrossbar<dspin_cmd_width>(
281	"xbar_clack_c",
282	mtd, // mapping table
283	x_id, y_id, // cluster coordinates
284	x_width, y_width, l_width,
285	1, // number of local sources
286	nb_procs, // number of local targets
287	1, 1, // fifo depths
288	true, // CMD
289	false, // don't use local routing table
290	false); // broadcast
291
292	/////////////////////////////////////////////////////////////////////////////
293	router_cmd = new VirtualDspinRouter<dspin_cmd_width>(
294	"router_cmd",
295	x_id,y_id, // coordinate in the mesh
296	x_width, y_width, // x & y fields width
297	3, // nb virtual channels
298	4,4); // input & output fifo depths
299
300	/////////////////////////////////////////////////////////////////////////////
301	router_rsp = new VirtualDspinRouter<dspin_rsp_width>(
302	"router_rsp",
303	x_id,y_id, // coordinates in mesh
304	x_width, y_width, // x & y fields width
305	2, // nb virtual channels
306	4,4); // input & output fifo depths
307
308	// IO cluster components
309	if (io)
310	{
311	/////////////////////////////////////////////
312	brom = new VciSimpleRom<vci_param_int>(
313	"brom",
314	IntTab(cluster_id, tgtid_brom),
315	mtd,
316	loader);
317
318	wt_brom = new VciDspinTargetWrapper<vci_param_int,
319	dspin_cmd_width,
320	dspin_rsp_width>(
321	"wt_brom",
322	x_width + y_width + l_width);
323
324	/////////////////////////////////////////////
325	fbuf = new VciFrameBuffer<vci_param_int>(
326	"fbuf",
327	IntTab(cluster_id, tgtid_fbuf),
328	mtd,
329	xfb, yfb);
330
331	wt_fbuf = new VciDspinTargetWrapper<vci_param_int,
332	dspin_cmd_width,
333	dspin_rsp_width>(
334	"wt_fbuf",
335	x_width + y_width + l_width);
336
337	/////////////////////////////////////////////
338	bdev = new VciBlockDeviceTsar<vci_param_int>(
339	"bdev",
340	mtd,
341	IntTab(cluster_id, nb_procs + 1),
342	IntTab(cluster_id, tgtid_bdev),
343	disk_name,
344	block_size,
345	64); // burst size
346
347	wt_bdev = new VciDspinTargetWrapper<vci_param_int,
348	dspin_cmd_width,
349	dspin_rsp_width>(
350	"wt_bdev",
351	x_width + y_width + l_width);
352
353	wi_bdev = new VciDspinInitiatorWrapper<vci_param_int,
354	dspin_cmd_width,
355	dspin_rsp_width>(
356	"wi_bdev",
357	x_width + y_width + l_width);
358
359	int mac = 0xBEEF0000;
360	mnic = new VciMultiNic<vci_param_int>(
361	"mnic",
362	IntTab(cluster_id, tgtid_mnic),
363	mtd,
364	nic_channels,
365	nic_rx_name,
366	nic_tx_name,
367	mac, // mac_4 address
368	0xBABE ); // mac_2 address
369
370	wt_mnic = new VciDspinTargetWrapper<vci_param_int,
371	dspin_cmd_width,
372	dspin_rsp_width>(
373	"wt_mnic",
374	x_width + y_width + l_width);
375
376	/////////////////////////////////////////////
377	chbuf = new VciChbufDma<vci_param_int>(
378	"chbuf_dma",
379	mtd,
380	IntTab(cluster_id, nb_procs + 2),
381	IntTab(cluster_id, tgtid_chbuf),
382	64,
383	chbufdma_channels);
384
385	wt_chbuf = new VciDspinTargetWrapper<vci_param_int,
386	dspin_cmd_width,
387	dspin_rsp_width>(
388	"wt_chbuf",
389	x_width + y_width + l_width);
390
391	wi_chbuf = new VciDspinInitiatorWrapper<vci_param_int,
392	dspin_cmd_width,
393	dspin_rsp_width>(
394	"wi_chbuf",
395	x_width + y_width + l_width);
396
397	/////////////////////////////////////////////
398	std::vector<std::string> vect_names;
399	for (size_t tid = 0; tid < nb_ttys; tid++)
400	{
401	std::ostringstream term_name;
402	term_name << "term" << tid;
403	vect_names.push_back(term_name.str().c_str());
404	}
405	mtty = new VciMultiTty<vci_param_int>(
406	"mtty",
407	IntTab(cluster_id, tgtid_mtty),
408	mtd,
409	vect_names);
410
411	wt_mtty = new VciDspinTargetWrapper<vci_param_int,
412	dspin_cmd_width,
413	dspin_rsp_width>(
414	"wt_mtty",
415	x_width + y_width + l_width);
416
417	simhelper = new VciSimhelper<vci_param_int>(
418	"sim_helper",
419	IntTab(cluster_id, tgtid_simh),
420	mtd);
421
422	wt_simhelper = new VciDspinTargetWrapper<vci_param_int,
423	dspin_cmd_width,
424	dspin_rsp_width>(
425	"wt_simhelper",
426	x_width + y_width + l_width);
427	}
428
429	////////////////////////////////////
430	// Connections are defined here
431	////////////////////////////////////
432
433	//////////////////////// CMD ROUTER and RSP ROUTER
434	router_cmd->p_clk (this->p_clk);
435	router_cmd->p_resetn (this->p_resetn);
436	router_rsp->p_clk (this->p_clk);
437	router_rsp->p_resetn (this->p_resetn);
438
439	for (int i = 0; i < 4; i++)
440	{
441	for (int k = 0; k < 3; k++)
442	{
443	router_cmd->p_out[i][k] (this->p_cmd_out[i][k]);
444	router_cmd->p_in[i][k] (this->p_cmd_in[i][k]);
445	}
446
447	for (int k = 0; k < 2; k++)
448	{
449	router_rsp->p_out[i][k] (this->p_rsp_out[i][k]);
450	router_rsp->p_in[i][k] (this->p_rsp_in[i][k]);
451	}
452	}
453
454	router_cmd->p_out[4][0] (signal_dspin_cmd_g2l_d);
455	router_cmd->p_out[4][1] (signal_dspin_m2p_g2l_c);
456	router_cmd->p_out[4][2] (signal_dspin_clack_g2l_c);
457	router_cmd->p_in[4][0] (signal_dspin_cmd_l2g_d);
458	router_cmd->p_in[4][1] (signal_dspin_m2p_l2g_c);
459	router_cmd->p_in[4][2] (signal_dspin_clack_l2g_c);
460
461	router_rsp->p_out[4][0] (signal_dspin_rsp_g2l_d);
462	router_rsp->p_out[4][1] (signal_dspin_p2m_g2l_c);
463	router_rsp->p_in[4][0] (signal_dspin_rsp_l2g_d);
464	router_rsp->p_in[4][1] (signal_dspin_p2m_l2g_c);
465
466
467	std::cout << " - CMD & RSP routers connected" << std::endl;
468
469	///////////////////// CMD DSPIN local crossbar direct
470	xbar_cmd_d->p_clk (this->p_clk);
471	xbar_cmd_d->p_resetn (this->p_resetn);
472	xbar_cmd_d->p_global_out (signal_dspin_cmd_l2g_d);
473	xbar_cmd_d->p_global_in (signal_dspin_cmd_g2l_d);
474
475	xbar_cmd_d->p_local_out[tgtid_memc] (signal_dspin_cmd_memc_t);
476	xbar_cmd_d->p_local_out[tgtid_xicu] (signal_dspin_cmd_xicu_t);
477	xbar_cmd_d->p_local_out[tgtid_mdma] (signal_dspin_cmd_mdma_t);
478
479	xbar_cmd_d->p_local_in[nb_procs] (signal_dspin_cmd_mdma_i);
480
481	for (size_t p = 0; p < nb_procs; p++)
482	xbar_cmd_d->p_local_in[p] (signal_dspin_cmd_proc_i[p]);
483
484	if (io)
485	{
486	xbar_cmd_d->p_local_out[tgtid_mtty] (signal_dspin_cmd_mtty_t);
487	xbar_cmd_d->p_local_out[tgtid_brom] (signal_dspin_cmd_brom_t);
488	xbar_cmd_d->p_local_out[tgtid_bdev] (signal_dspin_cmd_bdev_t);
489	xbar_cmd_d->p_local_out[tgtid_fbuf] (signal_dspin_cmd_fbuf_t);
490	xbar_cmd_d->p_local_out[tgtid_mnic] (signal_dspin_cmd_mnic_t);
491	xbar_cmd_d->p_local_out[tgtid_chbuf] (signal_dspin_cmd_chbuf_t);
492	xbar_cmd_d->p_local_out[tgtid_simh] (signal_dspin_cmd_simh_t);
493
494	xbar_cmd_d->p_local_in[nb_procs + 1] (signal_dspin_cmd_bdev_i);
495	xbar_cmd_d->p_local_in[nb_procs + 2] (signal_dspin_cmd_chbuf_i);
496	}
497
498	std::cout << " - Command Direct crossbar connected" << std::endl;
499
500	//////////////////////// RSP DSPIN local crossbar direct
501	xbar_rsp_d->p_clk (this->p_clk);
502	xbar_rsp_d->p_resetn (this->p_resetn);
503	xbar_rsp_d->p_global_out (signal_dspin_rsp_l2g_d);
504	xbar_rsp_d->p_global_in (signal_dspin_rsp_g2l_d);
505
506	xbar_rsp_d->p_local_in[tgtid_memc] (signal_dspin_rsp_memc_t);
507	xbar_rsp_d->p_local_in[tgtid_xicu] (signal_dspin_rsp_xicu_t);
508	xbar_rsp_d->p_local_in[tgtid_mdma] (signal_dspin_rsp_mdma_t);
509
510	xbar_rsp_d->p_local_out[nb_procs] (signal_dspin_rsp_mdma_i);
511
512	for (size_t p = 0; p < nb_procs; p++)
513	xbar_rsp_d->p_local_out[p] (signal_dspin_rsp_proc_i[p]);
514
515	if (io)
516	{
517	xbar_rsp_d->p_local_in[tgtid_mtty] (signal_dspin_rsp_mtty_t);
518	xbar_rsp_d->p_local_in[tgtid_brom] (signal_dspin_rsp_brom_t);
519	xbar_rsp_d->p_local_in[tgtid_bdev] (signal_dspin_rsp_bdev_t);
520	xbar_rsp_d->p_local_in[tgtid_fbuf] (signal_dspin_rsp_fbuf_t);
521	xbar_rsp_d->p_local_in[tgtid_mnic] (signal_dspin_rsp_mnic_t);
522	xbar_rsp_d->p_local_in[tgtid_chbuf] (signal_dspin_rsp_chbuf_t);
523	xbar_rsp_d->p_local_in[tgtid_simh] (signal_dspin_rsp_simh_t);
524
525	xbar_rsp_d->p_local_out[nb_procs + 1] (signal_dspin_rsp_bdev_i);
526	xbar_rsp_d->p_local_out[nb_procs + 2] (signal_dspin_rsp_chbuf_i);
527	}
528
529	std::cout << " - Response Direct crossbar connected" << std::endl;
530
531	////////////////////// M2P DSPIN local crossbar coherence
532	xbar_m2p_c->p_clk (this->p_clk);
533	xbar_m2p_c->p_resetn (this->p_resetn);
534	xbar_m2p_c->p_global_out (signal_dspin_m2p_l2g_c);
535	xbar_m2p_c->p_global_in (signal_dspin_m2p_g2l_c);
536	xbar_m2p_c->p_local_in[0] (signal_dspin_m2p_memc);
537	for (size_t p = 0; p < nb_procs; p++)
538	xbar_m2p_c->p_local_out[p] (signal_dspin_m2p_proc[p]);
539
540	std::cout << " - M2P Coherence crossbar connected" << std::endl;
541
542	////////////////////// CLACK DSPIN local crossbar coherence
543	xbar_clack_c->p_clk (this->p_clk);
544	xbar_clack_c->p_resetn (this->p_resetn);
545	xbar_clack_c->p_global_out (signal_dspin_clack_l2g_c);
546	xbar_clack_c->p_global_in (signal_dspin_clack_g2l_c);
547	xbar_clack_c->p_local_in[0] (signal_dspin_clack_memc);
548	for (size_t p = 0; p < nb_procs; p++)
549	xbar_clack_c->p_local_out[p] (signal_dspin_clack_proc[p]);
550
551	std::cout << " - Clack Coherence crossbar connected" << std::endl;
552
553	////////////////////////// P2M DSPIN local crossbar coherence
554	xbar_p2m_c->p_clk (this->p_clk);
555	xbar_p2m_c->p_resetn (this->p_resetn);
556	xbar_p2m_c->p_global_out (signal_dspin_p2m_l2g_c);
557	xbar_p2m_c->p_global_in (signal_dspin_p2m_g2l_c);
558	xbar_p2m_c->p_local_out[0] (signal_dspin_p2m_memc);
559	for (size_t p = 0; p < nb_procs; p++)
560	xbar_p2m_c->p_local_in[p] (signal_dspin_p2m_proc[p]);
561
562	std::cout << " - P2M Coherence crossbar connected" << std::endl;
563
564
565	//////////////////////////////////// Processors
566	for (size_t p = 0; p < nb_procs; p++)
567	{
568	proc[p]->p_clk (this->p_clk);
569	proc[p]->p_resetn (this->p_resetn);
570	proc[p]->p_vci (signal_vci_ini_proc[p]);
571	proc[p]->p_dspin_m2p (signal_dspin_m2p_proc[p]);
572	proc[p]->p_dspin_p2m (signal_dspin_p2m_proc[p]);
573	proc[p]->p_dspin_clack (signal_dspin_clack_proc[p]);
574	proc[p]->p_irq[0] (signal_proc_it[p]);
575	for ( size_t j = 1 ; j < 6 ; j++)
576	{
577	proc[p]->p_irq[j] (signal_false);
578	}
579
580	wi_proc[p]->p_clk (this->p_clk);
581	wi_proc[p]->p_resetn (this->p_resetn);
582	wi_proc[p]->p_dspin_cmd (signal_dspin_cmd_proc_i[p]);
583	wi_proc[p]->p_dspin_rsp (signal_dspin_rsp_proc_i[p]);
584	wi_proc[p]->p_vci (signal_vci_ini_proc[p]);
585	}
586
587	std::cout << " - Processors connected" << std::endl;
588
589	///////////////////////////////////// XICU
590	xicu->p_clk (this->p_clk);
591	xicu->p_resetn (this->p_resetn);
592	xicu->p_vci (signal_vci_tgt_xicu);
593	for (size_t p = 0; p < nb_procs; p++)
594	{
595	xicu->p_irq[p] (signal_proc_it[p]);
596	}
597	for (size_t i = 0; i < 32; i++)
598	{
599	if (io) // I/O cluster
600	{
601	if (i < 8) xicu->p_hwi[i] (signal_false);
602	else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i - 8]);
603	else if (i < 16) xicu->p_hwi[i] (signal_false);
604	else if (i < (16 + nb_ttys)) xicu->p_hwi[i] (signal_irq_mtty[i - 16]);
605	else if (i < 31) xicu->p_hwi[i] (signal_false);
606	else xicu->p_hwi[i] (signal_irq_bdev);
607	}
608	else // other clusters
609	{
610	if (i < 8) xicu->p_hwi[i] (signal_false);
611	else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i - 8]);
612	else xicu->p_hwi[i] (signal_false);
613	}
614	}
615
616	// wrapper XICU
617	wt_xicu->p_clk (this->p_clk);
618	wt_xicu->p_resetn (this->p_resetn);
619	wt_xicu->p_dspin_cmd (signal_dspin_cmd_xicu_t);
620	wt_xicu->p_dspin_rsp (signal_dspin_rsp_xicu_t);
621	wt_xicu->p_vci (signal_vci_tgt_xicu);
622
623	std::cout << " - XICU connected" << std::endl;
624
625	//////////////////////////////////////////////// MEMC
626	memc->p_clk (this->p_clk);
627	memc->p_resetn (this->p_resetn);
628	memc->p_vci_ixr (signal_vci_xram);
629	memc->p_vci_tgt (signal_vci_tgt_memc);
630	memc->p_dspin_p2m (signal_dspin_p2m_memc);
631	memc->p_dspin_m2p (signal_dspin_m2p_memc);
632	memc->p_dspin_clack (signal_dspin_clack_memc);
633
634	// wrapper MEMC
635	wt_memc->p_clk (this->p_clk);
636	wt_memc->p_resetn (this->p_resetn);
637	wt_memc->p_dspin_cmd (signal_dspin_cmd_memc_t);
638	wt_memc->p_dspin_rsp (signal_dspin_rsp_memc_t);
639	wt_memc->p_vci (signal_vci_tgt_memc);
640
641	std::cout << " - MEMC connected" << std::endl;
642
643	/////////////////////////////////////////////// XRAM
644	xram->p_clk (this->p_clk);
645	xram->p_resetn (this->p_resetn);
646	xram->p_vci (signal_vci_xram);
647
648	std::cout << " - XRAM connected" << std::endl;
649
650	////////////////////////////////////////////// MDMA
651	mdma->p_clk (this->p_clk);
652	mdma->p_resetn (this->p_resetn);
653	mdma->p_vci_target (signal_vci_tgt_mdma);
654	mdma->p_vci_initiator (signal_vci_ini_mdma);
655	for (size_t i = 0; i < nb_dmas; i++)
656	mdma->p_irq[i] (signal_irq_mdma[i]);
657
658	// wrapper tgt MDMA
659	wt_mdma->p_clk (this->p_clk);
660	wt_mdma->p_resetn (this->p_resetn);
661	wt_mdma->p_dspin_cmd (signal_dspin_cmd_mdma_t);
662	wt_mdma->p_dspin_rsp (signal_dspin_rsp_mdma_t);
663	wt_mdma->p_vci (signal_vci_tgt_mdma);
664
665	// wrapper ini MDMA
666	wi_mdma->p_clk (this->p_clk);
667	wi_mdma->p_resetn (this->p_resetn);
668	wi_mdma->p_dspin_cmd (signal_dspin_cmd_mdma_i);
669	wi_mdma->p_dspin_rsp (signal_dspin_rsp_mdma_i);
670	wi_mdma->p_vci (signal_vci_ini_mdma);
671
672	std::cout << " - MDMA connected" << std::endl;
673
674	/////////////////////////////// Components in I/O cluster
675
676	if (io)
677	{
678	// BDEV
679	bdev->p_clk (this->p_clk);
680	bdev->p_resetn (this->p_resetn);
681	bdev->p_irq (signal_irq_bdev);
682	bdev->p_vci_target (signal_vci_tgt_bdev);
683	bdev->p_vci_initiator (signal_vci_ini_bdev);
684
685	// wrapper tgt BDEV
686	wt_bdev->p_clk (this->p_clk);
687	wt_bdev->p_resetn (this->p_resetn);
688	wt_bdev->p_dspin_cmd (signal_dspin_cmd_bdev_t);
689	wt_bdev->p_dspin_rsp (signal_dspin_rsp_bdev_t);
690	wt_bdev->p_vci (signal_vci_tgt_bdev);
691
692	// wrapper ini BDEV
693	wi_bdev->p_clk (this->p_clk);
694	wi_bdev->p_resetn (this->p_resetn);
695	wi_bdev->p_dspin_cmd (signal_dspin_cmd_bdev_i);
696	wi_bdev->p_dspin_rsp (signal_dspin_rsp_bdev_i);
697	wi_bdev->p_vci (signal_vci_ini_bdev);
698
699	std::cout << " - BDEV connected" << std::endl;
700
701	// FBUF
702	fbuf->p_clk (this->p_clk);
703	fbuf->p_resetn (this->p_resetn);
704	fbuf->p_vci (signal_vci_tgt_fbuf);
705
706	// wrapper tgt FBUF
707	wt_fbuf->p_clk (this->p_clk);
708	wt_fbuf->p_resetn (this->p_resetn);
709	wt_fbuf->p_dspin_cmd (signal_dspin_cmd_fbuf_t);
710	wt_fbuf->p_dspin_rsp (signal_dspin_rsp_fbuf_t);
711	wt_fbuf->p_vci (signal_vci_tgt_fbuf);
712
713	std::cout << " - FBUF connected" << std::endl;
714
715	// MNIC
716	mnic->p_clk (this->p_clk);
717	mnic->p_resetn (this->p_resetn);
718	mnic->p_vci (signal_vci_tgt_mnic);
719	for (size_t i = 0; i < nic_channels; i++)
720	{
721	mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]);
722	mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]);
723	}
724
725	// wrapper tgt MNIC
726	wt_mnic->p_clk (this->p_clk);
727	wt_mnic->p_resetn (this->p_resetn);
728	wt_mnic->p_dspin_cmd (signal_dspin_cmd_mnic_t);
729	wt_mnic->p_dspin_rsp (signal_dspin_rsp_mnic_t);
730	wt_mnic->p_vci (signal_vci_tgt_mnic);
731
732	std::cout << " - MNIC connected" << std::endl;
733
734	// CHBUF
735	chbuf->p_clk (this->p_clk);
736	chbuf->p_resetn (this->p_resetn);
737	chbuf->p_vci_target (signal_vci_tgt_chbuf);
738	chbuf->p_vci_initiator (signal_vci_ini_chbuf);
739	for (size_t i = 0; i < chbufdma_channels; i++)
740	{
741	chbuf->p_irq[i] (signal_irq_chbuf[i]);
742	}
743
744	// wrapper tgt CHBUF
745	wt_chbuf->p_clk (this->p_clk);
746	wt_chbuf->p_resetn (this->p_resetn);
747	wt_chbuf->p_dspin_cmd (signal_dspin_cmd_chbuf_t);
748	wt_chbuf->p_dspin_rsp (signal_dspin_rsp_chbuf_t);
749	wt_chbuf->p_vci (signal_vci_tgt_chbuf);
750
751	// wrapper ini CHBUF
752	wi_chbuf->p_clk (this->p_clk);
753	wi_chbuf->p_resetn (this->p_resetn);
754	wi_chbuf->p_dspin_cmd (signal_dspin_cmd_chbuf_i);
755	wi_chbuf->p_dspin_rsp (signal_dspin_rsp_chbuf_i);
756	wi_chbuf->p_vci (signal_vci_ini_chbuf);
757
758	std::cout << " - CHBUF connected" << std::endl;
759
760	// BROM
761	brom->p_clk (this->p_clk);
762	brom->p_resetn (this->p_resetn);
763	brom->p_vci (signal_vci_tgt_brom);
764
765	// wrapper tgt BROM
766	wt_brom->p_clk (this->p_clk);
767	wt_brom->p_resetn (this->p_resetn);
768	wt_brom->p_dspin_cmd (signal_dspin_cmd_brom_t);
769	wt_brom->p_dspin_rsp (signal_dspin_rsp_brom_t);
770	wt_brom->p_vci (signal_vci_tgt_brom);
771
772	std::cout << " - BROM connected" << std::endl;
773
774	// MTTY
775	mtty->p_clk (this->p_clk);
776	mtty->p_resetn (this->p_resetn);
777	mtty->p_vci (signal_vci_tgt_mtty);
778	for (size_t i = 0; i < nb_ttys; i++)
779	{
780	mtty->p_irq[i] (signal_irq_mtty[i]);
781	}
782
783	// wrapper tgt MTTY
784	wt_mtty->p_clk (this->p_clk);
785	wt_mtty->p_resetn (this->p_resetn);
786	wt_mtty->p_dspin_cmd (signal_dspin_cmd_mtty_t);
787	wt_mtty->p_dspin_rsp (signal_dspin_rsp_mtty_t);
788	wt_mtty->p_vci (signal_vci_tgt_mtty);
789
790
791	// Sim Helper
792	simhelper->p_clk (this->p_clk);
793	simhelper->p_resetn (this->p_resetn);
794	simhelper->p_vci (signal_vci_tgt_simh);
795
796	// wrapper tgt Sim Helper
797	wt_simhelper->p_clk (this->p_clk);
798	wt_simhelper->p_resetn (this->p_resetn);
799	wt_simhelper->p_dspin_cmd (signal_dspin_cmd_simh_t);
800	wt_simhelper->p_dspin_rsp (signal_dspin_rsp_simh_t);
801	wt_simhelper->p_vci (signal_vci_tgt_simh);
802
803	std::cout << " - MTTY connected" << std::endl;
804	}
805	} // end constructor
806
807
808
809	template<size_t dspin_cmd_width,
810	size_t dspin_rsp_width,
811	typename vci_param_int,
812	typename vci_param_ext> TsarXbarCluster<dspin_cmd_width,
813	dspin_rsp_width,
814	vci_param_int,
815	vci_param_ext>::~TsarXbarCluster() {
816
817	dealloc_elems<DspinInput<dspin_cmd_width> > (p_cmd_in, 4, 3);
818	dealloc_elems<DspinOutput<dspin_cmd_width> >(p_cmd_out, 4, 3);
819	dealloc_elems<DspinInput<dspin_rsp_width> > (p_rsp_in, 4, 2);
820	dealloc_elems<DspinOutput<dspin_rsp_width> >(p_rsp_out, 4, 2);
821
822	for (size_t p = 0; p < n_procs; p++)
823	{
824	delete proc[p];
825	delete wi_proc[p];
826	}
827
828	delete memc;
829	delete wt_memc;
830	delete xram;
831	delete xicu;
832	delete wt_xicu;
833	delete mdma;
834	delete wt_mdma;
835	delete wi_mdma;
836	delete xbar_cmd_d;
837	delete xbar_rsp_d;
838	delete xbar_m2p_c;
839	delete xbar_p2m_c;
840	delete xbar_clack_c;
841	delete router_cmd;
842	delete router_rsp;
843	if (brom != NULL)
844	{
845	delete brom;
846	delete wt_brom;
847	delete fbuf;
848	delete wt_fbuf;
849	delete bdev;
850	delete wt_bdev;
851	delete wi_bdev;
852	delete mnic;
853	delete wt_mnic;
854	delete chbuf;
855	delete wt_chbuf;
856	delete wi_chbuf;
857	delete mtty;
858	delete wt_mtty;
859	delete simhelper;
860	delete wt_simhelper;
861	}
862	}
863
864
865	}}
866
867	// Local Variables:
868	// tab-width: 4
869	// c-basic-offset: 4
870	// c-file-offsets:((innamespace . 0)(inline-open . 0))
871	// indent-tabs-mode: nil
872	// End:
873
874	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
875
876
877

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Project-Id-Version: Trac 0.12
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PO-Revision-Date: 2010-07-19 23:05+0200
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