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source: trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp @ 836

Last change on this file since 836 was 836, checked in by meunier, 10 years ago

Trunk:

Cosmetic in mem_cache_directory.h and xram_transaction.h
Renamed mem_cache param dspin_in_width and dspin_out_width to memc_dspin_in_width and memc_dspin_out_width (because of a bug in soclib-cc ?). Should have updated these names in the .sd or .py files of all platforms
Updated the scripts for tsar_generic_xbar to take into account the ideal write-through + added a graph in create_graphs.py

File size: 30.5 KB

Line
1	//////////////////////////////////////////////////////////////////////////////
2	// File: tsar_xbar_cluster.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : march 2011
6	// This program is released under the GNU public license
7	//////////////////////////////////////////////////////////////////////////////
8	// This file define a TSAR cluster architecture with virtual memory:
9	// - It uses two virtual_dspin_router as distributed global interconnect
10	// - It uses four dspin_local_crossbar as local interconnect
11	// - It uses the vci_cc_vcache_wrapper
12	// - It uses the vci_mem_cache
13	// - It contains a private RAM with a variable latency to emulate the L3 cache
14	// - It can contains 1, 2 or 4 processors
15	// - Each processor has a private dma channel (vci_multi_dma)
16	// - It uses the vci_xicu interrupt controller
17	// - The peripherals MTTY, BDEV, FBUF, MNIC and BROM are in cluster (0,0)
18	// - The Multi-TTY component controls up to 15 terminals.
19	// - Each Multi-DMA component controls up to 8 DMA channels.
20	// - The DMA IRQs are connected to IRQ_IN[8]...IRQ_IN[15]
21	// - The TTY IRQs are connected to IRQ_IN[16]...IRQ_IN[30]
22	// - The BDEV IRQ is connected to IRQ_IN[31]
23	//////////////////////////////////////////////////////////////////////////////////
24
25	#include "../include/tsar_xbar_cluster.h"
26
27
28	namespace soclib {
29	namespace caba {
30
31	////////////////////////////////////////////////////////////////////////////////////
32	template<size_t dspin_cmd_width,
33	size_t dspin_rsp_width,
34	typename vci_param_int,
35	typename vci_param_ext> TsarXbarCluster<dspin_cmd_width,
36	dspin_rsp_width,
37	vci_param_int,
38	vci_param_ext>::TsarXbarCluster(
39	////////////////////////////////////////////////////////////////////////////////////
40	sc_module_name insname,
41	size_t nb_procs,
42	size_t nb_ttys,
43	size_t nb_dmas,
44	size_t x_id,
45	size_t y_id,
46	size_t cluster_id,
47	const soclib::common::MappingTable &mtd,
48	const soclib::common::MappingTable &mtx,
49	size_t x_width,
50	size_t y_width,
51	size_t l_width,
52	size_t tgtid_memc,
53	size_t tgtid_xicu,
54	size_t tgtid_mdma,
55	size_t tgtid_fbuf,
56	size_t tgtid_mtty,
57	size_t tgtid_brom,
58	size_t tgtid_mnic,
59	size_t tgtid_chbuf,
60	size_t tgtid_bdev,
61	size_t tgtid_simh,
62	size_t memc_ways,
63	size_t memc_sets,
64	size_t l1_i_ways,
65	size_t l1_i_sets,
66	size_t l1_d_ways,
67	size_t l1_d_sets,
68	size_t irq_per_processor,
69	size_t xram_latency,
70	bool io,
71	size_t xfb,
72	size_t yfb,
73	char* disk_name,
74	size_t block_size,
75	size_t nic_channels,
76	char* nic_rx_name,
77	char* nic_tx_name,
78	uint32_t nic_timeout,
79	size_t chbufdma_channels,
80	const Loader & loader,
81	uint32_t frozen_cycles,
82	uint32_t debug_start_cycle,
83	bool memc_debug_ok,
84	bool proc_debug_ok)
85	: soclib::caba::BaseModule(insname),
86	p_clk("clk"),
87	p_resetn("resetn")
88
89	{
90
91	n_procs = nb_procs;
92
93	// Vectors of ports definition
94	p_cmd_in = alloc_elems<DspinInput<dspin_cmd_width> > ("p_cmd_in", 4, 3);
95	p_cmd_out = alloc_elems<DspinOutput<dspin_cmd_width> > ("p_cmd_out", 4, 3);
96	p_rsp_in = alloc_elems<DspinInput<dspin_rsp_width> > ("p_rsp_in", 4, 2);
97	p_rsp_out = alloc_elems<DspinOutput<dspin_rsp_width> > ("p_rsp_out", 4, 2);
98
99	/////////////////////////////////////////////////////////////////////////////
100	// Components definition
101	/////////////////////////////////////////////////////////////////////////////
102
103	for (size_t p = 0; p < nb_procs; p++)
104	{
105	std::ostringstream sproc;
106	sproc << "proc_" << x_id << "_" << y_id << "_" << p;
107	proc[p] = new VciCcVCacheWrapper<vci_param_int,
108	dspin_cmd_width,
109	dspin_rsp_width,
110	GdbServer<Mips32ElIss> >(
111	sproc.str().c_str(),
112	cluster_id * nb_procs + p, // GLOBAL PROC_ID
113	mtd, // Mapping Table
114	IntTab(cluster_id,p), // SRCID
115	(cluster_id << l_width) + p, // CC_GLOBAL_ID
116	8, // ITLB ways
117	8, // ITLB sets
118	8, // DTLB ways
119	8, // DTLB sets
120	l1_i_ways,l1_i_sets, 16, // ICACHE size
121	l1_d_ways,l1_d_sets, 16, // DCACHE size
122	4, // WBUF nlines
123	4, // WBUF nwords
124	x_width,
125	y_width,
126	frozen_cycles, // max frozen cycles
127	debug_start_cycle,
128	proc_debug_ok);
129
130	}
131
132	/////////////////////////////////////////////////////////////////////////////
133	std::ostringstream smemc;
134	smemc << "memc_" << x_id << "_" << y_id;
135	memc = new VciMemCache<vci_param_int,
136	vci_param_ext,
137	dspin_rsp_width,
138	dspin_cmd_width>(
139	smemc.str().c_str(),
140	mtd, // Mapping Table direct space
141	mtx, // Mapping Table external space
142	IntTab(cluster_id), // SRCID external space
143	IntTab(cluster_id, tgtid_memc), // TGTID direct space
144	x_width, // Number of x bits in platform
145	y_width, // Number of y bits in platform
146	memc_ways, memc_sets, 16, // CACHE SIZE
147	3, // MAX NUMBER OF COPIES
148	4096, // HEAP SIZE
149	8, // TRANSACTION TABLE DEPTH
150	8, // UPDATE TABLE DEPTH
151	8, // INVALIDATE TABLE DEPTH
152	debug_start_cycle,
153	memc_debug_ok);
154
155
156	/////////////////////////////////////////////////////////////////////////////
157	std::ostringstream sxram;
158	sxram << "xram_" << x_id << "_" << y_id;
159	xram = new VciSimpleRam<vci_param_ext>(
160	sxram.str().c_str(),
161	IntTab(cluster_id),
162	mtx,
163	loader,
164	xram_latency);
165
166	/////////////////////////////////////////////////////////////////////////////
167	std::ostringstream sxicu;
168	sxicu << "xicu_" << x_id << "_" << y_id;
169	xicu = new VciXicu<vci_param_int>(
170	sxicu.str().c_str(),
171	mtd, // mapping table
172	IntTab(cluster_id, tgtid_xicu), // TGTID_D
173	nb_procs, // number of timer IRQs
174	32, // number of hard IRQs
175	32, // number of soft IRQs
176	nb_procs*irq_per_processor); // number of output IRQs
177
178
179	/////////////////////////////////////////////////////////////////////////////
180	std::ostringstream smdma;
181	smdma << "mdma_" << x_id << "_" << y_id;
182	mdma = new VciMultiDma<vci_param_int>(
183	smdma.str().c_str(),
184	mtd,
185	IntTab(cluster_id, nb_procs), // SRCID
186	IntTab(cluster_id, tgtid_mdma), // TGTID
187	64, // burst size
188	nb_dmas); // number of IRQs
189
190
191	/////////////////////////////////////////////////////////////////////////////
192	size_t nb_direct_initiators = nb_procs + 1;
193	size_t nb_direct_targets = 3;
194	if (io)
195	{
196	nb_direct_initiators = nb_procs + 3;
197	nb_direct_targets = 10;
198	}
199
200	std::ostringstream sxbar;
201	sxbar << "xbar_" << x_id << "_" << y_id;
202	xbar_d = new VciLocalCrossbar<vci_param_int>(
203	sxbar.str().c_str(),
204	mtd, // mapping table
205	//x_id, y_id, // cluster coordinates
206	cluster_id,
207	nb_direct_initiators, // number of local of sources
208	nb_direct_targets, // number of local dests
209	tgtid_memc); // Default target
210
211	////////////// vci_dspin wrappers
212	std::ostringstream swtxbar;
213	swtxbar << "wt_xbar_" << x_id << "_" << y_id;
214	wt_xbar_d = new VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>(
215	swtxbar.str().c_str(),
216	x_width + y_width + l_width);
217
218	std::ostringstream swixbar;
219	swixbar << "wi_xbar_" << x_id << "_" << y_id;
220	wi_xbar_d = new VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>(
221	swixbar.str().c_str(),
222	x_width + y_width + l_width );
223
224	/////////////////////////////////////////////////////////////////////////////
225	xbar_m2p_c = new DspinLocalCrossbar<dspin_cmd_width>(
226	"xbar_m2p_c",
227	mtd, // mapping table
228	x_id, y_id, // cluster coordinates
229	x_width, y_width, l_width,
230	1, // number of local sources
231	nb_procs, // number of local targets
232	2, 2, // fifo depths
233	true, // CMD
234	false, // don't use local routing table
235	true ); // broadcast
236
237	/////////////////////////////////////////////////////////////////////////////
238	xbar_p2m_c = new DspinLocalCrossbar<dspin_rsp_width>(
239	"xbar_p2m_c",
240	mtd, // mapping table
241	x_id, y_id, // cluster coordinates
242	x_width, y_width, 0, // l_width unused on p2m network
243	nb_procs, // number of local sources
244	1, // number of local dests
245	2, 2, // fifo depths
246	false, // RSP
247	false, // don't use local routing table
248	false ); // no broadcast
249
250	/////////////////////////////////////////////////////////////////////////////
251	xbar_clack_c = new DspinLocalCrossbar<dspin_cmd_width>(
252	"xbar_clack_c",
253	mtd, // mapping table
254	x_id, y_id, // cluster coordinates
255	x_width, y_width, l_width,
256	1, // number of local sources
257	nb_procs, // number of local targets
258	1, 1, // fifo depths
259	true, // CMD
260	false, // don't use local routing table
261	false); // broadcast
262
263	/////////////////////////////////////////////////////////////////////////////
264	router_cmd = new VirtualDspinRouter<dspin_cmd_width>(
265	"router_cmd",
266	x_id,y_id, // coordinate in the mesh
267	x_width, y_width, // x & y fields width
268	3, // nb virtual channels
269	4,4); // input & output fifo depths
270
271	/////////////////////////////////////////////////////////////////////////////
272	router_rsp = new VirtualDspinRouter<dspin_rsp_width>(
273	"router_rsp",
274	x_id,y_id, // coordinates in mesh
275	x_width, y_width, // x & y fields width
276	2, // nb virtual channels
277	4,4); // input & output fifo depths
278
279	// IO cluster components
280	if (io)
281	{
282	/////////////////////////////////////////////
283	brom = new VciSimpleRom<vci_param_int>(
284	"brom",
285	IntTab(cluster_id, tgtid_brom),
286	mtd,
287	loader);
288
289	/////////////////////////////////////////////
290	fbuf = new VciFrameBuffer<vci_param_int>(
291	"fbuf",
292	IntTab(cluster_id, tgtid_fbuf),
293	mtd,
294	xfb, yfb);
295
296	/////////////////////////////////////////////
297	bdev = new VciBlockDeviceTsar<vci_param_int>(
298	"bdev",
299	mtd,
300	IntTab(cluster_id, nb_procs + 1),
301	IntTab(cluster_id, tgtid_bdev),
302	disk_name,
303	block_size,
304	64); // burst size
305
306	int mac = 0xBEEF0000;
307	mnic = new VciMultiNic<vci_param_int>(
308	"mnic",
309	IntTab(cluster_id, tgtid_mnic),
310	mtd,
311	nic_channels,
312	mac, // mac_4 address
313	0xBABE, // mac_2 address
314	nic_rx_name,
315	nic_tx_name);
316
317
318
319	/////////////////////////////////////////////
320	chbuf = new VciChbufDma<vci_param_int>(
321	"chbuf_dma",
322	mtd,
323	IntTab(cluster_id, nb_procs + 2),
324	IntTab(cluster_id, tgtid_chbuf),
325	64,
326	chbufdma_channels);
327
328	/////////////////////////////////////////////
329	std::vector<std::string> vect_names;
330	for (size_t tid = 0; tid < nb_ttys; tid++)
331	{
332	std::ostringstream term_name;
333	term_name << "term" << tid;
334	vect_names.push_back(term_name.str().c_str());
335	}
336	mtty = new VciMultiTty<vci_param_int>(
337	"mtty",
338	IntTab(cluster_id, tgtid_mtty),
339	mtd,
340	vect_names);
341
342	simhelper = new VciSimhelper<vci_param_int>(
343	"sim_helper",
344	IntTab(cluster_id, tgtid_simh),
345	mtd);
346	}
347
348	////////////////////////////////////
349	// Connections are defined here
350	////////////////////////////////////
351
352	//////////////////////// CMD ROUTER and RSP ROUTER
353	router_cmd->p_clk (this->p_clk);
354	router_cmd->p_resetn (this->p_resetn);
355	router_rsp->p_clk (this->p_clk);
356	router_rsp->p_resetn (this->p_resetn);
357
358	for (int i = 0; i < 4; i++)
359	{
360	for (int k = 0; k < 3; k++)
361	{
362	router_cmd->p_out[i][k] (this->p_cmd_out[i][k]);
363	router_cmd->p_in[i][k] (this->p_cmd_in[i][k]);
364	}
365
366	for (int k = 0; k < 2; k++)
367	{
368	router_rsp->p_out[i][k] (this->p_rsp_out[i][k]);
369	router_rsp->p_in[i][k] (this->p_rsp_in[i][k]);
370	}
371	}
372
373	router_cmd->p_out[4][0] (signal_dspin_cmd_g2l_d);
374	router_cmd->p_out[4][1] (signal_dspin_m2p_g2l_c);
375	router_cmd->p_out[4][2] (signal_dspin_clack_g2l_c);
376	router_cmd->p_in[4][0] (signal_dspin_cmd_l2g_d);
377	router_cmd->p_in[4][1] (signal_dspin_m2p_l2g_c);
378	router_cmd->p_in[4][2] (signal_dspin_clack_l2g_c);
379
380	router_rsp->p_out[4][0] (signal_dspin_rsp_g2l_d);
381	router_rsp->p_out[4][1] (signal_dspin_p2m_g2l_c);
382	router_rsp->p_in[4][0] (signal_dspin_rsp_l2g_d);
383	router_rsp->p_in[4][1] (signal_dspin_p2m_l2g_c);
384
385
386	std::cout << " - CMD & RSP routers connected" << std::endl;
387
388	wi_xbar_d->p_clk (this->p_clk);
389	wi_xbar_d->p_resetn (this->p_resetn);
390	wi_xbar_d->p_vci (signal_vci_l2g_d);
391	wi_xbar_d->p_dspin_cmd (signal_dspin_cmd_l2g_d);
392	wi_xbar_d->p_dspin_rsp (signal_dspin_rsp_g2l_d);
393
394	std::cout << " - Wrapper Ini VCI2DSPIN Direct connected" << std::endl;
395
396	wt_xbar_d->p_clk (this->p_clk);
397	wt_xbar_d->p_resetn (this->p_resetn);
398	wt_xbar_d->p_vci (signal_vci_g2l_d);
399	wt_xbar_d->p_dspin_cmd (signal_dspin_cmd_g2l_d);
400	wt_xbar_d->p_dspin_rsp (signal_dspin_rsp_l2g_d);
401
402	std::cout << " - Wrapper Tgt VCI2DSPIN Direct connected" << std::endl;
403
404	///////////////////// CMD VCI local crossbar direct
405	xbar_d->p_clk (this->p_clk);
406	xbar_d->p_resetn (this->p_resetn);
407	xbar_d->p_target_to_up (signal_vci_g2l_d);
408	xbar_d->p_initiator_to_up (signal_vci_l2g_d);
409
410	xbar_d->p_to_target[tgtid_memc] (signal_vci_tgt_memc);
411	xbar_d->p_to_target[tgtid_xicu] (signal_vci_tgt_xicu);
412	xbar_d->p_to_target[tgtid_mdma] (signal_vci_tgt_mdma);
413
414	xbar_d->p_to_initiator[nb_procs] (signal_vci_ini_mdma);
415
416	for (size_t p = 0; p < nb_procs; p++)
417	xbar_d->p_to_initiator[p] (signal_vci_ini_proc[p]);
418
419	if (io)
420	{
421	xbar_d->p_to_target[tgtid_mtty] (signal_vci_tgt_mtty);
422	xbar_d->p_to_target[tgtid_brom] (signal_vci_tgt_brom);
423	xbar_d->p_to_target[tgtid_bdev] (signal_vci_tgt_bdev);
424	xbar_d->p_to_target[tgtid_fbuf] (signal_vci_tgt_fbuf);
425	xbar_d->p_to_target[tgtid_mnic] (signal_vci_tgt_mnic);
426	xbar_d->p_to_target[tgtid_chbuf] (signal_vci_tgt_chbuf);
427	xbar_d->p_to_target[tgtid_simh] (signal_vci_tgt_simh);
428
429	xbar_d->p_to_initiator[nb_procs + 1] (signal_vci_ini_bdev);
430	xbar_d->p_to_initiator[nb_procs + 2] (signal_vci_ini_chbuf);
431	}
432
433	std::cout << " - Direct crossbar connected" << std::endl;
434
435	////////////////////// M2P DSPIN local crossbar coherence
436	xbar_m2p_c->p_clk (this->p_clk);
437	xbar_m2p_c->p_resetn (this->p_resetn);
438	xbar_m2p_c->p_global_out (signal_dspin_m2p_l2g_c);
439	xbar_m2p_c->p_global_in (signal_dspin_m2p_g2l_c);
440	xbar_m2p_c->p_local_in[0] (signal_dspin_m2p_memc);
441	for (size_t p = 0; p < nb_procs; p++)
442	xbar_m2p_c->p_local_out[p] (signal_dspin_m2p_proc[p]);
443
444	std::cout << " - M2P Coherence crossbar connected" << std::endl;
445
446	////////////////////// CLACK DSPIN local crossbar coherence
447	xbar_clack_c->p_clk (this->p_clk);
448	xbar_clack_c->p_resetn (this->p_resetn);
449	xbar_clack_c->p_global_out (signal_dspin_clack_l2g_c);
450	xbar_clack_c->p_global_in (signal_dspin_clack_g2l_c);
451	xbar_clack_c->p_local_in[0] (signal_dspin_clack_memc);
452	for (size_t p = 0; p < nb_procs; p++)
453	xbar_clack_c->p_local_out[p] (signal_dspin_clack_proc[p]);
454
455	std::cout << " - Clack Coherence crossbar connected" << std::endl;
456
457	////////////////////////// P2M DSPIN local crossbar coherence
458	xbar_p2m_c->p_clk (this->p_clk);
459	xbar_p2m_c->p_resetn (this->p_resetn);
460	xbar_p2m_c->p_global_out (signal_dspin_p2m_l2g_c);
461	xbar_p2m_c->p_global_in (signal_dspin_p2m_g2l_c);
462	xbar_p2m_c->p_local_out[0] (signal_dspin_p2m_memc);
463	for (size_t p = 0; p < nb_procs; p++)
464	xbar_p2m_c->p_local_in[p] (signal_dspin_p2m_proc[p]);
465
466	std::cout << " - P2M Coherence crossbar connected" << std::endl;
467
468
469	//////////////////////////////////// Processors
470	for (size_t p = 0; p < nb_procs; p++)
471	{
472	proc[p]->p_clk (this->p_clk);
473	proc[p]->p_resetn (this->p_resetn);
474	proc[p]->p_vci (signal_vci_ini_proc[p]);
475	proc[p]->p_dspin_m2p (signal_dspin_m2p_proc[p]);
476	proc[p]->p_dspin_p2m (signal_dspin_p2m_proc[p]);
477	proc[p]->p_dspin_clack (signal_dspin_clack_proc[p]);
478
479	for ( size_t i = 0; i < irq_per_processor; i++)
480	{
481	proc[p]->p_irq[i] (signal_proc_it[p*irq_per_processor + i]);
482	}
483	for ( size_t j = irq_per_processor; j < 6; j++) // 6 = number of irqs in the MIPS
484	{
485	proc[p]->p_irq[j] (signal_false);
486	}
487
488	}
489
490	std::cout << " - Processors connected" << std::endl;
491
492	///////////////////////////////////// XICU
493	xicu->p_clk (this->p_clk);
494	xicu->p_resetn (this->p_resetn);
495	xicu->p_vci (signal_vci_tgt_xicu);
496	for (size_t p = 0; p < nb_procs * irq_per_processor; p++)
497	{
498	xicu->p_irq[p] (signal_proc_it[p]);
499	}
500	for (size_t i = 0; i < 32; i++)
501	{
502	if (io) // I/O cluster
503	{
504	if (i < 8) xicu->p_hwi[i] (signal_false);
505	else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i - 8]);
506	else if (i < 16) xicu->p_hwi[i] (signal_false);
507	else if (i < (16 + nb_ttys)) xicu->p_hwi[i] (signal_irq_mtty[i - 16]);
508	else if (i < 30) xicu->p_hwi[i] (signal_false);
509	else if (i < 31) xicu->p_hwi[i] (signal_irq_memc);
510	else xicu->p_hwi[i] (signal_irq_bdev);
511	}
512	else // other clusters
513	{
514	if (i < 8) xicu->p_hwi[i] (signal_false);
515	else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i - 8]);
516	else if (i < 30) xicu->p_hwi[i] (signal_false);
517	else if (i < 31) xicu->p_hwi[i] (signal_irq_memc);
518	else xicu->p_hwi[i] (signal_false);
519	}
520	}
521
522	std::cout << " - XICU connected" << std::endl;
523
524	//////////////////////////////////////////////// MEMC
525	memc->p_clk (this->p_clk);
526	memc->p_resetn (this->p_resetn);
527	memc->p_irq (signal_irq_memc);
528	memc->p_vci_ixr (signal_vci_xram);
529	memc->p_vci_tgt (signal_vci_tgt_memc);
530	memc->p_dspin_p2m (signal_dspin_p2m_memc);
531	memc->p_dspin_m2p (signal_dspin_m2p_memc);
532	memc->p_dspin_clack (signal_dspin_clack_memc);
533
534	std::cout << " - MEMC connected" << std::endl;
535
536	/////////////////////////////////////////////// XRAM
537	xram->p_clk (this->p_clk);
538	xram->p_resetn (this->p_resetn);
539	xram->p_vci (signal_vci_xram);
540
541	std::cout << " - XRAM connected" << std::endl;
542
543	////////////////////////////////////////////// MDMA
544	mdma->p_clk (this->p_clk);
545	mdma->p_resetn (this->p_resetn);
546	mdma->p_vci_target (signal_vci_tgt_mdma);
547	mdma->p_vci_initiator (signal_vci_ini_mdma);
548	for (size_t i = 0; i < nb_dmas; i++)
549	mdma->p_irq[i] (signal_irq_mdma[i]);
550
551	std::cout << " - MDMA connected" << std::endl;
552
553	/////////////////////////////// Components in I/O cluster
554
555	if (io)
556	{
557	// BDEV
558	bdev->p_clk (this->p_clk);
559	bdev->p_resetn (this->p_resetn);
560	bdev->p_irq (signal_irq_bdev);
561	bdev->p_vci_target (signal_vci_tgt_bdev);
562	bdev->p_vci_initiator (signal_vci_ini_bdev);
563
564	std::cout << " - BDEV connected" << std::endl;
565
566	// FBUF
567	fbuf->p_clk (this->p_clk);
568	fbuf->p_resetn (this->p_resetn);
569	fbuf->p_vci (signal_vci_tgt_fbuf);
570
571	std::cout << " - FBUF connected" << std::endl;
572
573	// MNIC
574	mnic->p_clk (this->p_clk);
575	mnic->p_resetn (this->p_resetn);
576	mnic->p_vci (signal_vci_tgt_mnic);
577	for (size_t i = 0; i < nic_channels; i++)
578	{
579	mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]);
580	mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]);
581	}
582
583	std::cout << " - MNIC connected" << std::endl;
584
585	// CHBUF
586	chbuf->p_clk (this->p_clk);
587	chbuf->p_resetn (this->p_resetn);
588	chbuf->p_vci_target (signal_vci_tgt_chbuf);
589	chbuf->p_vci_initiator (signal_vci_ini_chbuf);
590	for (size_t i = 0; i < chbufdma_channels; i++)
591	{
592	chbuf->p_irq[i] (signal_irq_chbuf[i]);
593	}
594
595	std::cout << " - CHBUF connected" << std::endl;
596
597	// BROM
598	brom->p_clk (this->p_clk);
599	brom->p_resetn (this->p_resetn);
600	brom->p_vci (signal_vci_tgt_brom);
601
602	std::cout << " - BROM connected" << std::endl;
603
604	// MTTY
605	mtty->p_clk (this->p_clk);
606	mtty->p_resetn (this->p_resetn);
607	mtty->p_vci (signal_vci_tgt_mtty);
608	for (size_t i = 0; i < nb_ttys; i++)
609	{
610	mtty->p_irq[i] (signal_irq_mtty[i]);
611	}
612
613	std::cout << " - MTTY connected" << std::endl;
614
615
616	// Sim Helper
617	simhelper->p_clk (this->p_clk);
618	simhelper->p_resetn (this->p_resetn);
619	simhelper->p_vci (signal_vci_tgt_simh);
620
621	std::cout << " - SIMH connected" << std::endl;
622	}
623	} // end constructor
624
625
626
627	template<size_t dspin_cmd_width,
628	size_t dspin_rsp_width,
629	typename vci_param_int,
630	typename vci_param_ext> TsarXbarCluster<dspin_cmd_width,
631	dspin_rsp_width,
632	vci_param_int,
633	vci_param_ext>::~TsarXbarCluster() {
634
635	dealloc_elems<DspinInput<dspin_cmd_width> > (p_cmd_in, 4, 3);
636	dealloc_elems<DspinOutput<dspin_cmd_width> >(p_cmd_out, 4, 3);
637	dealloc_elems<DspinInput<dspin_rsp_width> > (p_rsp_in, 4, 2);
638	dealloc_elems<DspinOutput<dspin_rsp_width> >(p_rsp_out, 4, 2);
639
640	for (size_t p = 0; p < n_procs; p++)
641	{
642	delete proc[p];
643	}
644
645	delete memc;
646	delete xram;
647	delete xicu;
648	delete mdma;
649	delete xbar_d;
650	delete wt_xbar_d;
651	delete wi_xbar_d;
652	delete xbar_m2p_c;
653	delete xbar_p2m_c;
654	delete xbar_clack_c;
655	delete router_cmd;
656	delete router_rsp;
657	if (brom != NULL)
658	{
659	delete brom;
660	delete fbuf;
661	delete bdev;
662	delete mnic;
663	delete chbuf;
664	delete mtty;
665	delete simhelper;
666	}
667	}
668
669
670	template<size_t dspin_cmd_width,
671	size_t dspin_rsp_width,
672	typename vci_param_int,
673	typename vci_param_ext>
674	void TsarXbarCluster<dspin_cmd_width,
675	dspin_rsp_width,
676	vci_param_int,
677	vci_param_ext>::trace(sc_core::sc_trace_file * tf, const std::string & name) {
678
679	#define __trace(x) sc_core::sc_trace(tf, x, name + "_" + #x)
680	__trace(signal_vci_l2g_d);
681	__trace(signal_vci_g2l_d);
682	__trace(signal_vci_tgt_memc);
683	__trace(signal_vci_tgt_xicu);
684	__trace(signal_vci_tgt_mdma);
685	__trace(signal_vci_ini_mdma);
686
687	for (size_t p = 0; p < n_procs; p++) {
688	std::ostringstream signame;
689	signame << "vci_ini_proc_" << p;
690	sc_core::sc_trace(tf, signal_vci_ini_proc[p], signame.str());
691	}
692	__trace(signal_vci_tgt_mtty);
693	__trace(signal_vci_tgt_brom);
694	__trace(signal_vci_tgt_bdev);
695	__trace(signal_vci_tgt_fbuf);
696	__trace(signal_vci_tgt_simh);
697	__trace(signal_vci_ini_bdev);
698	__trace(signal_vci_tgt_memc);
699	__trace(signal_vci_xram);
700	#undef trace
701
702	}
703
704
705
706
707	}}
708
709	// Local Variables:
710	// tab-width: 4
711	// c-basic-offset: 4
712	// c-file-offsets:((innamespace . 0)(inline-open . 0))
713	// indent-tabs-mode: nil
714	// End:
715
716	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
717

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