source: trunk/softs/giet_tsar/reset.S @ 622

Last change on this file since 622 was 622, checked in by alain, 9 years ago

Introducing a minimal GIET:

  • no virtual memory
  • no conyext switch
  • no system calls
File size: 3.7 KB
Line 
1/********************************************************************************
2*       File : reset.S
3*       Author : Alain Greiner
4*       Date : 15/01/2014
5*********************************************************************************
6* This is a boot code for a generic multi-clusters / multi-processors
7* TSAR architecture (up to 256 clusters / up to 4  processors per cluster).
8* The physical address is 40 bits, and the 8 MSB bits A[39:32] define the
9* cluster index.
10*
11* As we don't want to use the virtual memory, the physical address is
12* equal to  the virtual address (identity mapping) and all processors use
13* the physical memory bank in cluster 0. Both the reset base address and
14* the kernel base address can be redefined to use a physical memory bank
15* smaller than 4 Gbytes.
16*
17* There is one XCU iand one MMC per cluster.
18* All other peripherals (including the boot ROM) are located in cluster 0.
19* Only two HWI interrupts are supported:
20* - IRQ_IN[0]      IOC
21* - IRQ_IN[12]     MMC
22*
23* The boot sequence is the following:
24*   - Each processor initializes the stack pointer ($29) depending on proc_id.
25*   - Each processor initializes the CP0 EBASE register
26*       - Only processor 0 initializes the Interrupt vector.
27*   - Each processor initializes its private XCU mask.
28*       - Each processor initializes the Status Register (SR)
29*       - Each processor jumps to the same main address in kernel mode...
30********************************************************************************/
31
32#include "hard_config.h"
33#include "mips32_registers.h"
34
35        .section .reset,"ax",@progbits
36
37        .extern seg_stack_base
38        .extern seg_xcu_base
39    .extern seg_kcode_base
40        .extern _interrupt_vector
41        .extern _ioc_isr
42        .extern _mmc_isr
43    .extern main
44
45        .globl  reset                           
46        .ent    reset
47        .align  2
48
49reset:
50        .set noreorder
51
52/* each proc computes  proc_id, lpid, cluster_xy */
53    mfc0    $26,    CP0_PROCID
54    andi    $26,    $26,    0x3FF           /* at most 1024 processors */
55    move    $10,    $26                 /* $10 <= proc_id  */
56    li      $27,    NB_PROCS_MAX
57    divu    $26,    $27
58    mfhi    $11                         /* $11 <= lpid */
59    mflo    $12                         /* $12 <= cluster_xy */
60
61/* each proc initializes stack pointer (64K per processor) */
62    la      $27,    seg_stack_base
63    addi    $26,    $10,    1               /* $26 <= (proc_id + 1)           */
64    sll     $26,    $26,    16          /* $26 <= (proc_id + 1) * 64K     */
65    addu    $29,    $27,    $26             /* $29 <= seg_stack_base(proc_id) */
66
67/* each proc initializes CP0 EBASE register */
68    la      $26,    seg_kcode_base
69    mtc0    $26,    CP0_EBASE           /* CP0_EBASE <= seg_kcode_base */
70
71/* only proc (0,0,0) initializes interrupt vector */
72    bne     $10,    $0,    reset_xcu
73    nop
74
75    la      $26,    _interrupt_vector   /* interrupt vector address */
76    la      $27,    _ioc_isr
77    sw      $27,     0($26)             /* interrupt_vector[0] <= _isr_ioc */
78    la      $27,    _mmc_isr
79    sw      $27,     48($26)            /* interrupt_vector[12] <= _isr_mmc */
80   
81reset_xcu:
82
83/* only proc (x,y,0) receive IRQs and initialise its private XCU mask */
84    bne     $11,    $0,     reset_end
85    nop
86    la      $26,    seg_xcu_base
87    li      $27,    0b010010000000      /* offset for MSK_HWI_ENABLE & lpid == 0 */
88    addu    $24,    $26,    $27         /* $24 <= &MASK  */
89    li      $25,    0x00001001              /* IOC: IRQ[0] / MEMC: IRQ[12] */
90    sw      $25,    0($24)              /* set MASK */
91
92reset_end:
93
94/* initializes SR register */
95    li      $26,    0x0000FF01         
96    mtc0    $26,    $12                         /* SR <= kernel mode / IRQ enable */
97
98/* jumps to main in kernel mode */
99    la      $26,    main
100    jr      $26
101    nop
102
103    .end        reset
104
105    .set reorder
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