source: trunk/softs/tests_cc_vcache/common/xicu.h @ 520

Last change on this file since 520 was 520, checked in by bouyer, 11 years ago

Re-add the tests; reverting previous which was done at the wrong level (sorry)

File size: 3.7 KB
Line 
1#define XICU_BASE 0xd8200000
2#define __XICU_FUNC_SHIFT 7
3#define __XICU_IDX_SHIFT 2
4#define __XICU_RIDX(func, idx) \
5    ((((func) & 0x1f) << __XICU_FUNC_SHIFT) + \
6     (((idx) & 0x1f) << __XICU_IDX_SHIFT))
7
8/* triggers the wtiidx interrupt. R/W */
9#define XICU_WTI_REG_FUNC 0x00
10#define XICU_WTI_REG(wtiidx) __XICU_RIDX(XICU_WTI_REG_FUNC, wtiidx)
11
12/* Timer period R/W */
13#define XICU_PTI_PER_FUNC 0x01
14#define XICU_PTI_PER(ptiidx) __XICU_RIDX(XICU_PTI_PER_FUNC, ptiidx)
15
16/* timer value R/W */
17#define XICU_PTI_VAL_FUNC 0x02
18#define XICU_PTI_VAL(ptiidx) __XICU_RIDX(XICU_PTI_VAL_FUNC, ptiidx)
19
20/* Timer interrupt acknowledge. R */
21#define XICU_PTI_ACK_FUNC 0x03
22#define XICU_PTI_ACK(ptiidx) __XICU_RIDX(XICU_PTI_ACK_FUNC, ptiidx)
23
24/*
25 * remaining registers define the way interrupt sources are mutiplexed to
26 * the output lines. Indexed by output line number.
27 */
28/*
29 * Multiplex timers to output lines:
30 * XICU_MSK_PTI mask register for outidx line (bit to 1 enable interrupt)
31 * XICU_MSK_PTI_E atomically add a set of bits to XICU_MSK_PTI
32 * XICU_MSK_PTI_D atomically clear a set of bits from XICU_MSK_PTI
33 * XICU_PTI_ACT get active PTI lines for this output line
34 */
35#define XICU_MSK_PTI_FUNC 0x04 /* R/W */
36#define XICU_MSK_PTI(outidx) __XICU_RIDX(XICU_MSK_PTI_FUNC, outidx)
37
38#define XICU_MSK_PTI_E_FUNC 0x05 /* W */
39#define XICU_MSK_PTI_E(outidx) __XICU_RIDX(XICU_MSK_PTI_E_FUNC, outidx)
40
41#define XICU_MSK_PTI_D_FUNC 0x06 /* W */
42#define XICU_MSK_PTI_D(outidx) __XICU_RIDX(XICU_MSK_PTI_D_FUNC, outidx)
43
44#define XICU_PTI_ACT_FUNC 0x06 /* R */
45#define XICU_PTI_ACT(outidx) __XICU_RIDX(XICU_PTI_ACT_FUNC, outidx)
46
47/*
48 * Multiplex hardware input lines to output lines:
49 * XICU_MSK_HWI mask register for outidx line (bit to 1 enable interrupt)
50 * XICU_MSK_HWI_E atomically add a set of bits to XICU_MSK_HWI
51 * XICU_MSK_HWI_D atomically clear a set of bits from XICU_MSK_HWI
52 * XICU_HWI_ACT get active HWI lines for this output line
53 */
54#define XICU_MSK_HWI_FUNC 0x08 /* R/W */
55#define XICU_MSK_HWI(outidx) __XICU_RIDX(XICU_MSK_HWI_FUNC, outidx)
56
57#define XICU_MSK_HWI_E_FUNC 0x09 /* W */
58#define XICU_MSK_HWI_E(outidx) __XICU_RIDX(XICU_MSK_HWI_E_FUNC, outidx)
59
60#define XICU_MSK_HWI_D_FUNC 0x0a /* W */
61#define XICU_MSK_HWI_D(outidx) __XICU_RIDX(XICU_MSK_HWI_D_FUNC, outidx)
62
63#define XICU_HWI_ACT_FUNC 0x0a /* R */
64#define XICU_HWI_ACT(outidx) __XICU_RIDX(XICU_HWI_ACT_FUNC, outidx)
65
66/*
67 * Multiplex hardware input lines to output lines:
68 * XICU_MSK_WTI mask register for outidx line (bit to 1 enable interrupt)
69 * XICU_MSK_WTI_E atomically add a set of bits to XICU_MSK_WTI
70 * XICU_MSK_WTI_D atomically clear a set of bits from XICU_MSK_WTI
71 * XICU_WTI_ACT get active WTI lines for this output line
72 */
73#define XICU_MSK_WTI_FUNC 0x0c /* R/W */
74#define XICU_MSK_WTI(outidx) __XICU_RIDX(XICU_MSK_WTI_FUNC, outidx)
75
76#define XICU_MSK_WTI_E_FUNC 0x0d /* W */
77#define XICU_MSK_WTI_E(outidx) __XICU_RIDX(XICU_MSK_WTI_E_FUNC, outidx)
78
79#define XICU_MSK_WTI_D_FUNC 0x0e /* W */
80#define XICU_MSK_WTI_D(outidx) __XICU_RIDX(XICU_MSK_WTI_D_FUNC, outidx)
81
82#define XICU_WTI_ACT_FUNC 0x0e /* R */
83#define XICU_WTI_ACT(outidx) __XICU_RIDX(XICU_WTI_ACT_FUNC, outidx)
84
85/* source priority encoder for outpout lines */
86#define XICU_PRIO_FUNC 0x0f
87#define XICU_PRIO(outidx) __XICU_RIDX(XICU_PRIO_FUNC, outidx)
88
89#define XICU_PRIO_PTI 0x00000001 /* Timer interrrupt pending */
90#define XICU_PRIO_PTII(val) ((val) >> 8 & 0x1f) /* first PTI pending */
91#define XICU_PRIO_HWI 0x00000002 /* Hardware interrrupt pending */
92#define XICU_PRIO_HWII(val) ((val) >> 16 & 0x1f) /* first HWI pending */
93#define XICU_PRIO_WTI 0x00000004 /* write-triggered interrrupt pending */
94#define XICU_PRIO_WTII(val) ((val) >> 24 & 0x1f) /* first WTI pending */
95
96#define XICU_PRIO_PENDING (XICU_PRIO_PTI|XICU_PRIO_HWI|XICU_PRIO_WTI)
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