source: trunk/softs/tsar_boot/conf/platform_de2_115_fpga/hard_config.h @ 758

Last change on this file since 758 was 758, checked in by cfuguet, 10 years ago

tsar_boot: improving configuration infrastructure

  • Using hard_config.h which respects the same sintax that the hard_config.h file of all TSAR platforms. This file can be then generated by the GIET-VM genmap tool or written manually.
  • All peripheral drivers have been moved to a drivers directory and they are compiled as a static library. This allows GCC to only include in the final .ELF the object files of used peripherals and not all of them.
  • Example hard_config.h and ldscripts have been introduced in the conf directory.
  • Improving comments in all files
File size: 2.4 KB
Line 
1#ifndef HARD_CONFIG_H
2#define HARD_CONFIG_H
3
4/* General platform parameters */
5
6#define X_SIZE                 1
7#define Y_SIZE                 1
8#define X_WIDTH                4
9#define Y_WIDTH                4
10#define X_IO                   0
11#define Y_IO                   0
12#define NB_PROCS_MAX           2
13#define IRQ_PER_PROCESSOR      4
14#define RESET_ADDRESS          0xff000000
15#define NB_TOTAL_PROCS         16
16
17/* Peripherals */
18
19#define NB_TTY_CHANNELS        1
20#define NB_IOC_CHANNELS        1
21#define NB_NIC_CHANNELS        0
22#define NB_CMA_CHANNELS        0
23#define NB_TIM_CHANNELS        0
24#define NB_DMA_CHANNELS        0
25
26#define USE_XCU                1
27#define USE_IOB                0
28#define USE_PIC                0
29#define USE_FBF                1
30
31#define USE_IOC_BDV            0
32#define USE_IOC_SPI            1
33#define USE_IOC_HBA            0
34
35#define USE_RAMDISK            0
36
37#define FBUF_X_SIZE            640
38#define FBUF_Y_SIZE            480
39
40#define XCU_NB_INPUTS          16
41
42/* base addresses and sizes for physical segments */
43
44#define SEG_RAM_BASE           0x0
45#define SEG_RAM_SIZE           0x08000000 /* 128 MB */
46
47#define SEG_CMA_BASE           0xb6000000
48#define SEG_CMA_SIZE           0x4000
49
50#define SEG_DMA_BASE           0xb1000000
51#define SEG_DMA_SIZE           0x4000
52
53#define SEG_FBF_BASE           0xb7000000
54#define SEG_FBF_SIZE           0x100000
55
56#define SEG_ICU_BASE           0xffffffff
57#define SEG_ICU_SIZE           0x0
58
59#define SEG_IOB_BASE           0xbe000000
60#define SEG_IOB_SIZE           0x1000
61
62#define SEG_IOC_BASE           0xf2000000
63#define SEG_IOC_SIZE           0x1000
64
65#define SEG_MMC_BASE           0xe0000000
66#define SEG_MMC_SIZE           0x1000
67
68#define SEG_MWR_BASE           0xffffffff
69#define SEG_MWR_SIZE           0x0
70
71#define SEG_ROM_BASE           0xff000000
72#define SEG_ROM_SIZE           0x4000
73
74#define SEG_SIM_BASE           0xffffffff
75#define SEG_SIM_SIZE           0x0
76
77#define SEG_NIC_BASE           0xffffffff
78#define SEG_NIC_SIZE           0x0
79
80#define SEG_PIC_BASE           0xffffffff
81#define SEG_PIC_SIZE           0x0
82
83#define SEG_TIM_BASE           0xffffffff
84#define SEG_TIM_SIZE           0x0
85
86#define SEG_TTY_BASE           0xf4000000
87#define SEG_TTY_SIZE           0x4000
88
89#define SEG_XCU_BASE           0xf0000000
90#define SEG_XCU_SIZE           0x1000
91
92#define SEG_RDK_BASE           0xffffffff
93#define SEG_RDK_SIZE           0x0
94
95#endif
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