source: trunk/softs/tsar_boot/conf/platform_tsar_generic_iob/hard_config.h @ 758

Last change on this file since 758 was 758, checked in by cfuguet, 10 years ago

tsar_boot: improving configuration infrastructure

  • Using hard_config.h which respects the same sintax that the hard_config.h file of all TSAR platforms. This file can be then generated by the GIET-VM genmap tool or written manually.
  • All peripheral drivers have been moved to a drivers directory and they are compiled as a static library. This allows GCC to only include in the final .ELF the object files of used peripherals and not all of them.
  • Example hard_config.h and ldscripts have been introduced in the conf directory.
  • Improving comments in all files
File size: 2.4 KB
Line 
1/* Generated by genmap for tsar_iob_2_2_4 */
2
3#ifndef HARD_CONFIG_H
4#define HARD_CONFIG_H
5
6/* General platform parameters */
7
8#define X_SIZE                 2
9#define Y_SIZE                 2
10#define X_WIDTH                4
11#define Y_WIDTH                4
12#define X_IO                   0
13#define Y_IO                   0
14#define NB_PROCS_MAX           4
15#define IRQ_PER_PROCESSOR      4
16#define RESET_ADDRESS          0xbfc00000
17#define NB_TOTAL_PROCS         16
18
19/* Peripherals */
20
21#define NB_TTY_CHANNELS        1
22#define NB_IOC_CHANNELS        1
23#define NB_NIC_CHANNELS        2
24#define NB_CMA_CHANNELS        4
25#define NB_TIM_CHANNELS        0
26#define NB_DMA_CHANNELS        4
27
28#define USE_XCU                1
29#define USE_IOB                1
30#define USE_PIC                1
31#define USE_FBF                1
32
33#define USE_IOC_BDV            1
34#define USE_IOC_SPI            0
35#define USE_IOC_HBA            0
36
37#define USE_RAMDISK            0
38
39#define FBUF_X_SIZE            1024
40#define FBUF_Y_SIZE            1024
41
42#define XCU_NB_INPUTS          16
43
44/* base addresses and sizes for physical segments */
45
46#define SEG_RAM_BASE           0x0
47#define SEG_RAM_SIZE           0x4000000
48
49#define SEG_CMA_BASE           0xb6000000
50#define SEG_CMA_SIZE           0x4000
51
52#define SEG_DMA_BASE           0xb1000000
53#define SEG_DMA_SIZE           0x4000
54
55#define SEG_FBF_BASE           0xb7000000
56#define SEG_FBF_SIZE           0x100000
57
58#define SEG_ICU_BASE           0xffffffff
59#define SEG_ICU_SIZE           0x0
60
61#define SEG_IOB_BASE           0xbe000000
62#define SEG_IOB_SIZE           0x1000
63
64#define SEG_IOC_BASE           0xb3000000
65#define SEG_IOC_SIZE           0x1000
66
67#define SEG_MMC_BASE           0xb2000000
68#define SEG_MMC_SIZE           0x1000
69
70#define SEG_MWR_BASE           0xffffffff
71#define SEG_MWR_SIZE           0x0
72
73#define SEG_ROM_BASE           0xbfc00000
74#define SEG_ROM_SIZE           0x4000
75
76#define SEG_SIM_BASE           0xffffffff
77#define SEG_SIM_SIZE           0x0
78
79#define SEG_NIC_BASE           0xb5000000
80#define SEG_NIC_SIZE           0x80000
81
82#define SEG_PIC_BASE           0xb8000000
83#define SEG_PIC_SIZE           0x1000
84
85#define SEG_TIM_BASE           0xffffffff
86#define SEG_TIM_SIZE           0x0
87
88#define SEG_TTY_BASE           0xb4000000
89#define SEG_TTY_SIZE           0x4000
90
91#define SEG_XCU_BASE           0xb0000000
92#define SEG_XCU_SIZE           0x1000
93
94#define SEG_RDK_BASE           0xffffffff
95#define SEG_RDK_SIZE           0x0
96
97#endif
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