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reset.S @ 348

Last change on this file since 348 was 348, checked in by cfuguet, 11 years ago
Adding the boot_putc and the boot_getc in the functions pointer table defined at the beginning of the reset code
File size: 6.5 KB

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1	/**
2	* \file : reset.S
3	* \date : 01/12/2012
4	* \author: Cesar FUGUET & Manuel BOUYER & Alain Greiner
5	*
6	* This is a boot code for a generic multi-clusters / multi-processors
7	* TSAR architecture (up to 256 clusters / up to 4 processors per cluster).
8	* There is one XICU, one TTY, one DMA and one stack segment per cluster.
9	* segment base adresses = base + cluster_segment_increment*cluster_id
10	*
11	* - Each processor initializes the Status Register (SR) to disable interrupts.
12	* - Each processor initializes the Count Register.
13	* - Each processor initialises its private XICU Write Triggered Interruption
14	* mask register.
15	* - Only processor 0 initializes the stack pointer ($29).
16	* - Only processor 0 (boot processor) executes the boot_load_elf function to
17	* load in memory the boot loader stored in the block BOOT_LOADER_LBA of
18	* the disk.
19	* - All non-boot processors wait in a low power consumption mode that the
20	* processor 0 wakes them using the IPI (Inter Processor Interruption)
21	* functionality of the XICU device.
22	*/
23
24	#include <defs.h>
25	#include <mips32_registers.h>
26
27	.section .boot,"ax",@progbits
28
29	.extern seg_stack_base
30
31	.extern dtb_addr
32	.extern boot_ioc_init
33	.extern boot_putc
34	.extern boot_getc
35	.extern boot_puts
36	.extern boot_putx
37	.extern boot_ioc_read
38	.extern boot_elf_loader
39	.extern boot_memcpy
40
41	.globl boot /* Make reset an external symbol */
42	.ent boot
43
44	.align 2
45	.set noreorder
46
47	boot:
48	b _boot /* 0xbfc0000 */
49	nop /* 0xbfc0004 */
50
51	/* Addresses of the functions provided by this pre-loader */
52
53	.word BOOT_VERSION /* 0xbfc0008 */
54	.word dtb_addr /* 0xbfc000c */
55	.word boot_getc /* 0xbfc0010 */
56	.word boot_putc /* 0xbfc0014 */
57	.word boot_puts /* 0xbfc0018 */
58	.word boot_putx /* 0xbfc001C */
59	.word boot_putd /* 0xbfc0020 */
60	.word boot_ioc_read /* 0xbfc0024 */
61	.word boot_elf_loader /* 0xbfc0028 */
62	.word boot_memcpy /* 0xbfc002C */
63
64	_boot:
65	/* Disable interruptions, keep STATUSbev enabled */
66
67	li k0, (1 << 22)
68	mtc0 k0, CP0_STATUS
69
70	/* Computes proc_id, local_id, cluster_id, and cluster_increment */
71
72	mfc0 k0, CP0_EBASE
73	andi t0, k0, 0x3FF /* t0 <= proc_id (at most 1024 processors) */
74
75	move t3, t0
76
77	la k0, NB_PROCS /* k0 <= number of processors per cluster */
78	divu t3, k0
79	mfhi t1 /* t1 <= local_id = proc_id % NB_PROCS */
80	mflo t2 /* t2 <= cluster_id = proc_id / NB_PROCS */
81
82	la k0, NB_CLUSTERS
83	li t3, 0x80000000
84	divu t3, k0
85	mflo t4
86	sll t4, 1 /* t4 <= cluster_increment = 4G / NB_CLUSTERS */
87
88	mult t4, t2
89	mflo t5 /* t5 <= cluster_id * cluster_increment */
90
91	/* Initialization of the count register in the coprocessor 0 */
92
93	mtc0 zero, CP0_COUNT
94
95	/* In each cluster, the ICU base address depends on the cluster_id */
96
97	la t3, ICU_BASE
98	addu t3, t3, t5 /* t3 <= ICU_BASE + */
99	/* (cluster_id * cluster_increment) */
100
101	/**
102	* Compute the output index for the Write Triggered Interruption mask.
103	* Each processor enable the WTI for its irq output
104	* Each processor may have IRQ_PER_PROC private irq outputs from
105	* the XICU
106	*/
107
108	move t4, t1 /* t4 <= local_id */
109	li t5, IRQ_PER_PROC /* t5 <= IRQ_PER_PROC */
110	multu t4, t5
111	mflo t6 /* t6 <= IRQ_PER_PROC * local_id */
112	sll t4, t6, 2 /* t4 <= OUT_INDEX = t6 * 4 */
113
114	li t5, (0xC << 7) /* t5 <= FUNC = XICU_MSK_WTI */
115	or t4, t4, t5 /* t4 <= FUNC \| INDEX \| 00 */
116	or t5, t3, t4 /* t5 <= &XICU[MSK_WTI][OUT_INDEX] */
117
118	/* Compute and set WTI mask */
119
120	li t4, 1
121	sllv t4, t4, t1 /* Set XICU[MSK_WTI][INDEX][local_id] */
122	sw t4, 0(t5) /* XICU[MSK_WTI][INDEX] <= t4 */
123
124	/**
125	* We have:
126	* t0: global id
127	* t1: local id
128	* t2: cluster id
129	* t3: xicu base address
130	*
131	* Only processor 0 in cluster 0 executes the boot loader
132	*/
133
134	bne zero, t0, _reset_wait
135	nop
136
137	/* Initializes stack pointer */
138
139	la k1, seg_stack_base
140	li k0, BOOT_STACK_SIZE
141	addu sp, k1, k0 /* sp <= seg_stack_base + BOOT_STACK_SIZE */
142
143	#ifndef SOCLIB_IOC
144
145	/* Initialize the block device */
146
147	la k0, boot_ioc_init
148	jalr k0
149	nop
150
151	#endif
152
153	/**
154	* Jump to the boot elf loader routine
155	* Passing as argument the block number in which it must be
156	* the executable elf file to load
157	*/
158
159	la k0, boot_elf_loader
160	li a0, BOOT_LOADER_LBA
161	jalr k0
162	nop
163
164	/**
165	* We jump to the entry point address defined in the
166	* ELF file. This address is returned by boot_elf_loader function.
167	* All function arguments are 0
168	*/
169
170	move a0, zero
171	move a1, zero
172	move a2, zero
173	move a3, zero
174	jr v0
175	nop
176
177	/**
178	* Wait in low power consumption mode until the application wakes us.
179	* The application wakes up the non-boot CPUs using a IPI with a non-0
180	* value in the mailbox. This non-0 value is the address to jump to.
181	*/
182
183	_reset_wait:
184	/**
185	* We have:
186	* t0: global id
187	* t1: local id
188	* t2: cluster id
189	* t3: xicu base address
190	*/
191
192	sll t4, t1, 2 /* t4 <= local_id * 4 */
193	addu t5, t4, t3 /* t5 <= &XICU[WTI_REG][local_id] */
194
195	wait
196
197	lw k0, 0(t5) /* k0 <= XICU[WTI_REG][local_id] */
198	jr k0
199	nop
200
201	/* Exception entry point */
202	.org 0x0380
203	_excep:
204	mfc0 a0, CP0_STATUS /* first arg is status */
205	mfc0 a1, CP0_CAUSE /* second arg is cause */
206	mfc0 a2, CP0_EPC /* third argc is epc */
207	nop
208	j handle_except
209	nop
210
211	.end boot
212
213	.set reorder
214
215	/*
216	* vim: tabstop=4 : shiftwidth=4 : expandtab
217	*/

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