Changeset 1001 for branches/reconfiguration/modules/dspin_local_crossbar/caba/source/src/dspin_local_crossbar.cpp

Timestamp:

Jun 16, 2015, 9:24:36 PM (9 years ago)

Author:

cfuguet

Message:

reconf: introducing a hardware barrier in the global-local interface of
the local interconnects.

• This barrier is controlled by a port (barrier enable) in the dspin and vci local interconnects.

• The barrier enable port is connected to a configuration register of the XICU component to allow the software to control this barrier. The barrier is enabled when the barrier enable port value is different of 0xFFFFFFFF. As the configuration register of the XICU component are reset to 0, this barrier is enabled by default.

• This barrier allows to isolate the cluster from the rest of the architecture and only if it self-diagnoses as functional, it release the barrier to communicate with the others.

• The same barrier enable signal is connected to the five local interconnects. Therefore, either all are released or all are disabled.

• If a local initiator or an external initiator sends a packet out or into the cluster respectively, and the barrier is enabled, the packet is dropped.

File:

• branches/reconfiguration/modules/dspin_local_crossbar/caba/source/src/dspin_local_crossbar.cpp (modified) (7 diffs)

branches/reconfiguration/modules/dspin_local_crossbar/caba/source/src/dspin_local_crossbar.cpp

@@ -52 +52 @@
                                 const bool           is_cmd,
                                 const bool           use_routing_table,
-                                const bool           broadcast_supported)
+                                const bool           broadcast_supported,
+                                const bool           hardware_barrier )
     : BaseModule(name),
 
@@ -141 +142 @@
         }
 
+        if ( hardware_barrier )
+        {
+            p_barrier_enable = new sc_in<uint32_t>("p_barrier_enable");
+        }
+        else
+        {
+            p_barrier_enable = NULL;
+        }
+
         assert( (flit_width >= x_width + y_width + l_width) and
         "ERROR in DSPIN_LOCAL_CROSSBAR: flit_width < x_width + y_width + l_width");
@@ -281 +291 @@
         internal_flit_t     fifo_out_wdata[m_local_outputs+1];
 
+        // local-to-global and global-to-local hardware barrier enable signal
+        const bool barrier_enable = (p_barrier_enable != NULL) and
+                                    (p_barrier_enable->read() != 0xFFFFFFFF);
+
         // reset
         if ( p_resetn.read() == false )
@@ -326 +340 @@
         for ( size_t j = 0 ; j <= m_local_outputs ; j++ )
         {
-            if( r_alloc_out[j].read() and (r_fifo_out[j].wok()) )
+            bool read = r_fifo_out[j].wok();
+            if ( j == m_local_outputs )
+            {
+                read = read or barrier_enable;
+            }
+            if( r_alloc_out[j].read() and read )
             {
                 get_out[j] = r_index_out[j].read();
@@ -349 +368 @@
                 {
                     put_in[i] = false;
-                    if ( r_fifo_in[i].rok() ) // packet available in input fifo
+
+                    bool write = r_fifo_in[i].rok();
+                    if ( i == m_local_inputs )
+                    {
+                        write = write and not barrier_enable;
+                    }
+                    if ( write ) // packet available in input fifo
                     {
                         if ( is_broadcast(r_fifo_in[i].read().data ) and
@@ -491 +516 @@
             }
         }  // end loop on input ports
+        fifo_in_read[m_local_inputs] = fifo_in_read[m_local_inputs] or barrier_enable;
 
         // loop on the output ports :
@@ -499 +525 @@
             if( r_alloc_out[j] )  // output port allocated
             {
-                fifo_out_write[j] = put_in[r_index_out[j]];
+                bool write = put_in[r_index_out[j]];
+                if (j == m_local_outputs)
+                {
+                    write = write and not barrier_enable;
+                }
+                fifo_out_write[j] = write;
                 fifo_out_wdata[j] = data_in[r_index_out[j]];
+
             }
         }  // end loop on the output ports