Changeset 1012 for trunk/platforms/tsar_generic_xbar/top.cpp
- Timestamp:
- Sep 11, 2015, 3:44:14 PM (9 years ago)
- File:
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- 1 edited
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trunk/platforms/tsar_generic_xbar/top.cpp
r885 r1012 126 126 #endif 127 127 128 // cluster index (computed from x,y coordinates)128 // nluster index (computed from x,y coordinates) 129 129 #ifdef USE_ALMOS 130 130 #define cluster(x,y) (y + x * Y_SIZE) … … 213 213 214 214 #ifdef USE_ALMOS 215 #define soft_name PREFIX_OS"bootloader-tsar-mipsel.bin",\ 216 PREFIX_OS"kernel-soclib.bin@0xbfc10000:D",\ 217 PREFIX_OS"arch-info.bib@0xBFC08000:D" 215 #define soft_name PREFIX_OS"preloader.elf" 218 216 #endif 219 217 #ifdef USE_GIET … … 232 230 // For all components: global TGTID = global SRCID = cluster_index 233 231 //////////////////////////////////////////////////////////////////// 234 235 #define MEMC_TGTID 0236 #define XICU_TGTID 1237 #define MDMA_TGTID 2238 #define MTTY_TGTID 3239 #define BDEV_TGTID 4240 #define MNIC_TGTID 5241 #define BROM_TGTID 6242 #define CDMA_TGTID 7243 #define SIMH_TGTID 8244 #define FBUF_TGTID 9245 232 246 233 … … 254 241 255 242 #ifdef USE_GIET 256 // specific segments in "IO" cluster : absolute physical address 257 #define BROM_BASE 0x00BFC00000 258 #define BROM_SIZE 0x0000100000 // 1 Mbytes 259 260 #define FBUF_BASE 0x00B2000000 261 #define FBUF_SIZE (FBUF_X_SIZE * FBUF_Y_SIZE * 2) 262 263 #define BDEV_BASE 0x00B3000000 264 #define BDEV_SIZE 0x0000001000 // 4 Kbytes 265 266 #define MTTY_BASE 0x00B4000000 267 #define MTTY_SIZE 0x0000001000 // 4 Kbytes 268 269 #define MNIC_BASE 0x00B5000000 270 #define MNIC_SIZE 0x0000080000 // 512 Kbytes (for 8 channels) 271 272 #define CDMA_BASE 0x00B6000000 273 #define CDMA_SIZE 0x0000004000 * NB_CMA_CHANNELS 274 275 // replicated segments : address is incremented by a cluster offset 276 // offset = cluster(x,y) << (address_width-x_width-y_width); 277 278 #define MEMC_BASE 0x0000000000 279 #define MEMC_SIZE 0x0010000000 // 256 Mbytes per cluster 280 281 #define XICU_BASE 0x00B0000000 282 #define XICU_SIZE 0x0000001000 // 4 Kbytes 283 284 #define MDMA_BASE 0x00B1000000 285 #define MDMA_SIZE 0x0000001000 * NB_DMA_CHANNELS // 4 Kbytes per channel 286 287 #define SIMH_BASE 0x00B7000000 288 #define SIMH_SIZE 0x0000001000 243 #error "This platform is no more supported for the GIET" 289 244 #endif 290 245 … … 293 248 // 1 bit for Memcache or Peripheral, 4 for local peripheral id) 294 249 // (Almos supports 32 bits physical addresses) 295 296 #define CLUSTER_INC (0x80000000ULL / (X_SIZE * Y_SIZE) * 2)297 298 #define CLUSTER_IO_INC (cluster_io_id * CLUSTER_INC)299 #define MEMC_MAX_SIZE (0x40000000 / (X_SIZE * Y_SIZE)) // 0x40000000 : valeur totale souhaitée (ici : 1Go)300 301 #define BROM_BASE 0x00BFC00000302 #define BROM_SIZE 0x0000100000 // 1 Mbytes303 304 #define MEMC_BASE 0x0000000000305 #define MEMC_SIZE min(0x04000000, MEMC_MAX_SIZE)306 307 #define XICU_BASE (CLUSTER_INC >> 1) + (XICU_TGTID << 19)308 #define XICU_SIZE 0x0000001000 // 4 Kbytes309 310 #define MDMA_BASE (CLUSTER_INC >> 1) + (MDMA_TGTID << 19)311 #define MDMA_SIZE (0x0000001000 * NB_DMA_CHANNELS) // 4 Kbytes per channel312 313 #define BDEV_BASE (CLUSTER_INC >> 1) + (BDEV_TGTID << 19) + (CLUSTER_IO_INC)314 #define BDEV_SIZE 0x0000001000 // 4 Kbytes315 316 #define MTTY_BASE (CLUSTER_INC >> 1) + (MTTY_TGTID << 19) + (CLUSTER_IO_INC)317 #define MTTY_SIZE 0x0000001000 // 4 Kbytes318 319 #define FBUF_BASE (CLUSTER_INC >> 1) + (FBUF_TGTID << 19) + (CLUSTER_IO_INC)320 #define FBUF_SIZE (FBUF_X_SIZE * FBUF_Y_SIZE * 2) // Should be 0x80000321 322 #define MNIC_BASE (CLUSTER_INC >> 1) + (MNIC_TGTID << 19) + (CLUSTER_IO_INC)323 #define MNIC_SIZE 0x0000080000324 325 #define CDMA_BASE (CLUSTER_INC >> 1) + (CDMA_TGTID << 19) + (CLUSTER_IO_INC)326 #define CDMA_SIZE (0x0000004000 * NB_CMA_CHANNELS)327 328 #define SIMH_BASE (CLUSTER_INC >> 1) + (SIMH_TGTID << 19) + (CLUSTER_IO_INC)329 #define SIMH_SIZE 0x0000001000330 250 #endif 331 251 … … 339 259 using namespace soclib::common; 340 260 341 #ifdef USE_GIET342 char soft_name[256] = soft_pathname; // pathname to binary code343 #endif344 261 const int64_t max_cycles = 5000000; // Maximum number of cycles simulated in one sc_start call 345 262 int64_t ncycles = 0x7FFFFFFFFFFFFFFF; // simulated cycles … … 556 473 size_t y_width = Y_WIDTH; 557 474 558 assert( 475 assert((X_WIDTH <= 4) and (Y_WIDTH <= 4) and 559 476 "Up to 256 clusters"); 560 477 561 assert( 478 assert((X_SIZE <= (1 << X_WIDTH)) and (Y_SIZE <= (1 << Y_WIDTH)) and 562 479 "The X_WIDTH and Y_WIDTH parameter are insufficient"); 563 480 … … 583 500 { 584 501 sc_uint<vci_address_width> offset; 585 offset = (sc_uint<vci_address_width>) cluster(x,y)586 << (vci_address_width -x_width-y_width);502 offset = (sc_uint<vci_address_width>) cluster(x,y) 503 << (vci_address_width - x_width - y_width); 587 504 588 505 std::ostringstream si; 589 506 si << "seg_xicu_" << x << "_" << y; 590 maptabd.add(Segment(si.str(), XICU_BASE + offset, XICU_SIZE,591 IntTab(cluster(x,y), XICU_TGTID), false));507 maptabd.add(Segment(si.str(), SEG_XCU_BASE + offset, SEG_XCU_SIZE, 508 IntTab(cluster(x,y), XCU_TGTID), false)); 592 509 593 510 std::ostringstream sd; 594 511 sd << "seg_mdma_" << x << "_" << y; 595 maptabd.add(Segment(sd.str(), MDMA_BASE + offset, MDMA_SIZE,596 IntTab(cluster(x,y), MDMA_TGTID), false));512 maptabd.add(Segment(sd.str(), SEG_DMA_BASE + offset, SEG_DMA_SIZE, 513 IntTab(cluster(x,y), DMA_TGTID), false)); 597 514 598 515 std::ostringstream sh; 599 516 sh << "seg_memc_" << x << "_" << y; 600 maptabd.add(Segment(sh.str(), MEMC_BASE + offset, MEMC_SIZE,601 IntTab(cluster(x,y), MEMC_TGTID), true));517 maptabd.add(Segment(sh.str(), SEG_RAM_BASE + offset, SEG_RAM_SIZE, 518 IntTab(cluster(x,y), RAM_TGTID), true)); 602 519 603 520 if ( cluster(x,y) == cluster_io_id ) 604 521 { 605 maptabd.add(Segment("seg_mtty", MTTY_BASE, MTTY_SIZE,606 IntTab(cluster(x,y), MTTY_TGTID), false));607 maptabd.add(Segment("seg_fbuf", FBUF_BASE, FBUF_SIZE,608 IntTab(cluster(x,y),FB UF_TGTID), false));609 maptabd.add(Segment("seg_bdev", BDEV_BASE, BDEV_SIZE,610 IntTab(cluster(x,y), BDEV_TGTID), false));611 maptabd.add(Segment("seg_brom", BROM_BASE, BROM_SIZE,612 IntTab(cluster(x,y), BROM_TGTID), true));613 maptabd.add(Segment("seg_mnic", MNIC_BASE, MNIC_SIZE,614 IntTab(cluster(x,y), MNIC_TGTID), false));615 maptabd.add(Segment("seg_cdma", CDMA_BASE, CDMA_SIZE,616 IntTab(cluster(x,y),C DMA_TGTID), false));617 maptabd.add(Segment("seg_simh", S IMH_BASE, SIMH_SIZE,618 IntTab(cluster(x,y),SIM H_TGTID), false));522 maptabd.add(Segment("seg_mtty", SEG_TTY_BASE, SEG_TTY_SIZE, 523 IntTab(cluster(x,y),TTY_TGTID), false)); 524 maptabd.add(Segment("seg_fbuf", SEG_FBF_BASE, SEG_FBF_SIZE, 525 IntTab(cluster(x,y),FBF_TGTID), false)); 526 maptabd.add(Segment("seg_bdev", SEG_IOC_BASE, SEG_IOC_SIZE, 527 IntTab(cluster(x,y),IOC_TGTID), false)); 528 maptabd.add(Segment("seg_brom", SEG_ROM_BASE, SEG_ROM_SIZE, 529 IntTab(cluster(x,y),ROM_TGTID), true)); 530 maptabd.add(Segment("seg_mnic", SEG_NIC_BASE, SEG_NIC_SIZE, 531 IntTab(cluster(x,y),NIC_TGTID), false)); 532 maptabd.add(Segment("seg_cdma", SEG_CMA_BASE, SEG_CMA_SIZE, 533 IntTab(cluster(x,y),CMA_TGTID), false)); 534 maptabd.add(Segment("seg_simh", SEG_SIM_BASE, SEG_SIM_SIZE, 535 IntTab(cluster(x,y),SIM_TGTID), false)); 619 536 } 620 537 } … … 624 541 // external network 625 542 MappingTable maptabx(vci_address_width, 626 IntTab(x_width +y_width),627 IntTab(x_width +y_width),543 IntTab(x_width + y_width), 544 IntTab(x_width + y_width), 628 545 0xFFFF000000ULL); 629 546 … … 634 551 635 552 sc_uint<vci_address_width> offset; 636 offset = (sc_uint<vci_address_width>) cluster(x,y)553 offset = (sc_uint<vci_address_width>) cluster(x,y) 637 554 << (vci_address_width - x_width - y_width); 638 555 … … 640 557 sh << "x_seg_memc_" << x << "_" << y; 641 558 642 maptabx.add(Segment(sh.str(), MEMC_BASE + offset,643 MEMC_SIZE, IntTab(cluster(x,y)), false));559 maptabx.add(Segment(sh.str(), SEG_RAM_BASE + offset, 560 SEG_RAM_SIZE, IntTab(cluster(x,y)), false)); 644 561 } 645 562 } … … 655 572 // Horizontal inter-clusters DSPIN signals 656 573 DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_inc = 657 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", X_SIZE -1, Y_SIZE);574 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", X_SIZE - 1, Y_SIZE); 658 575 DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_dec = 659 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", X_SIZE -1, Y_SIZE);576 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", X_SIZE - 1, Y_SIZE); 660 577 661 578 DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_inc = 662 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", X_SIZE -1, Y_SIZE);579 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", X_SIZE - 1, Y_SIZE); 663 580 DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_dec = 664 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", X_SIZE -1, Y_SIZE);581 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", X_SIZE - 1, Y_SIZE); 665 582 666 583 DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_inc = 667 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_inc", X_SIZE- 1, Y_SIZE);584 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_inc", X_SIZE- 1 , Y_SIZE); 668 585 DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_dec = 669 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_dec", X_SIZE -1, Y_SIZE);586 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_dec", X_SIZE - 1, Y_SIZE); 670 587 671 588 DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_inc = 672 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_inc", X_SIZE -1, Y_SIZE);589 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_inc", X_SIZE - 1, Y_SIZE); 673 590 DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_dec = 674 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_dec", X_SIZE -1, Y_SIZE);591 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_dec", X_SIZE - 1, Y_SIZE); 675 592 676 593 DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_inc = 677 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_inc", X_SIZE -1, Y_SIZE);594 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_inc", X_SIZE - 1, Y_SIZE); 678 595 DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_dec = 679 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_dec", X_SIZE -1, Y_SIZE);596 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_dec", X_SIZE - 1, Y_SIZE); 680 597 681 598 // Vertical inter-clusters DSPIN signals 682 599 DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_inc = 683 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", X_SIZE, Y_SIZE -1);600 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", X_SIZE, Y_SIZE - 1); 684 601 DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_dec = 685 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", X_SIZE, Y_SIZE -1);602 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", X_SIZE, Y_SIZE - 1); 686 603 687 604 DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_inc = 688 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", X_SIZE, Y_SIZE -1);605 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", X_SIZE, Y_SIZE - 1); 689 606 DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_dec = 690 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", X_SIZE, Y_SIZE -1);607 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", X_SIZE, Y_SIZE - 1); 691 608 692 609 DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_inc = 693 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_inc", X_SIZE, Y_SIZE -1);610 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_inc", X_SIZE, Y_SIZE - 1); 694 611 DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_dec = 695 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_dec", X_SIZE, Y_SIZE -1);612 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_dec", X_SIZE, Y_SIZE - 1); 696 613 697 614 DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_inc = 698 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_inc", X_SIZE, Y_SIZE -1);615 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_inc", X_SIZE, Y_SIZE - 1); 699 616 DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_dec = 700 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_dec", X_SIZE, Y_SIZE -1);617 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_dec", X_SIZE, Y_SIZE - 1); 701 618 702 619 DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_inc = 703 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_inc", X_SIZE, Y_SIZE -1);620 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_inc", X_SIZE, Y_SIZE - 1); 704 621 DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_dec = 705 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_dec", X_SIZE, Y_SIZE -1);622 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_dec", X_SIZE, Y_SIZE - 1); 706 623 707 624 // Mesh boundaries DSPIN signals (Most of those signals are not used...) … … 787 704 y_width, 788 705 vci_srcid_width - x_width - y_width, // l_id width, 789 MEMC_TGTID,790 X ICU_TGTID,791 MDMA_TGTID,792 FB UF_TGTID,793 MTTY_TGTID,794 BROM_TGTID,795 MNIC_TGTID,796 C DMA_TGTID,797 BDEV_TGTID,798 SIM H_TGTID,706 RAM_TGTID, 707 XCU_TGTID, 708 DMA_TGTID, 709 FBF_TGTID, 710 TTY_TGTID, 711 ROM_TGTID, 712 NIC_TGTID, 713 CMA_TGTID, 714 IOC_TGTID, 715 SIM_TGTID, 799 716 MEMC_WAYS, 800 717 MEMC_SETS, … … 806 723 XRAM_LATENCY, 807 724 (cluster(x,y) == cluster_io_id), 808 FB UF_X_SIZE,809 FB UF_Y_SIZE,725 FBF_X_SIZE, 726 FBF_Y_SIZE, 810 727 disk_name, 811 728 BDEV_SECTOR_SIZE, … … 1138 1055 for (size_t y = 0; y < Y_SIZE ; y++){ 1139 1056 for (int proc = 0; proc < NB_PROCS_MAX; proc++) { 1140 1141 1057 clusters[x][y]->proc[proc]->print_trace(); 1142 1058 std::ostringstream proc_signame;
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