Index: trunk/platforms/tsar_generic_iob/arch_info.py
===================================================================
--- trunk/platforms/tsar_generic_iob/arch_info.py	(revision 1046)
+++ trunk/platforms/tsar_generic_iob/arch_info.py	(revision 1050)
@@ -29,5 +29,4 @@
 #  - nb_ttys        : number of TTY channels (can be from 1 to 8)
 #  - nb_nics        : number of NIC channels (from 1 to 2)
-#  - nb_cmas        : number of CMA channels (from 1 to 4)
 #  - fbf_width      : frame_buffer width = frame_buffer heigth
 #  - ioc_type       : can be 'IOC_BDV','IOC_HBA','IOC_SDC', 'IOC_SPI','NONE'
@@ -35,4 +34,5 @@
 #  - io_cxy         : IO cluster identifier
 #  - boot_cxy       : boot cluster identifier
+#  - cache_line     : number of bytes in cache line (in 16,32,64)
 #
 #  The following parameters are imposed by the "tsar_generic_iob" architecture:
@@ -51,10 +51,10 @@
           nb_ttys       = 1,
           nb_nics       = 1, 
-          nb_cmas       = 2,
           fbf_width     = 128,
           ioc_type      = 'IOC_BDV',
           mwr_type      = 'MWR_CPY',
           io_cxy        = 0,
-          boot_cxy      = 0 ):
+          boot_cxy      = 0, 
+          cache_line    = 64):
 
     ### architecture constants
@@ -81,6 +81,4 @@
     assert( (nb_nics >= 1) and (nb_nics <= 2) )
 
-    assert( (nb_cmas >= 1) and (nb_cmas <= 4) )
-
     assert( ioc_type in ['IOC_BDV','IOC_HBA','IOC_SDC','IOC_SPI','IOC_RDK'] )
 
@@ -90,4 +88,6 @@
 
     assert( ((boot_cxy >> y_width) < x_size) and ((boot_cxy & ((1<<y_width)-1)) < y_size) )
+
+    assert( (cache_line == 16) or (cache_line == 32) or (cache_line == 64)  )
  
     ### define platform name
@@ -98,5 +98,5 @@
 
     ram_base = 0x0000000000
-    ram_size = 0x4000000                   # 64 Mbytes
+    ram_size = 0x800000                    # 8 Mbytes
 
     xcu_base = 0x00B0000000
@@ -119,8 +119,5 @@
 
     nic_base  = 0x00B5000000
-    nic_size  = 0x80000                    # 512 kbytes
-
-    cma_base  = 0x00B6000000
-    cma_size  = 0x1000 * nb_cmas           # 4 kbytes * nb_cmas
+    nic_size  = 0x4000                     # 16 kbytes
 
     fbf_base  = 0x00B7000000
@@ -151,4 +148,5 @@
                       io_cxy         = io_cxy,          
                       boot_cxy       = boot_cxy,
+                      cache_line     = cache_line,
                       reset_address  = rom_base, 
                       p_width        = p_width )
@@ -163,21 +161,23 @@
             offset = cxy << (paddr_width - x_width - y_width)
 
-            # build devices
-            ram = archi.addDevice( ptype    = 'RAM' , 
+            # define internal devices
+            ram = archi.addDevice( ptype    = 'RAM_SCL' , 
                                    base     = ram_base + offset, 
                                    size     = ram_size )
 
-            xcu = archi.addDevice( ptype    = 'XCU', 
+            xcu = archi.addDevice( ptype    = 'ICU_XCU', 
                                    base     = xcu_base + offset, 
                                    size     = xcu_size,
-                                   channels = nb_cores * irqs_per_core, 
+                                   channels = 1, 
                                    arg0     = 16, 
                                    arg1     = 16,
-                                   arg2     = 16 )
-
-            mmc = archi.addDevice( ptype    = 'MMC',
+                                   arg2     = 16,
+                                   arg3     = 16 )
+
+            mmc = archi.addDevice( ptype    = 'MMC_TSR',
                                    base     = mmc_base + offset,
                                    size     = mmc_size )
-            archi.addIrq( dstdev = xcu, port = 0, srcdev = mmc, isrtype = 'ISR_MMC' )
+
+            archi.addIrq( dstdev = xcu, port = 0, srcdev = mmc )
 
             if ( mwr_type == 'MWR_GCD' ):
@@ -189,5 +189,5 @@
                                        arg2  = 1, 
                                        arg3  = 0 )
-                archi.addIrq( dstdev = xcu, port = 1, srcdev = mwr, isrtype = 'ISR_MWR' )
+                archi.addIrq( dstdev = xcu, port = 1, srcdev = mwr )
 
             if ( mwr_type == 'MWR_DCT' ):
@@ -199,5 +199,5 @@
                                        arg2  = 1, 
                                        arg3  = 0 )
-                archi.addIrq( dstdev = xcu, port = 1, srcdev = mwr, isrtype = 'ISR_MWR' )
+                archi.addIrq( dstdev = xcu, port = 1, srcdev = mwr )
 
             if ( mwr_type == 'MWR_CPY' ):
@@ -209,9 +209,10 @@
                                        arg2  = 1, 
                                        arg3  = 0 )
-                archi.addIrq( dstdev = xcu, port = 1, srcdev = mwr, isrtype = 'ISR_MWR' )
-
+                archi.addIrq( dstdev = xcu, port = 1, srcdev = mwr )
+
+            # define external devices
             if( cxy == io_cxy ):
 
-                iob = archi.addDevice( ptype    = 'IOB', 
+                iob = archi.addDevice( ptype    = 'IOB_TSR', 
                                        base     = iob_base + offset,
                                        size     = iob_size )
@@ -221,20 +222,15 @@
                                        size     = ioc_size )
 
-                tty = archi.addDevice( ptype    = 'TTY',
+                tty = archi.addDevice( ptype    = 'TXT_TTY',
                                        base     = tty_base + offset,
                                        size     = tty_size, 
                                        channels = nb_ttys )
 
-                nic = archi.addDevice( ptype    = 'NIC',
+                nic = archi.addDevice( ptype    = 'NIC_CBF',
                                        base     = nic_base + offset, 
                                        size     = nic_size, 
                                        channels = nb_nics )
 
-                cma = archi.addDevice( ptype    = 'CMA',
-                                       base     = cma_base + offset,
-                                       size     = cma_size, 
-                                       channels = nb_cmas )
-
-                fbf = archi.addDevice( ptype    = 'FBF',
+                fbf = archi.addDevice( ptype    = 'FBF_SCL',
                                        base     = fbf_base + offset,
                                        size     = fbf_size, 
@@ -242,41 +238,38 @@
                                        arg1     = fbf_width )
 
-                rom = archi.addDevice( ptype    = 'ROM',
+                rom = archi.addDevice( ptype    = 'ROM_SCL',
                                        base     = rom_base + offset, 
                                        size     = rom_size )
 
-                pic = archi.addDevice( ptype    ='PIC',
+                pic = archi.addDevice( ptype    ='PIC_TSR',
                                        base     = pic_base + offset,
                                        size     = pic_size, 
                                        arg0     = 32 )
 
-                if   ( ioc_type == 'IOC_BDV' ): isr_ioc = 'ISR_BDV'
-                elif ( ioc_type == 'IOC_HBA' ): isr_ioc = 'ISR_HBA'
-                elif ( ioc_type == 'IOC_SDC' ): isr_ioc = 'ISR_SDC'
-                elif ( ioc_type == 'IOC_SPI' ): isr_ioc = 'ISR_SPI'
-                else                          : isr_ioc = 'ISR_DEFAULT'
-
-                archi.addIrq( dstdev = pic, port = 0 , srcdev = nic, isrtype = 'ISR_NIC_RX', channel = 0 )
-                archi.addIrq( dstdev = pic, port = 1 , srcdev = nic, isrtype = 'ISR_NIC_RX', channel = 1 )
-                archi.addIrq( dstdev = pic, port = 2 , srcdev = nic, isrtype = 'ISR_NIC_TX', channel = 0 )
-                archi.addIrq( dstdev = pic, port = 3 , srcdev = nic, isrtype = 'ISR_NIC_TX', channel = 1 )
-                archi.addIrq( dstdev = pic, port = 4 , srcdev = cma, isrtype = 'ISR_CMA'   , channel = 0 )
-                archi.addIrq( dstdev = pic, port = 5 , srcdev = cma, isrtype = 'ISR_CMA'   , channel = 1 )
-                archi.addIrq( dstdev = pic, port = 6 , srcdev = cma, isrtype = 'ISR_CMA'   , channel = 2 )
-                archi.addIrq( dstdev = pic, port = 7 , srcdev = cma, isrtype = 'ISR_CMA'   , channel = 3 )
-                archi.addIrq( dstdev = pic, port = 8 , srcdev = ioc, isrtype = isr_ioc     , channel = 0 )
-                archi.addIrq( dstdev = pic, port = 16, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 0 )
-                archi.addIrq( dstdev = pic, port = 17, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 1 )
-                archi.addIrq( dstdev = pic, port = 18, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 2 )
-                archi.addIrq( dstdev = pic, port = 19, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 3 )
-                archi.addIrq( dstdev = pic, port = 20, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 4 )
-                archi.addIrq( dstdev = pic, port = 21, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 5 )
-                archi.addIrq( dstdev = pic, port = 22, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 6 )
-                archi.addIrq( dstdev = pic, port = 23, srcdev = tty, isrtype = 'ISR_TTY_RX', channel = 7 )
-
-            # build cores
+                archi.addIrq( dstdev = pic, port = 0 , srcdev = nic, channel = 0 , is_rx = True )
+                archi.addIrq( dstdev = pic, port = 1 , srcdev = nic, channel = 1 , is_rx = True )
+                archi.addIrq( dstdev = pic, port = 2 , srcdev = nic, channel = 2 , is_rx = True )
+                archi.addIrq( dstdev = pic, port = 3 , srcdev = nic, channel = 3 , is_rx = True )
+
+                archi.addIrq( dstdev = pic, port = 4 , srcdev = nic, channel = 0 , is_rx = False )
+                archi.addIrq( dstdev = pic, port = 5 , srcdev = nic, channel = 1 , is_rx = False )
+                archi.addIrq( dstdev = pic, port = 6 , srcdev = nic, channel = 2 , is_rx = False )
+                archi.addIrq( dstdev = pic, port = 7 , srcdev = nic, channel = 3 , is_rx = False )
+
+                archi.addIrq( dstdev = pic, port = 12, srcdev = ioc )
+
+                archi.addIrq( dstdev = pic, port = 16, srcdev = tty, channel = 0 , is_rx = True )
+                archi.addIrq( dstdev = pic, port = 17, srcdev = tty, channel = 1 , is_rx = True )
+                archi.addIrq( dstdev = pic, port = 18, srcdev = tty, channel = 2 , is_rx = True )
+                archi.addIrq( dstdev = pic, port = 19, srcdev = tty, channel = 3 , is_rx = True )
+                archi.addIrq( dstdev = pic, port = 20, srcdev = tty, channel = 4 , is_rx = True )
+                archi.addIrq( dstdev = pic, port = 21, srcdev = tty, channel = 5 , is_rx = True )
+                archi.addIrq( dstdev = pic, port = 22, srcdev = tty, channel = 6 , is_rx = True )
+                archi.addIrq( dstdev = pic, port = 23, srcdev = tty, channel = 7 , is_rx = True )
+
+            # define cores
             for p in xrange ( nb_cores ):
-                core = archi.addCore( (x<<(y_width+p_width)) + (y<<p_width) + p,  # hardware identifier
-                                      (x<<y_width) + y,                           # cluster identifier
+                core = archi.addCore( (x<<(y_width+p_width)) + (y<<p_width) + p,  # hardware id
+                                      (x<<y_width) + y,                           # cluster 
                                        p )                                        # local index
 
