Index: trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp
===================================================================
--- trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp	(revision 83)
+++ trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp	(revision 116)
@@ -38,177 +38,174 @@
 namespace soclib { namespace caba {
 
-#ifdef DEBUG_VCI_MEM_CACHE 
   const char *tgt_cmd_fsm_str[] = {
-    "TGT_CMD_IDLE",
-    "TGT_CMD_READ",
+    "TGT_CMD_IDLE    ",
+    "TGT_CMD_READ    ",
     "TGT_CMD_READ_EOP",
-    "TGT_CMD_WRITE",
-    "TGT_CMD_ATOMIC",
+    "TGT_CMD_WRITE   ",
+    "TGT_CMD_ATOMIC  ",
   };
   const char *tgt_rsp_fsm_str[] = {
-    "TGT_RSP_READ_IDLE",
-    "TGT_RSP_WRITE_IDLE",
-    "TGT_RSP_LLSC_IDLE",
-    "TGT_RSP_XRAM_IDLE",
-    "TGT_RSP_INIT_IDLE",
+    "TGT_RSP_READ_IDLE   ",
+    "TGT_RSP_WRITE_IDLE  ",
+    "TGT_RSP_LLSC_IDLE   ",
+    "TGT_RSP_XRAM_IDLE   ",
+    "TGT_RSP_INIT_IDLE   ",
     "TGT_RSP_CLEANUP_IDLE",
-    "TGT_RSP_READ",
-    "TGT_RSP_WRITE",
-    "TGT_RSP_LLSC",
-    "TGT_RSP_XRAM",
-    "TGT_RSP_INIT",
-    "TGT_RSP_CLEANUP",
+    "TGT_RSP_READ        ",
+    "TGT_RSP_WRITE       ",
+    "TGT_RSP_LLSC        ",
+    "TGT_RSP_XRAM        ",
+    "TGT_RSP_INIT        ",
+    "TGT_RSP_CLEANUP     ",
   };
   const char *init_cmd_fsm_str[] = {
-    "INIT_CMD_INVAL_IDLE",
-    "INIT_CMD_INVAL_NLINE",
-    "INIT_CMD_XRAM_BRDCAST",
-    "INIT_CMD_UPDT_IDLE",
-    "INIT_CMD_WRITE_BRDCAST",
-    "INIT_CMD_UPDT_NLINE",
-    "INIT_CMD_UPDT_INDEX",
-    "INIT_CMD_UPDT_DATA",
-    "INIT_CMD_SC_UPDT_IDLE",
-    "INIT_CMD_SC_BRDCAST",
-    "INIT_CMD_SC_UPDT_NLINE",
-    "INIT_CMD_SC_UPDT_INDEX",
-    "INIT_CMD_SC_UPDT_DATA",
+    "INIT_CMD_INVAL_IDLE       ",
+    "INIT_CMD_INVAL_NLINE      ",
+    "INIT_CMD_XRAM_BRDCAST     ",
+    "INIT_CMD_UPDT_IDLE        ",
+    "INIT_CMD_WRITE_BRDCAST    ",
+    "INIT_CMD_UPDT_NLINE       ",
+    "INIT_CMD_UPDT_INDEX       ",
+    "INIT_CMD_UPDT_DATA        ",
+    "INIT_CMD_SC_UPDT_IDLE     ",
+    "INIT_CMD_SC_BRDCAST       ",
+    "INIT_CMD_SC_UPDT_NLINE    ",
+    "INIT_CMD_SC_UPDT_INDEX    ",
+    "INIT_CMD_SC_UPDT_DATA     ",
     "INIT_CMD_SC_UPDT_DATA_HIGH",
   };
   const char *init_rsp_fsm_str[] = {
-    "INIT_RSP_IDLE",
-    "INIT_RSP_UPT_LOCK",
+    "INIT_RSP_IDLE     ",
+    "INIT_RSP_UPT_LOCK ",
     "INIT_RSP_UPT_CLEAR",
-    "INIT_RSP_END",
+    "INIT_RSP_END      ",
   };
   const char *read_fsm_str[] = {
-    "READ_IDLE",
-    "READ_DIR_LOCK",
-    "READ_DIR_HIT",
-    "READ_HEAP_LOCK",
+    "READ_IDLE      ",
+    "READ_DIR_LOCK  ",
+    "READ_DIR_HIT   ",
+    "READ_HEAP_LOCK ",
     "READ_HEAP_WRITE",
     "READ_HEAP_ERASE",
-    "READ_HEAP_LAST",
-    "READ_RSP",
-    "READ_TRT_LOCK",
-    "READ_TRT_SET",
-    "READ_XRAM_REQ",
+    "READ_HEAP_LAST ",
+    "READ_RSP       ",
+    "READ_TRT_LOCK  ",
+    "READ_TRT_SET   ",
+    "READ_XRAM_REQ  ",
   };
   const char *write_fsm_str[] = {
-    "WRITE_IDLE",
-    "WRITE_NEXT",
-    "WRITE_DIR_LOCK",
-    "WRITE_DIR_HIT_READ",
-    "WRITE_DIR_HIT",
-    "WRITE_UPT_LOCK",
-    "WRITE_HEAP_LOCK",
-    "WRITE_UPT_REQ",
-    "WRITE_UPDATE",
-    "WRITE_UPT_DEC",
-    "WRITE_RSP",
-    "WRITE_TRT_LOCK",
-    "WRITE_TRT_DATA",
-    "WRITE_TRT_SET",
-    "WRITE_WAIT",
-    "WRITE_XRAM_REQ",
+    "WRITE_IDLE          ",
+    "WRITE_NEXT          ",
+    "WRITE_DIR_LOCK      ",
+    "WRITE_DIR_HIT_READ  ",
+    "WRITE_DIR_HIT       ",
+    "WRITE_UPT_LOCK      ",
+    "WRITE_HEAP_LOCK     ",
+    "WRITE_UPT_REQ       ",
+    "WRITE_UPDATE        ",
+    "WRITE_UPT_DEC       ",
+    "WRITE_RSP           ",
+    "WRITE_TRT_LOCK      ",
+    "WRITE_TRT_DATA      ",
+    "WRITE_TRT_SET       ",
+    "WRITE_WAIT          ",
+    "WRITE_XRAM_REQ      ",
     "WRITE_TRT_WRITE_LOCK",
-    "WRITE_INVAL_LOCK",
-    "WRITE_DIR_INVAL",
-    "WRITE_INVAL",
-    "WRITE_XRAM_SEND",
+    "WRITE_INVAL_LOCK    ",
+    "WRITE_DIR_INVAL     ",
+    "WRITE_INVAL         ",
+    "WRITE_XRAM_SEND     ",
   };
   const char *ixr_rsp_fsm_str[] = {
-    "IXR_RSP_IDLE",
-    "IXR_RSP_ACK",
+    "IXR_RSP_IDLE     ",
+    "IXR_RSP_ACK      ",
     "IXR_RSP_TRT_ERASE",
-    "IXR_RSP_TRT_READ",
+    "IXR_RSP_TRT_READ ",
   };
   const char *xram_rsp_fsm_str[] = {
-    "XRAM_RSP_IDLE",
-    "XRAM_RSP_TRT_COPY",
-    "XRAM_RSP_TRT_DIRTY",
-    "XRAM_RSP_DIR_LOCK",
-    "XRAM_RSP_DIR_UPDT",
-    "XRAM_RSP_DIR_RSP",
-    "XRAM_RSP_INVAL_LOCK",
-    "XRAM_RSP_INVAL_WAIT",
-    "XRAM_RSP_INVAL",
+    "XRAM_RSP_IDLE       ",
+    "XRAM_RSP_TRT_COPY   ",
+    "XRAM_RSP_TRT_DIRTY  ",
+    "XRAM_RSP_DIR_LOCK   ",
+    "XRAM_RSP_DIR_UPDT   ",
+    "XRAM_RSP_DIR_RSP    ",
+    "XRAM_RSP_INVAL_LOCK ",
+    "XRAM_RSP_INVAL_WAIT ",
+    "XRAM_RSP_INVAL      ",
     "XRAM_RSP_WRITE_DIRTY",
-    "XRAM_RSP_HEAP_ERASE",
-    "XRAM_RSP_HEAP_LAST",
+    "XRAM_RSP_HEAP_ERASE ",
+    "XRAM_RSP_HEAP_LAST  ",
   };
   const char *ixr_cmd_fsm_str[] = {
-    "IXR_CMD_READ_IDLE",
-    "IXR_CMD_WRITE_IDLE",
-    "IXR_CMD_LLSC_IDLE",
-    "IXR_CMD_XRAM_IDLE",
-    "IXR_CMD_READ_NLINE",
-    "IXR_CMD_WRITE_NLINE",
-    "IXR_CMD_LLSC_NLINE",
-    "IXR_CMD_XRAM_DATA",
+    "IXR_CMD_READ_IDLE   ",
+    "IXR_CMD_WRITE_IDLE  ",
+    "IXR_CMD_LLSC_IDLE   ",
+    "IXR_CMD_XRAM_IDLE   ",
+    "IXR_CMD_READ_NLINE  ",
+    "IXR_CMD_WRITE_NLINE ",
+    "IXR_CMD_LLSC_NLINE  ",
+    "IXR_CMD_XRAM_DATA   ",
   };
   const char *llsc_fsm_str[] = {
-    "LLSC_IDLE",
-    "SC_DIR_LOCK",
-    "SC_DIR_HIT_READ",
+    "LLSC_IDLE       ",
+    "SC_DIR_LOCK     ",
+    "SC_DIR_HIT_READ ",
     "SC_DIR_HIT_WRITE",
-    "SC_UPT_LOCK",
-    "SC_WAIT",
-    "SC_HEAP_LOCK",
-    "SC_UPT_REQ",
-    "SC_UPDATE",
-    "SC_TRT_LOCK",
-    "SC_INVAL_LOCK",
-    "SC_DIR_INVAL",
-    "SC_INVAL",
-    "SC_XRAM_SEND",
-    "SC_RSP_FALSE",
-    "SC_RSP_TRUE",
-    "LLSC_TRT_LOCK",
-    "LLSC_TRT_SET",
-    "LLSC_XRAM_REQ",
+    "SC_UPT_LOCK     ",
+    "SC_WAIT         ",
+    "SC_HEAP_LOCK    ",
+    "SC_UPT_REQ      ",
+    "SC_UPDATE       ",
+    "SC_TRT_LOCK     ",
+    "SC_INVAL_LOCK   ",
+    "SC_DIR_INVAL    ",
+    "SC_INVAL        ",
+    "SC_XRAM_SEND    ",
+    "SC_RSP_FALSE    ",
+    "SC_RSP_TRUE     ",
+    "LLSC_TRT_LOCK   ",
+    "LLSC_TRT_SET    ",
+    "LLSC_XRAM_REQ   ",
   };
   const char *cleanup_fsm_str[] = {
-    "CLEANUP_IDLE",
-    "CLEANUP_DIR_LOCK",
-    "CLEANUP_DIR_WRITE",
-    "CLEANUP_HEAP_LOCK",
+    "CLEANUP_IDLE       ",
+    "CLEANUP_DIR_LOCK   ",
+    "CLEANUP_DIR_WRITE  ",
+    "CLEANUP_HEAP_LOCK  ",
     "CLEANUP_HEAP_SEARCH",
-    "CLEANUP_HEAP_CLEAN",
-    "CLEANUP_HEAP_FREE",
-    "CLEANUP_UPT_LOCK",
-    "CLEANUP_UPT_WRITE",
-    "CLEANUP_WRITE_RSP",
-    "CLEANUP_RSP",
+    "CLEANUP_HEAP_CLEAN ",
+    "CLEANUP_HEAP_FREE  ",
+    "CLEANUP_UPT_LOCK   ",
+    "CLEANUP_UPT_WRITE  ",
+    "CLEANUP_WRITE_RSP  ",
+    "CLEANUP_RSP        ",
   };
   const char *alloc_dir_fsm_str[] = {
-    "ALLOC_DIR_READ",
-    "ALLOC_DIR_WRITE",
-    "ALLOC_DIR_LLSC",
-    "ALLOC_DIR_CLEANUP",
+    "ALLOC_DIR_READ    ",
+    "ALLOC_DIR_WRITE   ",
+    "ALLOC_DIR_LLSC    ",
+    "ALLOC_DIR_CLEANUP ",
     "ALLOC_DIR_XRAM_RSP",
   };
   const char *alloc_trt_fsm_str[] = {
-    "ALLOC_TRT_READ",
-    "ALLOC_TRT_WRITE",
-    "ALLOC_TRT_LLSC",
+    "ALLOC_TRT_READ    ",
+    "ALLOC_TRT_WRITE   ",
+    "ALLOC_TRT_LLSC    ",
     "ALLOC_TRT_XRAM_RSP",
-    "ALLOC_TRT_IXR_RSP",
+    "ALLOC_TRT_IXR_RSP ",
   };
   const char *alloc_upt_fsm_str[] = {
-    "ALLOC_UPT_WRITE",
+    "ALLOC_UPT_WRITE   ",
     "ALLOC_UPT_XRAM_RSP",
     "ALLOC_UPT_INIT_RSP",
-    "ALLOC_UPT_CLEANUP",
+    "ALLOC_UPT_CLEANUP ",
   };
   const char *alloc_heap_fsm_str[] = {
-    "ALLOC_HEAP_READ",
-    "ALLOC_HEAP_WRITE",
-    "ALLOC_HEAP_LLSC",
-    "ALLOC_HEAP_CLEANUP",
+    "ALLOC_HEAP_READ    ",
+    "ALLOC_HEAP_WRITE   ",
+    "ALLOC_HEAP_LLSC    ",
+    "ALLOC_HEAP_CLEANUP ",
     "ALLOC_HEAP_XRAM_RSP",
   };
-
-#endif
 
 #define tmpl(x) template<typename vci_param> x VciMemCacheV4<vci_param>
@@ -322,5 +319,5 @@
 
       // Set the broadcast address with Xmin,Xmax,Ymin,Ymax set to maximum
-      broadcast_addr = 0x3 | (0x7C1F << (vci_param::N-20));
+      m_broadcast_address = 0x3 | (0x7C1F << (vci_param::N-20));
 
       // Get the segments associated to the MemCache 
@@ -396,4 +393,19 @@
 
     } // end constructor
+
+  //////////////////////////////////////////////////
+  // This function prints a trace of internal states
+  //////////////////////////////////////////////////
+
+  tmpl(void)::print_trace()
+  {
+    std::cout << "MEM_CACHE " << name() << std::endl;
+    std::cout << " / " << tgt_cmd_fsm_str[r_tgt_cmd_fsm] 
+              << " / " << read_fsm_str[r_read_fsm]
+              << " / " << write_fsm_str[r_write_fsm]
+              << " / " << tgt_rsp_fsm_str[r_tgt_rsp_fsm] 
+              << " / " << init_cmd_fsm_str[r_init_cmd_fsm]
+              << " / " << init_rsp_fsm_str[r_init_rsp_fsm] << std::endl;
+  }
 
   /////////////////////////////////////////
@@ -607,5 +619,4 @@
 #endif
 
-
     ////////////////////////////////////////////////////////////////////////////////////
     //		TGT_CMD FSM
@@ -630,6 +641,6 @@
         {
           if ( p_vci_tgt.cmdval ) {
-            assert( (p_vci_tgt.srcid.read() < m_initiators)
-                && "VCI_MEM_CACHE error in VCI_MEM_CACHE : The received SRCID is larger than the number of initiators");
+            assert( (p_vci_tgt.srcid.read() < m_initiators) && 
+            "VCI_MEM_CACHE error in direct request : received SRCID is larger than the number of initiators");
 
             bool reached = false;
@@ -646,5 +657,5 @@
             if ( !reached ) 
             { 
-              std::cout << "VCI_MEM_CACHE Out of segment access in VCI_MEM_CACHE" << std::endl;
+              std::cout << "VCI_MEM_CACHE Out of segment access in " << name() << std::endl;
               std::cout << "Faulty address = " << std::hex << (addr_t)(p_vci_tgt.address.read()) << std::endl;
               std::cout << "Faulty initiator = " << std::dec << p_vci_tgt.srcid.read() << std::endl;
@@ -2315,8 +2326,8 @@
       case CLEANUP_IDLE:
         {
-
           if ( p_vci_tgt_cleanup.cmdval.read() ) {
             assert( (p_vci_tgt_cleanup.srcid.read() < m_initiators) &&
-                "VCI_MEM_CACHE error in VCI_MEM_CACHE in the CLEANUP network : The received SRCID is larger than the number of initiators");
+            "VCI_MEM_CACHE error in a cleanup request : received SRCID is larger than the number of initiators");
+
             bool reached = false;
             for ( size_t index = 0 ; index < ncseg && !reached ; index++ ){
@@ -2325,8 +2336,9 @@
               }
             }
+            // only write request to a mapped address that are not broadcast are handled
             if ( (p_vci_tgt_cleanup.cmd.read() == vci_param::CMD_WRITE) &&
-                (((addr_t)(p_vci_tgt_cleanup.address.read())&0x3) != 0x3) &&
-                reached) {
-
+                 ((p_vci_tgt_cleanup.address.read() & 0x3) == 0) &&
+                 reached) 
+            {
               m_cpt_cleanup++;
 
@@ -2575,5 +2587,5 @@
           if( r_alloc_upt_fsm.read() == ALLOC_UPT_CLEANUP )
           {
-            size_t index;
+            size_t index = 0;
             bool hit_inval;
             hit_inval = m_update_tab.search_inval(r_cleanup_nline.read(),index);
@@ -4106,5 +4118,4 @@
     // Command signals on the p_vci_ixr port
     ////////////////////////////////////////////////////////////
-
 
     p_vci_ixr.be      = 0xF;
@@ -4333,5 +4344,5 @@
       case INIT_CMD_XRAM_BRDCAST:
         p_vci_ini.cmdval  = true;
-        p_vci_ini.address = broadcast_addr;
+        p_vci_ini.address = m_broadcast_address;
         p_vci_ini.wdata   = (uint32_t)r_xram_rsp_to_init_cmd_nline.read();
         p_vci_ini.be      = ((r_xram_rsp_to_init_cmd_nline.read() >> 32) & 0x3);
@@ -4343,5 +4354,5 @@
       case INIT_CMD_WRITE_BRDCAST:
         p_vci_ini.cmdval  = true;
-        p_vci_ini.address = broadcast_addr;
+        p_vci_ini.address = m_broadcast_address;
         p_vci_ini.wdata   = (addr_t)r_write_to_init_cmd_nline.read();
         p_vci_ini.be      = ((r_write_to_init_cmd_nline.read() >> 32) & 0x3);
@@ -4398,5 +4409,5 @@
       case INIT_CMD_SC_BRDCAST:
         p_vci_ini.cmdval  = true;
-        p_vci_ini.address = broadcast_addr;
+        p_vci_ini.address = m_broadcast_address;
         p_vci_ini.wdata   = (addr_t)r_llsc_to_init_cmd_nline.read();
         p_vci_ini.be      = ((r_llsc_to_init_cmd_nline.read() >> 32) & 0x3);
