Changeset 128
- Timestamp:
- Jan 18, 2011, 6:37:31 PM (13 years ago)
- Location:
- trunk/modules/vci_synthetic_initator/caba/sources
- Files:
-
- 2 edited
-
include/vci_synthetic_initiator.h (modified) (4 diffs)
-
src/vci_synthetic_initiator.cpp (modified) (10 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_synthetic_initator/caba/sources/include/vci_synthetic_initiator.h
r126 r128 57 57 58 58 59 /* States of the GENERATORfsm */59 /* States of the VCI CMD fsm */ 60 60 enum vci_fsm_state_e{ 61 61 VCI_IDLE, … … 64 64 }; 65 65 66 enum bc_ rsp_fsm_state_e{66 enum bc_fsm_state_e{ 67 67 BC_RSP_IDLE, 68 68 BC_RSP_WAIT_RSP … … 70 70 71 71 72 uint64_t m_cpt_cycles; // Counter of cycles73 72 74 73 … … 115 114 116 115 // Component attributes 117 const size_t m_length; // Number of words to write 118 const size_t m_rho; // Rate of packets in the network wanted 119 //const float m_rho; // Rate of packets in the network wanted 120 const size_t m_depth; // Fifo depth 121 const size_t m_xmesh; 122 const size_t m_ymesh; 123 const size_t m_bc_period; // Broadcast period, if no broadcast => 0 124 const size_t m_xmin; 125 const size_t m_xmax; 126 const size_t m_ymin; 127 const size_t m_ymax; 128 const size_t m_srcid; 129 static const int tab_size = 1 << vci_param::T; 116 const size_t m_length; // Number of words to write 117 const size_t m_rho; // offered load * 1000 118 const size_t m_depth; // Fifo depth 119 const size_t m_xmesh; 120 const size_t m_ymesh; 121 const size_t m_bc_period; // Broadcast period, if no broadcast => 0 122 const size_t m_xmin; 123 const size_t m_xmax; 124 const size_t m_ymin; 125 const size_t m_ymax; 126 const size_t m_srcid; 127 static const int m_tab_size = 1 << vci_param::T; 130 128 131 sc_signal<size_t> r_count; // Numbers of words sent132 sc_signal<size_t> r_npackets; // Total number of packets already sent133 sc_signal<uint64_t> r_start_latency1; // Start time of sending packet wanted134 sc_signal<uint64_t> r_start_latency2; // Start time of sending packet135 sc_signal<uint64_t> r_latency1; // Average latency wanted136 sc_signal<uint64_t> r_latency2; // Average latency137 sc_signal<addr_t> r_address_to_send; // Address to send the write command138 sc_signal<uint32_t> r_local_seed;139 sc_signal<int> r_id_to_send;140 129 141 sc_signal<uint64_t> r_start_latency_bc;142 sc_signal<uint64_t> r_latency_bc;143 sc_signal<uint64_t> r_nb_bc;130 // Fifo transmitting requests from the generator FSM to the VCI FSM 131 GenericFifo<uint64_t> r_date_fifo; 132 GenericFifo<bool> r_bc_fifo; 144 133 145 // Fifo transmitting date to the VCI FSM 146 GenericFifo<uint32_t> m_date_fifo; 134 // VCI CMD FSM 135 sc_signal<int> r_cmd_fsm; 136 sc_signal<addr_t> r_cmd_address; // Address for the single transaction 137 sc_signal<int> r_cmd_trdid; // TRDID for the single transaction 138 sc_signal<size_t> r_cmd_count; // Numbers of words sent 139 sc_signal<uint32_t> r_cmd_seed; // seed for reproducible address generation 147 140 148 sc_signal<int> r_cmd_fsm; 141 // Broadcast FSM 142 sc_signal<bool> r_bc_fsm; // FSM state 143 sc_signal<uint64_t> r_bc_date; // broadcast transaction requested date 144 sc_signal<uint32_t> r_bc_nrsp; // Expected number of responses for a broadcast command 145 146 // Pending transaction FSMs 147 sc_signal<bool>* r_pending_fsm; // FSM states 148 sc_signal<uint64_t>* r_pending_date; // single transaction requested date 149 149 150 sc_signal<int> r_bc_rsp_fsm; 151 152 sc_signal<size_t> r_index; 153 154 sc_signal<bool> r_broadcast_req; 155 156 sc_signal<bool> r_broadcast_rsp; 157 158 sc_signal<uint32_t> r_bc_nrsp; // Expected number of responses for a broadcast command 159 160 sc_signal<uint64_t> **r_req_id; 161 150 // Instrumentation registers 151 sc_signal<uint64_t> r_cpt_cycles; // Local time 152 sc_signal<uint64_t> r_cpt_period; // Number of cycles between 2 broadcast transactions 153 sc_signal<size_t> r_nb_single; // Total number of single transactions 154 sc_signal<uint64_t> r_latency_single; // Total cumulated latency for single transactions 155 sc_signal<size_t> r_nb_bc; // Total number of bc transactions 156 sc_signal<uint64_t> r_latency_bc; // Total cumulated latency for broadcast transactions 162 157 163 158 }; // end class VciSyntheticInitiator -
trunk/modules/vci_synthetic_initator/caba/sources/src/vci_synthetic_initiator.cpp
r127 r128 52 52 const soclib::common::IntTab &vci_index, 53 53 const uint32_t length, // Packet length (flit numbers) 54 const uint32_t rho, // Packets ratio on the network 55 // const float rho, // Packets ratio on the network 54 const uint32_t rho, // Offered load * 1000 56 55 const uint32_t depth, // Fifo depth 57 56 const uint32_t xmesh, … … 82 81 m_ymin(ymin), 83 82 m_ymax(ymax), 84 m_date_fifo("m_date_fifo", depth), 85 r_count ("r_count"), 86 r_npackets ("r_npackets"), 87 r_start_latency1 ("r_start_latency1"), 88 r_start_latency2 ("r_start_latency2"), 89 r_latency1 ("r_latency1"), 90 r_latency2 ("r_latency2"), 91 r_address_to_send ("r_address_to_send"), 92 r_local_seed ("r_local_seed"), 93 r_id_to_send ("r_id_to_send"), 94 r_start_latency_bc("r_start_latency_bc"), 95 r_latency_bc ("r_latency_bc"), 96 r_nb_bc ("r_nb_bc"), 97 r_cmd_fsm("r_cmd_fsm"), 83 r_date_fifo("r_date_fifo", depth), 84 r_type_fifo("r_type_fifo", depth), 85 r_cmd_fsm; ("r_count"), 98 86 r_bc_rsp_fsm("r_bc_rsp_fsm"), 99 87 r_index("r_index"), … … 161 149 << " : state_cmd_fsm = " << state_cmd_str[r_cmd_fsm] 162 150 << " : state_rsp_fsm = " << state_bc_rsp_str[r_bc_rsp_fsm] 163 << " Adresse to send : " << std::hex << r_ address_to_send.read()151 << " Adresse to send : " << std::hex << r_cmd_address.read() 164 152 << " Number of broadcast to receive : " << std::dec << r_bc_nrsp.read() 165 << " Number of packets sent : " << std::dec << r_n packets.read() << " " << r_id_to_send.read() << std::endl;153 << " Number of packets sent : " << std::dec << r_nb_single.read() << " " << r_id_to_send.read() << std::endl; 166 154 for(int i = 0; i < (1<<vci_param::T) ; i++){ 167 155 std::cout << "ID : " << i << " " << (uint64_t)(r_req_id[i][0].read()) << " " << (uint64_t)(r_req_id[i][1].read()) << std::endl; … … 173 161 ////////////////////////////////// 174 162 { 175 std::cout << name() << " : "<< std::dec << m_cpt_cycles << " cycles, " << r_n packets.read() << " packets sent" << std::endl;176 std::cout << ((double)r_latency1.read()/(double)r_n packets.read()) << " | " << ((double)r_latency2.read()/(double)r_npackets.read()) << std::endl;163 std::cout << name() << " : "<< std::dec << m_cpt_cycles << " cycles, " << r_nb_single.read() << " packets sent" << std::endl; 164 std::cout << ((double)r_latency1.read()/(double)r_nb_single.read()) << " | " << ((double)r_latency2.read()/(double)r_nb_single.read()) << std::endl; 177 165 if(m_bc_period) 178 166 std::cout << ((double)r_latency_bc.read()/(double)r_nb_bc.read()) << std::endl; … … 184 172 { 185 173 // RESET 186 if ( ! p_resetn.read() ) { 174 if ( ! p_resetn.read() ) 175 { 187 176 // Initializing seed for random numbers generation 177 188 178 #ifndef DETERMINISTIC 189 179 srand(time(NULL)); … … 192 182 // Initializing FSMs 193 183 r_cmd_fsm = VCI_IDLE; 194 195 r_bc_rsp_fsm = BC_RSP_IDLE;184 r_bc_fsm = BC_RSP_IDLE; 185 for(size_t i=0 ; i<m_tab_size ; i++) r_pending_fsm[i] = false; 196 186 197 187 // Initializing FIFOs 198 m_date_fifo.init(); 199 200 // Initializing the stats 201 r_latency1 = 0 ; 202 r_latency2 = 0 ; 203 // Activity counters 204 m_cpt_cycles = 0; 188 r_date_fifo.init(); 189 r_bc_fifo.init(); 190 191 // Initializing the instrumentation registers 192 r_latency_single = 0 ; 193 r_nb_single = 0; 194 r_latency_bc = 0 ; 195 r_nb_bc = 0; 196 r_cpt_cycles = 0; 197 r_cpt_period = 0; 205 198 206 r_start_latency_bc = 0; 207 r_latency_bc = 0; 208 r_nb_bc = 0; 209 r_id_to_send = -1; 210 211 r_broadcast_req = false; 212 213 r_broadcast_rsp = false; 214 215 r_bc_nrsp = 0; 216 r_count = 0; 217 r_npackets = 0; 218 r_start_latency1 = 0; 219 r_start_latency2 = 0; 220 r_address_to_send = 0; 221 r_local_seed = (uint32_t)m_srcid; 222 223 r_latency_bc = 0; 224 225 for(int i = 0; i < tab_size; i++){ 226 r_req_id[i][0] = 0; 227 r_req_id[i][1] = 0; 228 } 199 r_cmd_seed = (uint32_t)m_srcid; 229 200 230 201 return; 231 202 } 232 203 233 bool date_fifo_put = false; 234 bool date_fifo_get = false; 204 bool fifo_put = false; 205 bool fifo_get = false; 206 bool fifo_bc; 235 207 236 208 uint32_t m_local_seed ; 237 209 238 239 // FSM controling effective requests send 210 ////////////////// 211 // VCI CMD FSM 212 ////////////////// 240 213 switch ( r_cmd_fsm.read() ) { 241 //////////////////242 214 case VCI_IDLE: 243 215 { 244 if (m_date_fifo.rok()){ 245 if (r_broadcast_req.read() && !r_broadcast_rsp.read()){ 246 r_address_to_send = 0x3 | (0x7c1f << vci_param::N-20) ; 216 if (r_date_fifo.rok()) 217 { 218 if ( r_bc_fifo() = true ) // its a broadcast request 219 { 220 if ( r_bc_fsm.read() = false ) // no current broadcast 221 { 247 222 r_cmd_fsm = VCI_BC_SEND ; 248 } else { 249 r_id_to_send = -1; 223 r_cmd_address = 0x3 | (0x7c1f << vci_param::N-20) ; 224 } 225 } 226 else // its a single request 227 { 228 int id = -1; 250 229 for(int i = 0; i < tab_size; i++){ 251 if(r_req_id[i][0].read() == 0){ 252 r_id_to_send = i; 230 if(r_pending_fsm[i].read() == false) 231 { 232 id = i; 253 233 break; 254 234 } 255 235 } 256 if(r_id_to_send.read() == -1){ 257 r_cmd_fsm = VCI_IDLE ; 258 break; 259 } else { 236 if(id != -1){ 260 237 r_cmd_fsm = VCI_SINGLE_SEND ; 238 r_cmd_count = 0; 239 r_cmd_trdid = id; 261 240 } 262 241 #ifdef DETERMINISTIC 263 m_local_seed = r_ local_seed.read();264 r_ address_to_send= destAdress(&m_local_seed) << (vci_param::N)-(soclib::common::uint32_log2((uint32_t)m_xmesh)+soclib::common::uint32_log2((uint32_t)m_ymesh));265 r_ local_seed = m_local_seed;242 m_local_seed = r_cmd_seed.read(); 243 r_cmd_address = destAdress(&m_local_seed) << (vci_param::N)-(soclib::common::uint32_log2((uint32_t)m_xmesh)+soclib::common::uint32_log2((uint32_t)m_ymesh)); 244 r_cmd_seed = m_local_seed; 266 245 #else 267 r_ address_to_send= destAdress() << (vci_param::N)-(soclib::common::uint32_log2((uint32_t)m_xmesh)+soclib::common::uint32_log2((uint32_t)m_ymesh));246 r_cmd_address = destAdress() << (vci_param::N)-(soclib::common::uint32_log2((uint32_t)m_xmesh)+soclib::common::uint32_log2((uint32_t)m_ymesh)); 268 247 #endif 269 r_count = 0;270 248 } 271 249 } 272 250 break; 273 251 } 274 //////////////////275 252 case VCI_SINGLE_SEND: 276 253 { 277 if (p_vci.cmdack.read()){ 278 if (r_count.read() == m_length-1) { 279 r_req_id[r_id_to_send.read()][0] = (uint64_t)(m_date_fifo.read()); 280 r_req_id[r_id_to_send.read()][1] = m_cpt_cycles; 281 //std::cout << name () << " FIFO " << m_date_fifo.read() << std::endl; 282 date_fifo_get = true; 283 r_npackets = r_npackets.read() + 1; 284 r_cmd_fsm = VCI_IDLE ; 285 } else { 286 r_cmd_fsm = VCI_SINGLE_SEND ; 287 r_count = r_count.read() + 1; 254 if ( p_vci.cmdack.read()) 255 { 256 r_count = r_count.read() + 1; 257 if (r_cmd_count.read() == m_length-1) 258 { 259 r_nb_single = r_nb_single.read() + 1; 260 r_cmd_fsm = VCI_SINGLE_REGISTER ; 288 261 } 289 262 } 290 263 break; 291 264 } 292 /////////////////// 265 case VCI_SINGLE_REGISTER: 266 { 267 r_pending_date[r_cmd_trdid.read()] = (uint64_t)(m_date_fifo.read()); 268 r_pending_fsm[r_cmd_trdid.read()] = true; 269 fifo_get = true; 270 r_cmd_fsm = VCI_IDLE; 271 } 293 272 case VCI_BC_SEND: 294 273 { 295 if (p_vci.rspval.read()) { 274 if (p_vci.cmdack.read()) 275 { 276 r_bc_fsm = true; 296 277 r_bc_nrsp = (m_xmax - m_xmin) * (m_ymax - m_ymin) ; 297 r_start_latency_bc = m_cpt_cycles; 298 r_broadcast_rsp = true; 299 date_fifo_get = true; 300 r_bc_rsp_fsm = VCI_IDLE; 278 r_bc_date = (uint64_t)(m_date_fifo.read()); 279 fifo_get = true; 280 r_cmd_fsm = VCI_IDLE; 301 281 break; 302 282 } … … 304 284 } // end switch vci_fsm 305 285 306 switch(r_bc_rsp_fsm.read()){ 307 /////////////////// 308 case BC_RSP_IDLE: 309 { 310 if (p_vci.rspval.read() && r_broadcast_rsp.read()) { 311 r_bc_rsp_fsm = BC_RSP_WAIT_RSP; 312 break; 313 } 314 } 315 //////////////////// 316 case BC_RSP_WAIT_RSP: 317 { 318 if (p_vci.rspval.read() && (p_vci.rpktid.read() == 1)){ 319 if (r_bc_nrsp == 1) { 320 r_broadcast_req = false; 321 r_broadcast_rsp = false; 322 //r_address_to_send.read() = 0; 323 r_latency_bc = r_latency_bc.read() + (m_cpt_cycles - r_start_latency_bc.read()); 324 r_nb_bc = r_nb_bc.read() + 1; 325 r_bc_rsp_fsm = BC_RSP_IDLE ; 326 } else { 327 r_bc_nrsp = r_bc_nrsp.read() - 1;; 328 r_bc_rsp_fsm = BC_RSP_WAIT_RSP ; 329 } 330 } 331 break; 332 } 333 } 334 335 if(p_vci.rspval.read()){ 336 if((int)(p_vci.pktid.read()) == 0){ 337 r_latency1 = r_latency1.read() + (m_cpt_cycles - r_req_id[(int)(p_vci.rtrdid.read())][0].read()); 338 r_latency2 = r_latency2.read() + (m_cpt_cycles - r_req_id[(int)(p_vci.rtrdid.read())][1].read()); 339 r_req_id[(int)(p_vci.rtrdid.read())][0] = 0; 340 r_req_id[(int)(p_vci.rtrdid.read())][1] = 0; 341 //std::cout << name() << " bla bla " << p_vci.rtrdid.read() << std::endl; 286 ///////////////////// 287 // BC_FSM 288 ///////////////////// 289 if ( r_bc_fsm.read() && p_vci.rspval.read() ) 290 { 291 if ( p_vci.rpktid.read() == 1 ) r_bc_nrsp = r_bc_nrsp.read() - 1; 292 if (r_bc_nrsp == 1) 293 { 294 r_bc_fsm = false; 295 r_latency_bc = r_latency_bc.read() + (r_cpt_cycle.read() - r_bc_date.read()); 342 296 } 343 297 } 344 298 345 /////////////////// Filling fifo 346 if( ( (uint64_t)(m_rho*m_cpt_cycles) > (uint64_t)(m_length*r_npackets.read()*1000)) ){ 347 if (m_date_fifo.wok()){ 348 date_fifo_put = true ; 349 } 350 if (m_bc_period){ 351 if (!r_broadcast_req.read() && (m_cpt_cycles % m_bc_period)){ 352 r_broadcast_req = true; 353 } 299 /////////////////// 300 // PENDING FSMs 301 ////////////////// 302 if(p_vci.rspval.read())i 303 { 304 if((int)(p_vci.pktid.read()) == 0) // not a broadcast 305 { 306 assert( ( r_pending_fsm[(int)p_vci.rtrdid.read()] == true ) && 307 "illegal single response received") 308 r_pending_fsm[p_vci.rtrdid.read()] = false; 309 r_latency_single = r_latency_single.read() + 310 (r_cpt_cycles.read() - r_pending_date[(int)p_vci.rtrdid.read()].read()); 354 311 } 355 312 } 356 313 314 //////////////////////// 315 // traffic regulator 316 //////////////////////// 317 if ( m_bc_period && (r_cpt_period.read() > m_bc_period) ) 318 { 319 fifo_put = true ; 320 fifo_bc = true; 321 if (r_date_fifo.wok()) r_nb_bc = r_nb_bc.read() + 1; 322 } 323 else if( ( (uint64_t)(m_rho*r_cpt_cycles.read()) > (uint64_t)(m_length*r_nb_single.read()*1000)) ) 324 { 325 fifo_put = true ; 326 fifo_bc = false; 327 if (r_date_fifo.wok()) r_nb_single = r_nb_single.read() + 1; 328 } 329 330 //////////////////////// 331 // update fifos 332 //////////////////////// 357 333 if (date_fifo_put){ 358 334 if (date_fifo_get){ 359 m_date_fifo.put_and_get(m_cpt_cycles); 335 r_date_fifo.put_and_get(r_cpt_cycles.read()); 336 r_bc_fifo.put_and_get(fifo_bc); 360 337 } else { 361 m_date_fifo.simple_put(m_cpt_cycles); 338 r_date_fifo.simple_put(m_cpt_cycles); 339 r_bc_fifo.simple_put(fifo_bc); 362 340 } 363 341 } else { 364 342 if (date_fifo_get){ 365 m_date_fifo.simple_get(); 343 r_date_fifo.simple_get(); 344 r_bc_fifo.simple_get(); 366 345 } 367 346 } 368 347 369 m_cpt_cycles++; 348 /////////////////////////// 349 // increment local time 350 /////////////////////////// 351 r_cpt_cycles = r_cpt_cycles.read() + 1; 352 r_cpt_period = r_cpt_period.read() + 1; 370 353 371 354 return; … … 375 358 ///////////////////////////// 376 359 tmpl(void)::genMoore() 377 360 ///////////////////////////// 378 361 { 379 362 //////////////////////////////////////////////////////////// … … 409 392 { 410 393 p_vci.cmdval = true; 411 p_vci.address = (addr_t)(r_ address_to_send.read() + (r_count.read()*4));394 p_vci.address = (addr_t)(r_cmd_address.read() + (r_count.read()*4)); 412 395 p_vci.plen = m_length*4; 413 396 p_vci.wdata = 0; … … 424 407 { 425 408 p_vci.cmdval = true; 426 p_vci.address = (addr_t) r_ address_to_send.read();409 p_vci.address = (addr_t) r_cmd_address.read(); 427 410 p_vci.plen = 4; 428 411 p_vci.wdata = 0;
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