Index: trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/include/vci_cc_vcache_wrapper2_v1.h
===================================================================
--- trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/include/vci_cc_vcache_wrapper2_v1.h	(revision 120)
+++ trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/include/vci_cc_vcache_wrapper2_v1.h	(revision 130)
@@ -565,4 +565,6 @@
     void print_cpi();
     void print_stats();
+    void clear_stats();
+    void print_trace(size_t mode = 0);
 
 private:
Index: trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp
===================================================================
--- trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp	(revision 120)
+++ trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp	(revision 130)
@@ -35,5 +35,5 @@
 //#define EVALUATION_CACHE
 
-#ifdef SOCLIB_MODULE_DEBUG
+//#ifdef SOCLIB_MODULE_DEBUG
 namespace {
 const char *icache_fsm_state_str[] = {
@@ -169,5 +169,5 @@
     };
 }
-#endif
+//#endif
 
 #define tmpl(...)  template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapper2V1<vci_param, iss_t>
@@ -368,4 +368,36 @@
     std::cout << name() << " CPI = " 
         << (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
+}
+
+////////////////////////////////////
+tmpl(void)::print_trace(size_t mode)
+////////////////////////////////////
+{
+    typename iss_t::InstructionRequest  ireq;
+    typename iss_t::DataRequest         dreq;
+
+    m_iss.getRequests( ireq, dreq );
+   
+    std::cout << std::dec << "L1_(" << name() << ") cycle: " << m_cpt_total_cycles << std::endl;
+    std::cout << " Proc state: PC = " << std::hex << ireq.addr << " / AD = " << dreq.addr 
+              << std::dec << " / V = " << dreq.valid << " / TYPE = " << dreq.type << std::endl;
+    
+    std::cout << " Cache state:"
+              << " tgt fsm: " << tgt_fsm_state_str[r_vci_tgt_fsm]
+              << " dcache fsm: " << dcache_fsm_state_str[r_dcache_fsm]
+              << " icache fsm: " << icache_fsm_state_str[r_icache_fsm]
+              << " cmd fsm: " << cmd_fsm_state_str[r_vci_cmd_fsm]
+              << " rsp fsm: " << rsp_fsm_state_str[r_vci_rsp_fsm] 
+              << " cleanup fsm: " << cleanup_fsm_state_str[r_cleanup_fsm]
+              << " inval itlb fsm: " << inval_itlb_fsm_state_str[r_inval_itlb_fsm] 
+              << " inval dtlb fsm: " << inval_dtlb_fsm_state_str[r_inval_dtlb_fsm] << std::endl;
+
+    if( r_vci_tgt_fsm != TGT_IDLE ) 
+        std::cout << "    ... coherence request address = " << std::hex << r_tgt_addr.read() << std::endl;
+    
+    if(mode & 0x1)
+    {
+        r_wbuf.printTrace();
+    }
 }
 
@@ -411,4 +443,94 @@
         << "- ITLB MISS TRANSACTION  = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
         << "- DTLB MISS TRANSACTION  = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
+}
+
+////////////////////////
+tmpl(void)::clear_stats()
+////////////////////////
+{
+    m_cpt_dcache_data_read  = 0;
+    m_cpt_dcache_data_write = 0;
+    m_cpt_dcache_dir_read   = 0;
+    m_cpt_dcache_dir_write  = 0;
+    m_cpt_icache_data_read  = 0;
+    m_cpt_icache_data_write = 0;
+    m_cpt_icache_dir_read   = 0;
+    m_cpt_icache_dir_write  = 0;
+    
+	m_cpt_frz_cycles        = 0;
+    m_cpt_dcache_frz_cycles = 0;
+	m_cpt_total_cycles      = 0;
+    
+    m_cpt_read         = 0;
+    m_cpt_write        = 0;
+    m_cpt_data_miss    = 0;
+    m_cpt_ins_miss     = 0;
+    m_cpt_unc_read     = 0;
+    m_cpt_write_cached = 0;
+    m_cpt_ins_read     = 0;
+    
+    m_cost_write_frz     = 0;
+    m_cost_data_miss_frz = 0;
+    m_cost_unc_read_frz  = 0;
+    m_cost_ins_miss_frz  = 0;
+    
+    m_cpt_imiss_transaction      = 0;
+    m_cpt_dmiss_transaction      = 0;
+    m_cpt_unc_transaction        = 0;
+    m_cpt_write_transaction      = 0;
+    m_cpt_icache_unc_transaction = 0;	
+    
+    m_cost_imiss_transaction      = 0;
+    m_cost_dmiss_transaction      = 0;
+    m_cost_unc_transaction        = 0;
+    m_cost_write_transaction      = 0;
+    m_cost_icache_unc_transaction = 0;
+    m_length_write_transaction    = 0;
+    
+    m_cpt_ins_tlb_read       = 0;             
+    m_cpt_ins_tlb_miss       = 0;             
+    m_cpt_ins_tlb_update_acc = 0;         
+    
+    m_cpt_data_tlb_read         = 0;           
+    m_cpt_data_tlb_miss         = 0;           
+    m_cpt_data_tlb_update_acc   = 0;       
+    m_cpt_data_tlb_update_dirty = 0;    
+    m_cpt_ins_tlb_hit_dcache    = 0;
+    m_cpt_data_tlb_hit_dcache   = 0;
+    m_cpt_ins_tlb_occup_cache   = 0;
+    m_cpt_data_tlb_occup_cache  = 0;
+    
+    m_cost_ins_tlb_miss_frz          = 0;      
+    m_cost_data_tlb_miss_frz         = 0;      
+    m_cost_ins_tlb_update_acc_frz    = 0;
+    m_cost_data_tlb_update_acc_frz   = 0;
+    m_cost_data_tlb_update_dirty_frz = 0;
+    m_cost_ins_tlb_occup_cache_frz   = 0;
+    m_cost_data_tlb_occup_cache_frz  = 0;
+    
+    m_cpt_itlbmiss_transaction      = 0;    
+    m_cpt_itlb_ll_transaction       = 0;  
+    m_cpt_itlb_sc_transaction       = 0;  
+    m_cpt_dtlbmiss_transaction      = 0;  
+    m_cpt_dtlb_ll_transaction       = 0;  
+    m_cpt_dtlb_sc_transaction       = 0;  
+    m_cpt_dtlb_ll_dirty_transaction = 0;  
+    m_cpt_dtlb_sc_dirty_transaction = 0;  
+    
+    m_cost_itlbmiss_transaction      = 0;   
+    m_cost_itlb_ll_transaction       = 0;  
+    m_cost_itlb_sc_transaction       = 0;  
+    m_cost_dtlbmiss_transaction      = 0;   
+    m_cost_dtlb_ll_transaction       = 0;   
+    m_cost_dtlb_sc_transaction       = 0;   
+    m_cost_dtlb_ll_dirty_transaction = 0;   
+    m_cost_dtlb_sc_dirty_transaction = 0;
+
+    m_cpt_cc_broadcast  = 0;
+    m_cpt_cc_update_data = 0;
+    m_cpt_cc_inval_data = 0;
+    m_cpt_cc_inval_ins = 0;
+    m_cpt_cc_cleanup_data = 0;
+    m_cpt_cc_cleanup_ins = 0;
 }
 
@@ -1159,5 +1281,5 @@
     case ICACHE_BIS: 
     {
-	if ( ireq.valid ) m_cost_ins_miss_frz++;
+	//if ( ireq.valid ) m_cost_ins_miss_frz++;
 
         // external cache invalidate request
@@ -2749,5 +2871,5 @@
                 r_dcache_hit_p_save = dcache_hit_p;
                 r_dcache_fsm = DCACHE_BIS;
-                m_cost_data_tlb_miss_frz++;
+                //m_cost_data_tlb_miss_frz++;
             }
             else  // cached or uncached access with a correct speculative physical address
@@ -2917,5 +3039,5 @@
     case DCACHE_BIS:
     {
-        if ( dreq.valid ) m_cost_data_miss_frz++;
+        //if ( dreq.valid ) m_cost_data_miss_frz++;
 
         // external cache invalidate request
@@ -5159,5 +5281,5 @@
     case DCACHE_ITLB_CLEANUP:
     {
-        if ( dreq.valid ) m_cost_data_miss_frz++;
+        //if ( dreq.valid ) m_cost_data_miss_frz++;
 
         r_dcache.setinbit(((paddr_t)r_dcache_itlb_cleanup_line.read()<<(uint32_log2(m_dcache_words)+2)), r_dcache_in_itlb, false);
@@ -5295,4 +5417,13 @@
 
         r_vci_cmd_cpt = 0;
+
+	if ( (r_dcache_cleanup_req && r_dcache_itlb_read_req && (((r_icache_paddr_save.read() & ~((m_dcache_words<<2)-1)) >> (uint32_log2(m_dcache_words) + 2)) == r_dcache_cleanup_line.read())) 
+	  || (r_dcache_cleanup_req && r_dcache_tlb_read_req && (((r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) >> (uint32_log2(m_dcache_words) + 2)) == r_dcache_cleanup_line.read()))
+	  || (r_dcache_cleanup_req && r_dcache_miss_req && (((r_dcache_paddr_save.read() & ~((m_dcache_words<<2)-1)) >> (uint32_log2(m_dcache_words) + 2)) == r_dcache_cleanup_line.read()))
+	  || (r_icache_cleanup_req && r_icache_miss_req && (((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) >> (uint32_log2(m_icache_words) + 2)) == r_icache_cleanup_line.read())) )
+	{
+	    break;
+	}
+
         if (r_dcache_itlb_read_req)           
         {            
@@ -5403,4 +5534,13 @@
 
         r_vci_rsp_cpt = 0;
+
+	if ( (r_dcache_cleanup_req && r_dcache_itlb_read_req && (((r_icache_paddr_save.read() & ~((m_dcache_words<<2)-1)) >> (uint32_log2(m_dcache_words) + 2)) == r_dcache_cleanup_line.read())) 
+	  || (r_dcache_cleanup_req && r_dcache_tlb_read_req && (((r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) >> (uint32_log2(m_dcache_words) + 2)) == r_dcache_cleanup_line.read()))
+	  || (r_dcache_cleanup_req && r_dcache_miss_req && (((r_dcache_paddr_save.read() & ~((m_dcache_words<<2)-1)) >> (uint32_log2(m_dcache_words) + 2)) == r_dcache_cleanup_line.read()))
+	  || (r_icache_cleanup_req && r_icache_miss_req && (((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) >> (uint32_log2(m_icache_words) + 2)) == r_icache_cleanup_line.read())) )
+	{
+	    break;
+	}
+
         if (r_dcache_itlb_read_req)          // ITLB miss response
         {            
@@ -6077,5 +6217,5 @@
     } // end switch TGT_FSM
 
-#ifdef SOCLIB_MODULE_DEBUG 
+#ifdef SOCLIB_MODULE_DEBUG
    std::cout << name() 
       	     << " Moore R/W:" << std::hex
