Index: trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp
===================================================================
--- trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp	(revision 140)
+++ trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp	(revision 141)
@@ -244,5 +244,7 @@
       size_t nsets,
       size_t nwords,
-      size_t heap_size)
+      size_t heap_size,
+      size_t transaction_tab_lines,
+      size_t update_tab_lines)
 
     : soclib::caba::BaseModule(name),
@@ -265,6 +267,8 @@
     m_cseglist(mtc.getSegmentList(vci_tgt_index_cleanup)),
     m_coherence_table( mtc.getCoherenceTable<vci_addr_t>() ),
-    m_transaction_tab( TRANSACTION_TAB_LINES, nwords ),
-    m_update_tab( UPDATE_TAB_LINES ),
+    m_transaction_tab_lines(transaction_tab_lines),
+    m_transaction_tab( transaction_tab_lines, nwords ),
+    m_update_tab_lines( update_tab_lines),
+    m_update_tab( update_tab_lines ),
     m_cache_directory( nways, nsets, nwords, vci_param::N ),
     m_heap_directory( m_heap_size ),
@@ -338,7 +342,4 @@
       assert(nwords);
       assert(nways);
-      assert(nsets <= 1024);
-      assert(nwords <= 32);
-      assert(nways <= 32);
 
       // Set the broadcast address with Xmin,Xmax,Ymin,Ymax set to maximum
@@ -383,5 +384,5 @@
 
       // Allocation for IXR_RSP FSM
-      r_ixr_rsp_to_xram_rsp_rok	    = new sc_signal<bool>[TRANSACTION_TAB_LINES];
+      r_ixr_rsp_to_xram_rsp_rok	    = new sc_signal<bool>[m_transaction_tab_lines];
 
       // Allocation for XRAM_RSP FSM
@@ -441,18 +442,23 @@
     std::cout << "----------------------------------" << std::dec << std::endl;
     std::cout << "MEM_CACHE " << m_srcid_ini << " / Time = " << m_cpt_cycles << std::endl
-      << "- READ RATE            = " << (double)m_cpt_read/m_cpt_cycles << std::endl
-      << "- READ MISS RATE       = " << (double)m_cpt_read_miss/m_cpt_read << std::endl
-      << "- WRITE RATE           = " << (double)m_cpt_write/m_cpt_cycles << std::endl
-      << "- WRITE MISS RATE      = " << (double)m_cpt_write_miss/m_cpt_write << std::endl
-      << "- WRITE BURST LENGTH   = " << (double)m_cpt_write_cells/m_cpt_write << std::endl
-      << "- UPDATE RATE          = " << (double)m_cpt_update/m_cpt_cycles << std::endl
-      << "- UPDATE ARITY         = " << (double)m_cpt_update_mult/m_cpt_update << std::endl
-      << "- INVAL MULTICAST RATE = " << (double)(m_cpt_inval-m_cpt_inval_brdcast)/m_cpt_cycles << std::endl
-      << "- INVAL MULTICAST ARITY= " << (double)m_cpt_inval_mult/(m_cpt_inval-m_cpt_inval_brdcast) << std::endl
-      << "- INVAL BROADCAST RATE = " << (double)m_cpt_inval_brdcast/m_cpt_cycles << std::endl
-      << "- SAVE DIRTY RATE      = " << (double)m_cpt_write_dirty/m_cpt_cycles << std::endl
-      << "- CLEANUP RATE         = " << (double)m_cpt_cleanup/m_cpt_cycles << std::endl
-      << "- LL RATE              = " << (double)m_cpt_ll/m_cpt_cycles << std::endl
-      << "- SC RATE              = " << (double)m_cpt_sc/m_cpt_cycles << std::endl;
+              << "- READ RATE            = " << (double)m_cpt_read/m_cpt_cycles << std::endl
+              << "- READ TOTAL           = " << m_cpt_read << std::endl
+              << "- READ MISS RATE       = " << (double)m_cpt_read_miss/m_cpt_read << std::endl
+              << "- WRITE RATE           = " << (double)m_cpt_write/m_cpt_cycles << std::endl
+              << "- WRITE TOTAL          = " << m_cpt_write << std::endl
+              << "- WRITE MISS RATE      = " << (double)m_cpt_write_miss/m_cpt_write << std::endl
+              << "- WRITE BURST LENGTH   = " << (double)m_cpt_write_cells/m_cpt_write << std::endl
+              << "- WRITE BURST TOTAL    = " << m_cpt_write_cells << std::endl
+              << "- REQUESTS TRT FULL    = " << m_cpt_trt_full << std::endl
+              << "- READ TRT BLOKED HIT  = " << m_cpt_trt_rb << std::endl
+              << "- UPDATE RATE          = " << (double)m_cpt_update/m_cpt_cycles << std::endl
+              << "- UPDATE ARITY         = " << (double)m_cpt_update_mult/m_cpt_update << std::endl
+              << "- INVAL MULTICAST RATE = " << (double)(m_cpt_inval-m_cpt_inval_brdcast)/m_cpt_cycles << std::endl
+              << "- INVAL MULTICAST ARITY= " << (double)m_cpt_inval_mult/(m_cpt_inval-m_cpt_inval_brdcast) << std::endl
+              << "- INVAL BROADCAST RATE = " << (double)m_cpt_inval_brdcast/m_cpt_cycles << std::endl
+              << "- SAVE DIRTY RATE      = " << (double)m_cpt_write_dirty/m_cpt_cycles << std::endl
+              << "- CLEANUP RATE         = " << (double)m_cpt_cleanup/m_cpt_cycles << std::endl
+              << "- LL RATE              = " << (double)m_cpt_ll/m_cpt_cycles << std::endl
+              << "- SC RATE              = " << (double)m_cpt_sc/m_cpt_cycles << std::endl;
   }
 
@@ -567,5 +573,5 @@
 #endif
 
-      for(size_t i=0; i<TRANSACTION_TAB_LINES ; i++){
+      for(size_t i=0; i<m_transaction_tab_lines ; i++){
         r_ixr_rsp_to_xram_rsp_rok[i] = false;
       }
@@ -602,4 +608,6 @@
       m_cpt_ll     		    = 0;
       m_cpt_sc     		    = 0;
+      m_cpt_trt_full      = 0;
+      m_cpt_trt_rb        = 0;
 
       return;
@@ -721,6 +729,8 @@
           if ( p_vci_tgt.cmdval && m_cmd_read_addr_fifo.wok() ) {
             cmd_read_fifo_put = true;
-            if ( p_vci_tgt.eop )  r_tgt_cmd_fsm = TGT_CMD_IDLE;
-            else                  r_tgt_cmd_fsm = TGT_CMD_READ_EOP;		
+            if ( p_vci_tgt.eop ) {
+                    m_cpt_read++;
+                    r_tgt_cmd_fsm = TGT_CMD_IDLE;
+            } else  r_tgt_cmd_fsm = TGT_CMD_READ_EOP;		
           } 
           break;
@@ -730,4 +740,5 @@
         {
           if ( p_vci_tgt.cmdval && p_vci_tgt.eop ){
+            m_cpt_read++;
             r_tgt_cmd_fsm = TGT_CMD_IDLE;
           }
@@ -881,5 +892,4 @@
             PRINTF("  * <MEM_CACHE.READ> Request from %d.%d at address %llx\n",(uint32_t)m_cmd_read_srcid_fifo.read(),(uint32_t)m_cmd_read_pktid_fifo.read(),(uint64_t)m_cmd_read_addr_fifo.read());
 
-            m_cpt_read++;
             r_read_fsm = READ_DIR_LOCK;
           }
@@ -922,5 +932,4 @@
             } else {
               r_read_fsm = READ_TRT_LOCK;
-              m_cpt_read_miss++;
             }
           }
@@ -1162,6 +1171,11 @@
             bool   wok = !m_transaction_tab.full(index);
             if( hit_read || !wok || hit_write ) {  // missing line already requested or no space
+              if(!wok)
+                m_cpt_trt_full++;
+              if(hit_read || hit_write)
+                m_cpt_trt_rb++;
               r_read_fsm = READ_IDLE;
             } else {			   // missing line is requested to the XRAM
+              m_cpt_read_miss++;
               r_read_trt_index = index;
               r_read_fsm       = READ_TRT_SET;
@@ -1324,5 +1338,4 @@
             } else {
               r_write_fsm = WRITE_TRT_LOCK;
-              m_cpt_write_miss++;
             }
           }
@@ -1594,9 +1607,12 @@
               r_write_trt_index = hit_index;
               r_write_fsm       = WRITE_TRT_DATA;
+              m_cpt_write_miss++;
             } else if ( wok && !hit_write ) {	// set a new entry in TRT
               r_write_trt_index = wok_index;
               r_write_fsm       = WRITE_TRT_SET;
+              m_cpt_write_miss++;
             } else {		// wait an empty entry in TRT
               r_write_fsm       = WRITE_WAIT;
+              m_cpt_trt_full++;
             }
           }
@@ -2040,5 +2056,5 @@
         {
           size_t ptr   = r_xram_rsp_trt_index.read();
-          size_t lines = TRANSACTION_TAB_LINES;
+          size_t lines = m_transaction_tab_lines;
           for(size_t i=0; i<lines; i++){
             size_t index=(i+ptr+1)%lines;
@@ -4859,6 +4875,6 @@
 
 // Local Variables:
-// tab-width: 4
-// c-basic-offset: 4
+// tab-width: 2
+// c-basic-offset: 2
 // c-file-offsets:((innamespace . 0)(inline-open . 0))
 // indent-tabs-mode: nil
