Index: trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp
===================================================================
--- trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp	(revision 167)
+++ trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp	(revision 175)
@@ -88,8 +88,4 @@
 # define set_num_icache(     addr,num_cache) set_num_cache     (addr,num_cache)
 # define set_num_icache_only(addr,num_cache) set_num_cache_only(addr,num_cache)
-# define get_num_dcache(     addr)           get_num_cache     (addr)          
-# define get_num_dcache_only(addr)           get_num_cache_only(addr)          
-# define set_num_dcache(     addr,num_cache) set_num_cache     (addr,num_cache)
-# define set_num_dcache_only(addr,num_cache) set_num_cache_only(addr,num_cache)
 #elif (CC_XCACHE_WRAPPER_MULTI_CACHE==2)
 # define get_num_icache(     addr,num_cpu)   num_cpu
@@ -97,11 +93,11 @@
 # define set_num_icache(     addr,num_cache) do  {} while (0)
 # define set_num_icache_only(addr,num_cache) addr
+#else
+#error "Invalid value to CC_XCACHE_WRAPPER_MULTI_CACHE"
+#endif
 # define get_num_dcache(     addr)           get_num_cache     (addr)          
 # define get_num_dcache_only(addr)           get_num_cache_only(addr)          
 # define set_num_dcache(     addr,num_cache) set_num_cache     (addr,num_cache)
 # define set_num_dcache_only(addr,num_cache) set_num_cache_only(addr,num_cache)
-#else
-#error "Invalid value to CC_XCACHE_WRAPPER_MULTI_CACHE"
-#endif
 
       const char *dcache_fsm_state_str[] = {
@@ -118,5 +114,4 @@
         "DCACHE_CC_CHECK",
         "DCACHE_CC_INVAL",
-        "DCACHE_CC_UPDT",
         "DCACHE_CC_CLEANUP",
       };
@@ -131,5 +126,4 @@
         "ICACHE_CC_CHECK",
         "ICACHE_CC_INVAL",
-        "ICACHE_CC_UPDT",
       };
       const char *cmd_fsm_state_str[] = {
@@ -300,5 +294,5 @@
              "wbuf_nlines must be a multiple of nb cache.");
 
-      // FIXME : s'adapter à la taille des requêtes XTN_READ/XTN_WRITE
+      // FIXME : s'adapter à la taille des requêtes XTN_READ/XTN_WRITE, car le type est fournit dans le champs l'adresse
       ASSERT((m_nb_dcache == 1) or (dcache_words >= 16),
              "When multi cache is activated, need 4 bits (16 word) to the cache set .");
@@ -576,5 +570,4 @@
             << _dcache_words << std::endl; // cache_nb_words
         }
-
 #endif
     } // end constructor
@@ -1209,6 +1202,16 @@
 //           r_wbuf[num_cache]->printTrace(1);
 // #endif
-
-        }
+        }
+#if CC_XCACHE_WRAPPER_DEBUG
+      if (m_cpt_total_cycles>=CC_XCACHE_WRAPPER_DEBUG_CYCLE_MIN)
+      {
+          PRINTF("    * rsp_fifo_icache %s\n",name().c_str());
+          r_vci_rsp_fifo_icache_data     .print();
+          r_vci_rsp_fifo_icache_num_cache.print();
+          PRINTF("    * rsp_fifo_dcache %s\n",name().c_str());
+          r_vci_rsp_fifo_dcache_data     .print();
+          r_vci_rsp_fifo_dcache_num_cache.print();
+      }
+#endif
 
       /////////////////////////////////////////////////////////////////////
@@ -2138,5 +2141,4 @@
               m_cpt_icache_data_read += m_icache_ways;
               addr_40 ad = r_tgt_iaddr;
-              data_t  icache_rdata = 0;
 
               PRINTF("    * <ICACHE [%d]> CC_CHECK\n",num_cache);
@@ -2157,5 +2159,8 @@
                 r_icache_fsm[num_cache] = r_icache_fsm_save[num_cache];
               } else {
-                bool    icache_hit   = r_icache[num_cache]->read(ad, &icache_rdata);
+                uint32_t word       = r_cache_word;
+                data_t   mask       = vci_param::be2mask(r_tgt_be[word]);
+                data_t   rdata      = 0;
+                bool     icache_hit = r_icache[num_cache]->read(ad+word*4,&rdata);
 
                 PRINTF("    * <ICACHE [%d]> have no request, hit cache : %d\n",num_cache,icache_hit);
@@ -2163,10 +2168,9 @@
                 if ( icache_hit and r_tgt_update) 
                   {
-                    uint32_t word  = r_cache_word;
-                    data_t   mask  = vci_param::be2mask(r_tgt_be[word]);
-                    data_t   rdata = 0;
-
-                    r_icache[num_cache]->read(ad+word*4,&rdata);
-                    r_tgt_buf[word] = (mask & r_tgt_buf[word]) | (~mask & rdata);
+                    // Assumption : We have RAM for icache with write enable on byte.
+                    // Consequence : icache_read is only consultation of directory
+
+                    //if(r_tgt_be[word])
+                    r_icache[num_cache]->write(ad+word*4, (mask & r_tgt_buf[word]) | (~mask & rdata));
                             
                     word ++;
@@ -2179,10 +2183,8 @@
                     if (word==m_icache_words)
                       {
-                        r_icache_fsm[num_cache] = ICACHE_CC_UPDT;
-
-                        // find next valid word
-                        for (word=0; word<m_icache_words; ++word)
-                          if (r_tgt_be[word] != 0)
-                            break;
+                          r_tgt_icache_req[num_cache] = false;
+                          r_tgt_icache_rsp[num_cache] = true;
+                          r_icache_fsm    [num_cache] = r_icache_fsm_save[num_cache].read();
+                          word = 0;
                       }
                     r_cache_word = word;
@@ -2214,35 +2216,4 @@
               break;
             }    
-            /////////////////////
-          case ICACHE_CC_UPDT:
-            {                       
-              addr_40 ad = r_tgt_iaddr.read();
-              m_cpt_icache_dir_write++;
-              m_cpt_icache_data_write++;
-
-              uint32_t word  = r_cache_word;
-
-              if(r_tgt_be[word])
-                r_icache[num_cache]->write(ad+word*4, r_tgt_buf[word]);
-
-              word ++;
-              
-              // find next valid word
-              for (; word<m_icache_words; ++word)
-                if (r_tgt_be[word] != 0)
-                  break;
-
-              if (word==m_icache_words)
-                {
-                  r_tgt_icache_req[num_cache] = false;
-                  r_tgt_icache_rsp[num_cache] = true;
-                  r_icache_fsm    [num_cache] = r_icache_fsm_save[num_cache].read();
-                  word = 0;
-                }
-              r_cache_word = word;
-
-              break;
-            }    
-
           }// end switch r_icache_fsm
 
@@ -2515,4 +2486,7 @@
                           if (not dcache_cached)
                             {
+                                ASSERT(not dcache_hit,
+                                       "Request is uncached, but hit in dcache!");
+
                               r_dcache_previous_unc[num_cache] = true;
                               m_cpt_data_write_uncached++;
@@ -2520,5 +2494,5 @@
                           else if (not dcache_hit)
                             m_cpt_data_write_miss++;
-                                        
+                                   
                           if (dcache_hit) {
                             // update data cache
@@ -2922,5 +2896,4 @@
             {
               addr_40  ad          = r_tgt_daddr;
-              data_t  dcache_rdata = 0;
 
               PRINTF("    * <DCACHE [%d]> CC_CHECK\n",num_cache);
@@ -2942,20 +2915,21 @@
                 r_dcache_fsm[num_cache] = r_dcache_fsm_save[num_cache];
               } else {
-                bool    dcache_hit   = r_dcache[num_cache]->read(ad, &dcache_rdata);
+                uint32_t word       = r_cache_word;
+                data_t   mask       = vci_param::be2mask(r_tgt_be[word]);
+                data_t   rdata      = 0;
+                bool     dcache_hit = r_dcache[num_cache]->read(ad+word*4,&rdata);
 
                 PRINTF("    * <DCACHE [%d]> have no request, hit cache : %d, update : %d\n",num_cache,dcache_hit,(uint32_t)r_tgt_update);
 
-                m_cpt_dcache_data_read += m_dcache_ways;
+                m_cpt_dcache_data_write+= m_dcache_ways;
                 m_cpt_dcache_dir_read += m_dcache_ways;
 
                 if ( dcache_hit and r_tgt_update ) 
                   {
-                    uint32_t word  = r_cache_word;
-                    data_t   mask  = vci_param::be2mask(r_tgt_be[word]);
-                    data_t   rdata = 0;
-
-                    r_dcache[num_cache]->read(ad+word*4,&rdata);
-                            
-                    r_tgt_buf[word] = (mask & r_tgt_buf[word]) | (~mask & rdata);
+                    // Assumption : We have RAM for dcache with write enable on byte.
+                    // Consequence : dcache_read is only consultation of directory
+
+                    //if(r_tgt_be[word])
+                    r_dcache[num_cache]->write(ad+word*4, (mask & r_tgt_buf[word]) | (~mask & rdata));
 
                     word ++;
@@ -2968,9 +2942,8 @@
                     if (word==m_dcache_words)
                       {
-                        r_dcache_fsm[num_cache] = DCACHE_CC_UPDT;
-
-                        for (word=0; word<m_dcache_words; ++word)
-                          if (r_tgt_be[word] != 0)
-                            break;
+                        r_tgt_dcache_req[num_cache] = false;
+                        r_tgt_dcache_rsp[num_cache] = true;
+                        r_dcache_fsm    [num_cache] = r_dcache_fsm_save[num_cache];
+                        word = 0;
                       }
                     r_cache_word = word;
@@ -2988,34 +2961,4 @@
                 }
               }
-              break;
-            }
-            ///////////////////
-          case DCACHE_CC_UPDT:    // update directory and data cache        
-            {
-              addr_40 ad = r_tgt_daddr;
-
-              m_cpt_dcache_dir_write++;
-              m_cpt_dcache_data_write++;
-
-              uint32_t word  = r_cache_word;
-                    
-              if(r_tgt_be[word])
-                r_dcache[num_cache]->write(ad+word*4, r_tgt_buf[word]);
-
-              word ++;
-
-              for (; word<m_dcache_words; ++word)
-                if (r_tgt_be[word] != 0)
-                  break;
-                    
-              if (word==m_dcache_words)
-                {
-                  r_tgt_dcache_req[num_cache] = false;
-                  r_tgt_dcache_rsp[num_cache] = true;
-                  r_dcache_fsm    [num_cache] = r_dcache_fsm_save[num_cache];
-                  word = 0;
-                }
-              r_cache_word = word;
-
               break;
             }
@@ -3898,5 +3841,5 @@
 
         m_cost_imiss_transaction++;
-        PRINTF("      * <RSP> rspval : %d\n",(uint32_t)p_vci_ini_rw.rspval.read());
+        PRINTF("      * <RSP> rspval : %d / r_vci_rsp_fifo_icache_data.wok %d\n",(uint32_t)p_vci_ini_rw.rspval.read(),(uint32_t)r_vci_rsp_fifo_icache_data.wok());
 
         if (p_vci_ini_rw.rspval.read() and r_vci_rsp_fifo_icache_data.wok())
@@ -3949,7 +3892,10 @@
 
         m_cost_dmiss_transaction++;
+
+        PRINTF("      * <RSP> rspval : %d / r_vci_rsp_fifo_icache_data.wok %d\n",(uint32_t)p_vci_ini_rw.rspval.read(),(uint32_t)r_vci_rsp_fifo_dcache_data.wok());
+
         if (p_vci_ini_rw.rspval.read() and r_vci_rsp_fifo_dcache_data.wok())
           {
-            PRINTF("      * <RSP> have rspval - error : %d\n",(int)p_vci_ini_rw.rerror.read());
+              PRINTF("      * <RSP> have rsp - r_vci_rsp_cpt : %d/%d\n",(uint32_t)r_vci_rsp_cpt.read(),(uint32_t)m_icache_words);
 
             ASSERT(r_vci_rsp_cpt.read() < m_dcache_words,
