Index: trunk/modules/vci_mem_cache_v4/caba/source/include/update_tab_v4.h
===================================================================
--- trunk/modules/vci_mem_cache_v4/caba/source/include/update_tab_v4.h	(revision 177)
+++ trunk/modules/vci_mem_cache_v4/caba/source/include/update_tab_v4.h	(revision 184)
@@ -47,13 +47,13 @@
       size_t i_count) 
   {
-    valid		= i_valid;
-    update	    = i_update;
+    valid	= i_valid;
+    update	= i_update;
     brdcast     = i_brdcast;
     rsp         = i_rsp;
-    srcid		= i_srcid;
-    trdid		= i_trdid;
-    pktid		= i_pktid;
-    nline		= i_nline;
-    count		= i_count;
+    srcid	= i_srcid;
+    trdid	= i_trdid;
+    pktid	= i_pktid;
+    nline	= i_nline;
+    count	= i_count;
   }
 
@@ -156,5 +156,5 @@
 
   ////////////////////////////////////////////////////////////////////
-  // The size() function returns the size of the tab  
+  // The print() function diplays the tab content 
   ////////////////////////////////////////////////////////////////////
   void print(){
@@ -262,4 +262,17 @@
 
   /////////////////////////////////////////////////////////////////////
+  // The is_not_empty() function returns true if the table is not empty
+  /////////////////////////////////////////////////////////////////////
+  bool is_not_empty()
+  {
+    for(size_t i = 0 ; i < size_tab ; i++){
+      if(tab[i].valid){
+        return true;
+      }
+    }
+    return false;
+  }
+
+  /////////////////////////////////////////////////////////////////////
   // The need_rsp() function returns the need of a response
   // Arguments :
Index: trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h
===================================================================
--- trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h	(revision 177)
+++ trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h	(revision 184)
@@ -80,5 +80,4 @@
         TGT_CMD_IDLE,
         TGT_CMD_READ,
-        TGT_CMD_READ_EOP,
         TGT_CMD_WRITE,
         TGT_CMD_ATOMIC,
@@ -89,5 +88,5 @@
         TGT_RSP_READ_IDLE,
         TGT_RSP_WRITE_IDLE,
-        TGT_RSP_LLSC_IDLE,
+        TGT_RSP_SC_IDLE,
         TGT_RSP_XRAM_IDLE,
         TGT_RSP_INIT_IDLE,
@@ -95,5 +94,5 @@
         TGT_RSP_READ,
         TGT_RSP_WRITE,
-        TGT_RSP_LLSC,
+        TGT_RSP_SC,
         TGT_RSP_XRAM,
         TGT_RSP_INIT,
@@ -139,5 +138,5 @@
         READ_TRT_LOCK,
         READ_TRT_SET,
-        READ_XRAM_REQ,
+        READ_TRT_REQ,
       };
 
@@ -197,15 +196,15 @@
         IXR_CMD_READ_IDLE,
         IXR_CMD_WRITE_IDLE,
-        IXR_CMD_LLSC_IDLE,
+        IXR_CMD_SC_IDLE,
         IXR_CMD_XRAM_IDLE,
         IXR_CMD_READ_NLINE,
         IXR_CMD_WRITE_NLINE,
-        IXR_CMD_LLSC_NLINE,
+        IXR_CMD_SC_NLINE,
         IXR_CMD_XRAM_DATA,
       };
 
-      /* States of the LLSC fsm */
-      enum llsc_fsm_state_e{
-        LLSC_IDLE,
+      /* States of the SC fsm */
+      enum sc_fsm_state_e{
+        SC_IDLE,
         SC_DIR_LOCK,
         SC_DIR_HIT_READ,
@@ -215,15 +214,15 @@
         SC_HEAP_LOCK,
         SC_UPT_REQ,
-        SC_UPDATE,
-        SC_TRT_LOCK,
+        SC_UPT_NEXT,
+        SC_TRT_PUT_LOCK,
         SC_INVAL_LOCK,
         SC_DIR_INVAL,
         SC_INVAL,
-        SC_XRAM_SEND,
-        SC_RSP_FALSE,
-        SC_RSP_TRUE,
-        LLSC_TRT_LOCK,
-        LLSC_TRT_SET,
-        LLSC_XRAM_REQ,
+        SC_TRT_PUT_REQ,
+        SC_RSP_FAIL,
+        SC_RSP_SUCCESS,
+        SC_TRT_GET_LOCK,
+        SC_TRT_GET_SET,
+        SC_TRT_GET_REQ,
       };
 
@@ -247,5 +246,5 @@
         ALLOC_DIR_READ,
         ALLOC_DIR_WRITE,
-        ALLOC_DIR_LLSC,
+        ALLOC_DIR_SC,
         ALLOC_DIR_CLEANUP,
         ALLOC_DIR_XRAM_RSP,
@@ -256,5 +255,5 @@
         ALLOC_TRT_READ,
         ALLOC_TRT_WRITE,
-        ALLOC_TRT_LLSC,
+        ALLOC_TRT_SC,
         ALLOC_TRT_XRAM_RSP,
         ALLOC_TRT_IXR_RSP,
@@ -267,5 +266,5 @@
         ALLOC_UPT_INIT_RSP,
         ALLOC_UPT_CLEANUP,
-        ALLOC_UPT_LLSC,
+        ALLOC_UPT_SC,
       };
 
@@ -274,9 +273,28 @@
         ALLOC_HEAP_READ,
         ALLOC_HEAP_WRITE,
-        ALLOC_HEAP_LLSC,
+        ALLOC_HEAP_SC,
         ALLOC_HEAP_CLEANUP,
         ALLOC_HEAP_XRAM_RSP,
       };
 
+      // debug variables (for each FSM)
+      size_t       m_debug_start_cycle;
+      bool         m_debug_ok;
+      bool         m_debug_global;
+      bool         m_debug_tgt_cmd_fsm;
+      bool         m_debug_tgt_rsp_fsm;
+      bool         m_debug_init_cmd_fsm;
+      bool         m_debug_init_rsp_fsm;
+      bool         m_debug_read_fsm;
+      bool         m_debug_write_fsm;
+      bool         m_debug_sc_fsm;
+      bool         m_debug_cleanup_fsm;
+      bool         m_debug_ixr_cmd_fsm;
+      bool         m_debug_ixr_rsp_fsm;
+      bool         m_debug_xram_rsp_fsm;
+      bool         m_debug_previous_hit;
+      size_t       m_debug_previous_count;
+
+      // instrumentation counters
       uint32_t	   m_cpt_cycles;            // Counter of cycles 
       uint32_t	   m_cpt_read;              // Number of READ transactions
@@ -297,4 +315,6 @@
       uint32_t	   m_cpt_sc;                // Number of SC transactions
 
+      size_t       m_prev_count;
+
       protected:
 
@@ -310,29 +330,28 @@
 
       VciMemCacheV4(
-          sc_module_name name,                              // Instance Name 
-          const soclib::common::MappingTable &mtp,          // Mapping table for primary requets
-          const soclib::common::MappingTable &mtc,          // Mapping table for coherence requets
-          const soclib::common::MappingTable &mtx,          // Mapping table for XRAM
-          const soclib::common::IntTab &vci_ixr_index,      // VCI port to XRAM (initiator)
-          const soclib::common::IntTab &vci_ini_index,      // VCI port to PROC (initiator)
-          const soclib::common::IntTab &vci_tgt_index,      // VCI port to PROC (target)
-          const soclib::common::IntTab &vci_tgt_index_cleanup,    // VCI port to PROC (target) for cleanup
-          size_t nways,                                     // Number of ways per set 
-          size_t nsets,                                     // Number of sets
-          size_t nwords,                                    // Number of words per line
-          size_t heap_size=1024,                            // Size of the heap
-          size_t transaction_tab_lines=TRANSACTION_TAB_LINES,// Size of the TRT
-          size_t update_tab_lines=UPDATE_TAB_LINES          // Size of the UPT
-          );
+          sc_module_name name,                                // Instance Name 
+          const soclib::common::MappingTable &mtp,            // Mapping table for primary requets
+          const soclib::common::MappingTable &mtc,            // Mapping table for coherence requets
+          const soclib::common::MappingTable &mtx,            // Mapping table for XRAM
+          const soclib::common::IntTab &vci_ixr_index,        // VCI port to XRAM (initiator)
+          const soclib::common::IntTab &vci_ini_index,        // VCI port to PROC (initiator)
+          const soclib::common::IntTab &vci_tgt_index,        // VCI port to PROC (target)
+          const soclib::common::IntTab &vci_tgt_index_cleanup,// VCI port to PROC (target) for cleanup
+          size_t nways,                                       // Number of ways per set 
+          size_t nsets,                                       // Number of sets
+          size_t nwords,                                      // Number of words per line
+          size_t heap_size=1024,                              // Size of the heap
+          size_t transaction_tab_lines=TRANSACTION_TAB_LINES, // Size of the TRT
+          size_t update_tab_lines=UPDATE_TAB_LINES,           // Size of the UPT
+          size_t debug_start_cycle=0,
+          bool   debug_ok=false);
 
       ~VciMemCacheV4();
 
       void transition();
-
       void genMoore();
-
       void print_stats();
-
       void print_trace();
+      void cache_monitor(vci_addr_t addr);
 
       private:
@@ -343,18 +362,18 @@
       const size_t              		m_ways;                 // Number of ways in a set
       const size_t              		m_sets;                 // Number of cache sets
-      const size_t              		m_words;		// Number of words in a line
-      const size_t              		m_srcid_ixr;		// Srcid for requests to XRAM 
-      const size_t              		m_srcid_ini;		// Srcid for requests to processors
+      const size_t              		m_words;		        // Number of words in a line
+      const size_t              		m_srcid_ixr;		    // Srcid for requests to XRAM 
+      const size_t              		m_srcid_ini;		    // Srcid for requests to processors
       std::list<soclib::common::Segment>  	m_seglist;    		// memory cached into the cache
       std::list<soclib::common::Segment>  	m_cseglist;   		// coherence segment for the cache
       vci_addr_t        		     	*m_coherence_table; 	// address(srcid)
       uint32_t                    		m_transaction_tab_lines;
-      TransactionTab      		    	m_transaction_tab;	// xram transaction table
+      TransactionTab      		    	m_transaction_tab;	    // xram transaction table
       uint32_t                    		m_update_tab_lines;
-      UpdateTab                 		m_update_tab;		// pending update & invalidate 
-      CacheDirectory			        m_cache_directory;	// data cache directory
-      HeapDirectory             		m_heap_directory;       // heap directory
-
-      data_t	        	       		***m_cache_data;	// data array[set][way][word]
+      UpdateTab                 		m_update_tab;		    // pending update & invalidate 
+      CacheDirectory			        m_cache_directory;	    // data cache directory
+      HeapDirectory             		m_heap;                 // heap for copies
+
+      data_t	        	       		***m_cache_data;	    // data array[set][way][word]
 
       // adress masks
@@ -371,4 +390,5 @@
       //////////////////////////////////////////////////
       sc_signal<size_t>   r_copies_limit; // Limit of the number of copies for one line
+      sc_signal<size_t>   xxx_count;
 
       //////////////////////////////////////////////////
@@ -392,11 +412,11 @@
       GenericFifo<be_t>	     m_cmd_write_be_fifo;
 
-      // Fifo between TGT_CMD fsm and LLSC fsm
-      GenericFifo<uint64_t>  m_cmd_llsc_addr_fifo;
-      GenericFifo<bool>      m_cmd_llsc_eop_fifo;
-      GenericFifo<size_t>    m_cmd_llsc_srcid_fifo;
-      GenericFifo<size_t>    m_cmd_llsc_trdid_fifo;
-      GenericFifo<size_t>    m_cmd_llsc_pktid_fifo;
-      GenericFifo<data_t>    m_cmd_llsc_wdata_fifo;
+      // Fifo between TGT_CMD fsm and SC fsm
+      GenericFifo<uint64_t>  m_cmd_sc_addr_fifo;
+      GenericFifo<bool>      m_cmd_sc_eop_fifo;
+      GenericFifo<size_t>    m_cmd_sc_srcid_fifo;
+      GenericFifo<size_t>    m_cmd_sc_trdid_fifo;
+      GenericFifo<size_t>    m_cmd_sc_pktid_fifo;
+      GenericFifo<data_t>    m_cmd_sc_wdata_fifo;
 
       sc_signal<int>         r_tgt_cmd_fsm;
@@ -555,57 +575,57 @@
 
       ///////////////////////////////////////////////////////
-      // Registers controlled by LLSC fsm
+      // Registers controlled by SC fsm
       ///////////////////////////////////////////////////////
 
-      sc_signal<int>       r_llsc_fsm;          // FSM state
-      sc_signal<data_t>	   r_llsc_wdata;		// write data word
-      sc_signal<data_t>	   *r_llsc_rdata;		// read data word
-      sc_signal<uint32_t>  r_llsc_lfsr;         // lfsr for random introducing
-      sc_signal<size_t>    r_llsc_cpt;  	    // size of command
-      sc_signal<copy_t>    r_llsc_copy; 	    // Srcid of the first copy
-      sc_signal<copy_t>    r_llsc_copy_cache;   // Srcid of the first copy
-      sc_signal<bool>      r_llsc_copy_inst;	// Type of the first copy
-      sc_signal<size_t>    r_llsc_count;	    // number of copies
-      sc_signal<size_t>    r_llsc_ptr;  	    // pointer to the heap
-      sc_signal<size_t>    r_llsc_next_ptr;  	// next pointer to the heap
-      sc_signal<bool>      r_llsc_is_cnt;	    // is_cnt bit (in directory)
-      sc_signal<bool>      r_llsc_dirty;	    // dirty bit (in directory)
-      sc_signal<size_t>    r_llsc_way;		    // way in directory
-      sc_signal<size_t>    r_llsc_set;		    // set in directory
-      sc_signal<data_t>    r_llsc_tag;		    // cache line tag (in directory)
-      sc_signal<size_t>    r_llsc_trt_index;    // Transaction Table index
-      sc_signal<size_t>    r_llsc_upt_index;    // Update Table index
-
-      // Buffer between LLSC fsm and INIT_CMD fsm (XRAM read)	
-      sc_signal<bool>	   r_llsc_to_ixr_cmd_req;   // valid request
-      sc_signal<addr_t>	   r_llsc_to_ixr_cmd_nline; // cache line index
-      sc_signal<size_t>	   r_llsc_to_ixr_cmd_trdid; // index in Transaction Table
-      sc_signal<bool>	   r_llsc_to_ixr_cmd_write; // write request
-      sc_signal<data_t>	  *r_llsc_to_ixr_cmd_data;  // cache line data
-
-
-      // Buffer between LLSC fsm and TGT_RSP fsm
-      sc_signal<bool>	   r_llsc_to_tgt_rsp_req;   // valid request
-      sc_signal<data_t>    r_llsc_to_tgt_rsp_data;  // read data word
-      sc_signal<size_t>	   r_llsc_to_tgt_rsp_srcid; // Transaction srcid
-      sc_signal<size_t>	   r_llsc_to_tgt_rsp_trdid; // Transaction trdid
-      sc_signal<size_t>	   r_llsc_to_tgt_rsp_pktid; // Transaction pktid
-
-      // Buffer between LLSC fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
-      sc_signal<bool>	   r_llsc_to_init_cmd_multi_req;    // valid request
-      sc_signal<bool>	   r_llsc_to_init_cmd_brdcast_req;  // brdcast request
-      sc_signal<addr_t>	   r_llsc_to_init_cmd_nline;	    // cache line index
-      sc_signal<size_t>	   r_llsc_to_init_cmd_trdid;	    // index in Update Table
-      sc_signal<data_t>    r_llsc_to_init_cmd_wdata;        // data (one word)
-      sc_signal<bool>      r_llsc_to_init_cmd_is_long;      // it is a 64 bits SC
-      sc_signal<data_t>    r_llsc_to_init_cmd_wdata_high;   // data high (one word)
-      sc_signal<size_t>	   r_llsc_to_init_cmd_index;	    // index of the word in line
-      GenericFifo<bool>    m_llsc_to_init_cmd_inst_fifo;    // fifo for the L1 type
-      GenericFifo<size_t>  m_llsc_to_init_cmd_srcid_fifo;   // fifo for srcids
-      GenericFifo<size_t>  m_llsc_to_init_cmd_cache_id_fifo;// fifo for srcids
-
-      // Buffer between LLSC fsm and INIT_RSP fsm (Decrement UPT entry)
-      sc_signal<bool>      r_llsc_to_init_rsp_req;          // valid request
-      sc_signal<size_t>    r_llsc_to_init_rsp_upt_index;    // index in update table
+      sc_signal<int>       r_sc_fsm;                        // FSM state
+      sc_signal<data_t>	   r_sc_wdata;	                    // write data word
+      sc_signal<data_t>	   *r_sc_rdata;	                    // read data word
+      sc_signal<uint32_t>  r_sc_lfsr;                       // lfsr for random introducing
+      sc_signal<size_t>    r_sc_cpt;  	                    // size of command
+      sc_signal<copy_t>    r_sc_copy; 	                    // Srcid of the first copy
+      sc_signal<copy_t>    r_sc_copy_cache;                 // Srcid of the first copy
+      sc_signal<bool>      r_sc_copy_inst;	                // Type of the first copy
+      sc_signal<size_t>    r_sc_count;	                    // number of copies
+      sc_signal<size_t>    r_sc_ptr;  	                    // pointer to the heap
+      sc_signal<size_t>    r_sc_next_ptr;  	                // next pointer to the heap
+      sc_signal<bool>      r_sc_is_cnt;	                    // is_cnt bit (in directory)
+      sc_signal<bool>      r_sc_dirty;	                    // dirty bit (in directory)
+      sc_signal<size_t>    r_sc_way;		                // way in directory
+      sc_signal<size_t>    r_sc_set;		                // set in directory
+      sc_signal<data_t>    r_sc_tag;		                // cache line tag (in directory)
+      sc_signal<size_t>    r_sc_trt_index;                  // Transaction Table index
+      sc_signal<size_t>    r_sc_upt_index;                  // Update Table index
+
+      // Buffer between SC fsm and INIT_CMD fsm (XRAM read)	
+      sc_signal<bool>	   r_sc_to_ixr_cmd_req;             // valid request
+      sc_signal<addr_t>	   r_sc_to_ixr_cmd_nline;           // cache line index
+      sc_signal<size_t>	   r_sc_to_ixr_cmd_trdid;           // index in Transaction Table
+      sc_signal<bool>	   r_sc_to_ixr_cmd_write;           // write request
+      sc_signal<data_t>	  *r_sc_to_ixr_cmd_data;            // cache line data
+
+
+      // Buffer between SC fsm and TGT_RSP fsm
+      sc_signal<bool>	   r_sc_to_tgt_rsp_req;             // valid request
+      sc_signal<data_t>    r_sc_to_tgt_rsp_data;            // read data word
+      sc_signal<size_t>	   r_sc_to_tgt_rsp_srcid;           // Transaction srcid
+      sc_signal<size_t>	   r_sc_to_tgt_rsp_trdid;           // Transaction trdid
+      sc_signal<size_t>	   r_sc_to_tgt_rsp_pktid;           // Transaction pktid
+
+      // Buffer between SC fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
+      sc_signal<bool>	   r_sc_to_init_cmd_multi_req;      // valid request
+      sc_signal<bool>	   r_sc_to_init_cmd_brdcast_req;    // brdcast request
+      sc_signal<addr_t>	   r_sc_to_init_cmd_nline;	        // cache line index
+      sc_signal<size_t>	   r_sc_to_init_cmd_trdid;	        // index in Update Table
+      sc_signal<data_t>    r_sc_to_init_cmd_wdata;          // data (one word)
+      sc_signal<bool>      r_sc_to_init_cmd_is_long;        // it is a 64 bits SC
+      sc_signal<data_t>    r_sc_to_init_cmd_wdata_high;     // data high (one word)
+      sc_signal<size_t>	   r_sc_to_init_cmd_index;	        // index of the word in line
+      GenericFifo<bool>    m_sc_to_init_cmd_inst_fifo;      // fifo for the L1 type
+      GenericFifo<size_t>  m_sc_to_init_cmd_srcid_fifo;     // fifo for srcids
+      GenericFifo<size_t>  m_sc_to_init_cmd_cache_id_fifo;  // fifo for srcids
+
+      // Buffer between SC fsm and INIT_RSP fsm (Decrement UPT entry)
+      sc_signal<bool>      r_sc_to_init_rsp_req;            // valid request
+      sc_signal<size_t>    r_sc_to_init_rsp_upt_index;      // index in update table
 
       ////////////////////////////////////////////////////
Index: trunk/modules/vci_mem_cache_v4/caba/source/include/xram_transaction_v4.h
===================================================================
--- trunk/modules/vci_mem_cache_v4/caba/source/include/xram_transaction_v4.h	(revision 177)
+++ trunk/modules/vci_mem_cache_v4/caba/source/include/xram_transaction_v4.h	(revision 184)
@@ -14,22 +14,22 @@
 
 class TransactionTabEntry {
-  typedef uint32_t size_t;
-  typedef uint32_t data_t;
-  typedef sc_dt::sc_uint<40> addr_t;
-  typedef uint32_t be_t;
+  typedef uint32_t              size_t;
+  typedef uint32_t              data_t;
+  typedef sc_dt::sc_uint<40>    addr_t;
+  typedef uint32_t              be_t;
 
  public:
-  bool 		      valid;     	    // entry valid 
-  bool 		      xram_read; 	    // read request to XRAM
-  addr_t   	      nline;    	    // index (zy) of the requested line
-  size_t 	      srcid;     	    // processor requesting the transaction
-  size_t 	      trdid;     	    // processor requesting the transaction
-  size_t 	      pktid;     	    // processor requesting the transaction
-  bool 		      proc_read;	    // read request from processor
-  size_t 		  read_length;      // length of the read (for the response)
-  size_t 	      word_index;    	// index of the first read word (for the response)
-  std::vector<data_t> wdata;        // write buffer (one cache line)
-  std::vector<be_t>   wdata_be;    	// be for each data in the write buffer
-  bool            rerror;           // error returned by xram
+  bool 		            valid;     	    // entry valid 
+  bool 		            xram_read; 	    // read request to XRAM
+  addr_t   	            nline;    	    // index (zy) of the requested line
+  size_t 	            srcid;     	    // processor requesting the transaction
+  size_t 	            trdid;     	    // processor requesting the transaction
+  size_t 	            pktid;     	    // processor requesting the transaction
+  bool 		            proc_read;	    // read request from processor
+  size_t 	            read_length;    // length of the read (for the response)
+  size_t 	            word_index;    	// index of the first read word (for the response)
+  std::vector<data_t>   wdata;          // write buffer (one cache line)
+  std::vector<be_t>     wdata_be;    	// be for each data in the write buffer
+  bool                  rerror;         // error returned by xram
 
   /////////////////////////////////////////////////////////////////////
@@ -39,4 +39,5 @@
   {
     valid		= false;
+    rerror      = false;
   }
 
@@ -50,6 +51,7 @@
     wdata_be.reserve( (int)n_words );
     wdata.reserve( (int)n_words );
-    for(size_t i=0; i<n_words; i++){
-      wdata_be.push_back(false);
+    for(size_t i=0; i<n_words; i++)
+    {
+      wdata_be.push_back(0);
       wdata.push_back(0);
     }
@@ -352,5 +354,6 @@
     tab[index].read_length	    = read_length;
     tab[index].word_index	    = word_index;
-    for(size_t i=0; i<tab[index].wdata.size(); i++) {
+    for(size_t i=0; i<tab[index].wdata.size(); i++) 
+    {
       tab[index].wdata_be[i]    = data_be[i];
       tab[index].wdata[i]       = data[i];
@@ -361,9 +364,10 @@
   // The write_rsp() function writes a word of the response to an 
   // XRAM read transaction.
-  // The data is only written when the corresponding BE field is Ox0.
+  // The BE field in TRT is taken into account.
   // Arguments :
   // - index : the index of the transaction in the transaction tab
   // - word_index : the index of the data in the line
   // - data : the data to write
+  // - error : invalid data
   /////////////////////////////////////////////////////////////////////
   void write_rsp(const size_t index,
@@ -396,4 +400,5 @@
 	    && "The selected entry is out of range in erase() Transaction Tab");
     tab[index].valid	= false;
+    tab[index].rerror   = false;
   }
 }; // end class TransactionTab
