Changeset 196 for trunk/modules


Ignore:
Timestamp:
Feb 19, 2012, 5:39:16 PM (12 years ago)
Author:
alain
Message:

Fixing 2 bugs:
1/ The coherence requests must be taken in state DCACHE_XTN_WRITE to avoid dead-locks.
2/ Completion of the ITLB flush was not properly handled in the DCACHE_XTN_SWITCH state.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp

    r195 r196  
    12291229    //
    12301230    // In case of uncacheable address, the ICACHE FSM request an uncached VCI transaction
    1231     // to CMD FSM usig the r_icache_unc_req flip-flop, that reset this flip-flop
     1231    // to CMD FSM using the r_icache_unc_req flip-flop, that reset this flip-flop
    12321232    // when the transaction starts. The ICACHE FSM goes to ICACHE_UNC_WAIT to wait
    12331233    // the response from the RSP FSM, through the response fifo. The missing instruction
     
    12401240    // the update is completed, and reset r_icache_tlb_miss_req to signal the completion.
    12411241    //
    1242     // The DCACHE FSM signals XTN processor requests using the r_dcache_xtn_req flip-flop.
     1242    // The DCACHE FSM signals XTN processor requests to ICACHE_FSM
     1243    // using the r_dcache_xtn_req flip-flop.
    12431244    // The request opcode and the address to be invalidated are transmitted
    12441245    // in the r_dcache_xtn_opcode and r_dcache_p0_wdata registers respectively.
     
    32933294    case DCACHE_XTN_SWITCH:             // Both itlb and dtlb must be flushed
    32943295    {
    3295         if ( r_dcache_xtn_req.read() )
     3296        if ( not r_dcache_xtn_req.read() )
    32963297        {
    32973298            r_dtlb.flush();
     
    33033304    /////////////////////
    33043305    case DCACHE_XTN_SYNC:               // waiting until write buffer empty
    3305     {
     3306                                        // The coherence request must be taken
     3307                                        // as there is a risk of dead-lock
     3308    {
     3309        // external coherence request
     3310        if ( r_tgt_dcache_req.read() )   
     3311        {
     3312            r_dcache_fsm = DCACHE_CC_CHECK;
     3313            r_dcache_fsm_save = DCACHE_XTN_SYNC;
     3314        }       
     3315
    33063316        if ( r_wbuf.empty() )
    33073317        {
     
    35563566              << " / set = "   << set
    35573567              << " / valid = "  << valid
    3558               << " / line = " << victim << std::endl;
     3568              << " / line = " << std::hex << victim << std::endl;
    35593569}
    35603570#endif
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