Changeset 253 for trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp
- Timestamp:
- Aug 16, 2012, 2:41:27 PM (12 years ago)
- File:
-
- 1 edited
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- Added
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trunk/modules/vci_cc_vcache_wrapper_v4/caba/source/src/vci_cc_vcache_wrapper_v4.cpp
r251 r253 2042 2042 if ( m_debug_dcache_fsm ) 2043 2043 { 2044 std::cout << " <PROC .DCACHE_IDLE> Cache update in P2 stage" << std::dec2044 std::cout << " <PROC " << name() << ".DCACHE_IDLE> Cache update in P2 stage" << std::dec 2045 2045 << " / WAY = " << way 2046 2046 << " / SET = " << set … … 2490 2490 if ( m_debug_dcache_fsm ) 2491 2491 { 2492 std::cout << " <PROC .DCACHE_IDLE> HIT in dtlb, but privilege violation" << std::endl;2492 std::cout << " <PROC " << name() << ".DCACHE_IDLE> HIT in dtlb, but privilege violation" << std::endl; 2493 2493 } 2494 2494 #endif … … 2506 2506 if ( m_debug_dcache_fsm ) 2507 2507 { 2508 std::cout << " <PROC .DCACHE_IDLE> HIT in dtlb, but writable violation" << std::endl;2508 std::cout << " <PROC " << name() << ".DCACHE_IDLE> HIT in dtlb, but writable violation" << std::endl; 2509 2509 } 2510 2510 #endif … … 2555 2555 if ( m_debug_dcache_fsm ) 2556 2556 { 2557 std::cout << " <PROC .DCACHE_IDLE> Speculative access miss" << std::endl;2557 std::cout << " <PROC " << name() << ".DCACHE_IDLE> Speculative access miss" << std::endl; 2558 2558 } 2559 2559 #endif … … 2589 2589 if ( m_debug_dcache_fsm ) 2590 2590 { 2591 std::cout << " <PROC .DCACHE_IDLE> HIT in dcache" << std::endl;2591 std::cout << " <PROC " << name() << ".DCACHE_IDLE> HIT in dcache" << std::endl; 2592 2592 } 2593 2593 #endif … … 2777 2777 if ( r_dcache_tlb_ins.read() ) 2778 2778 { 2779 std::cout << " <PROC .DCACHE_TLB_MISS> ITLB miss";2779 std::cout << " <PROC " << name() << ".DCACHE_TLB_MISS> ITLB miss"; 2780 2780 } 2781 2781 else 2782 2782 { 2783 std::cout << " <PROC .DCACHE_TLB_MISS> DTLB miss";2783 std::cout << " <PROC " << name() << ".DCACHE_TLB_MISS> DTLB miss"; 2784 2784 } 2785 2785 std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read() … … 2831 2831 if ( m_debug_dcache_fsm ) 2832 2832 { 2833 std::cout << " <PROC .DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"2833 std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped" 2834 2834 << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() 2835 2835 << std::dec << " / way = " << way … … 2866 2866 if ( m_debug_dcache_fsm ) 2867 2867 { 2868 std::cout << " <PROC .DCACHE_TLB_PTE1_GET> HIT in dcache"2868 std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache" 2869 2869 << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() 2870 2870 << std::dec << " / way = " << way … … 2887 2887 if ( m_debug_dcache_fsm ) 2888 2888 { 2889 std::cout << " <PROC .DCACHE_TLB_PTE1_GET> HIT in dcache"2889 std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache" 2890 2890 << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() 2891 2891 << std::dec << " / way = " << way … … 2907 2907 if ( m_debug_dcache_fsm ) 2908 2908 { 2909 std::cout << " <PROC .DCACHE_TLB_PTE1_GET> MISS in dcache:"2909 std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_GET> MISS in dcache:" 2910 2910 << " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl; 2911 2911 } … … 2948 2948 { 2949 2949 if ( r_dcache_tlb_ins.read() ) 2950 std::cout << " <PROC .DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";2950 std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:"; 2951 2951 else 2952 std::cout << " <PROC .DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";2952 std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:"; 2953 2953 std::cout << " way = " << std::dec << way 2954 2954 << " / set = " << set << std::endl; … … 3033 3033 if ( r_dcache_tlb_ins.read() ) 3034 3034 { 3035 std::cout << " <PROC .DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB";3035 std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB"; 3036 3036 std::cout << " / set = " << std::dec << r_dcache_tlb_set.read() 3037 3037 << " / way = " << r_dcache_tlb_way.read() << std::endl; … … 3040 3040 else 3041 3041 { 3042 std::cout << " <PROC .DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB";3042 std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB"; 3043 3043 std::cout << " / set = " << std::dec << r_dcache_tlb_set.read() 3044 3044 << " / way = " << r_dcache_tlb_way.read() << std::endl; … … 3092 3092 if ( m_debug_dcache_fsm ) 3093 3093 { 3094 std::cout << " <PROC .DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped"3094 std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped" 3095 3095 << " PTE_FLAGS = " << std::hex << pte_flags 3096 3096 << " PTE_PPN = " << std::hex << pte_ppn << std::endl; … … 3111 3111 if ( m_debug_dcache_fsm ) 3112 3112 { 3113 std::cout << " <PROC .DCACHE_TLB_PTE2_GET> HIT in dcache:"3113 std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE2_GET> HIT in dcache:" 3114 3114 << " PTE_FLAGS = " << std::hex << pte_flags 3115 3115 << " PTE_PPN = " << std::hex << pte_ppn << std::endl; … … 3128 3128 if ( m_debug_dcache_fsm ) 3129 3129 { 3130 std::cout << " <PROC .DCACHE_TLB_PTE2_GET> MISS in dcache:"3130 std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE2_GET> MISS in dcache:" 3131 3131 << " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl; 3132 3132 } … … 3166 3166 { 3167 3167 if ( r_dcache_tlb_ins.read() ) 3168 std::cout << " <PROC .DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";3168 std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:"; 3169 3169 else 3170 std::cout << " <PROC .DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";3170 std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:"; 3171 3171 std::cout << " way = " << std::dec << way 3172 3172 << " / set = " << set << std::endl; … … 3252 3252 if ( r_dcache_tlb_ins.read() ) 3253 3253 { 3254 std::cout << " <PROC .DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB";3254 std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB"; 3255 3255 std::cout << " / set = " << std::dec << r_dcache_tlb_set.read() 3256 3256 << " / way = " << r_dcache_tlb_way.read() << std::endl; … … 3259 3259 else 3260 3260 { 3261 std::cout << " <PROC .DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB";3261 std::cout << " <PROC " << name() << ".DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB"; 3262 3262 std::cout << " / set = " << std::dec << r_dcache_tlb_set.read() 3263 3263 << " / way = " << r_dcache_tlb_way.read() << std::endl; … … 3278 3278 if ( m_debug_dcache_fsm ) 3279 3279 { 3280 std::cout << " <PROC .DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;3280 std::cout << " <PROC " << name() << ".DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl; 3281 3281 } 3282 3282 #endif … … 3323 3323 if ( m_debug_dcache_fsm ) 3324 3324 { 3325 std::cout << " <PROC .DCACHE_TLB_LR_WAIT> SC response received" << std::endl;3325 std::cout << " <PROC " << name() << ".DCACHE_TLB_LR_WAIT> SC response received" << std::endl; 3326 3326 } 3327 3327 #endif … … 3337 3337 if ( m_debug_dcache_fsm ) 3338 3338 { 3339 std::cout << " <PROC .DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;3339 std::cout << " <PROC " << name() << ".DCACHE_TLB_RETURN> TLB MISS completed" << std::endl; 3340 3340 } 3341 3341 #endif … … 3492 3492 if ( m_debug_dcache_fsm ) 3493 3493 { 3494 std::cout << " <PROC .DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex3494 std::cout << " <PROC " << name() << ".DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex 3495 3495 << " / VADDR = " << r_dcache_p0_wdata.read() 3496 3496 << " / PADDR = " << paddr << std::endl; … … 3533 3533 if ( m_debug_dcache_fsm ) 3534 3534 { 3535 std::cout << " <PROC .DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex3535 std::cout << " <PROC " << name() << ".DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex 3536 3536 << " / PADDR = " << r_dcache_p0_paddr.read() << std::dec 3537 3537 << " / HIT = " << hit … … 3589 3589 if ( m_debug_dcache_fsm ) 3590 3590 { 3591 std::cout << " <PROC .DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex3591 std::cout << " <PROC " << name() << ".DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex 3592 3592 << " / NLINE = " << nline << std::endl; 3593 3593 } … … 3638 3638 if ( m_debug_dcache_fsm ) 3639 3639 { 3640 std::cout << " <PROC .DCACHE_MISS_VICTIM> Select a slot:" << std::dec3640 std::cout << " <PROC " << name() << ".DCACHE_MISS_VICTIM> Select a slot:" << std::dec 3641 3641 << " / WAY = " << way 3642 3642 << " / SET = " << set … … 3666 3666 if ( m_debug_dcache_fsm ) 3667 3667 { 3668 std::cout << " <PROC .DCACHE_MISS_INVAL> inval line:" << std::dec3668 std::cout << " <PROC " << name() << ".DCACHE_MISS_INVAL> inval line:" << std::dec 3669 3669 << " / way = " << way 3670 3670 << " / set = " << set … … 3844 3844 if ( r_dcache_miss_word.read() < m_dcache_words-1 ) 3845 3845 { 3846 std::cout << " <PROC .DCACHE_MISS_UPDT> Matching coherence request:"3846 std::cout << " <PROC " << name() << ".DCACHE_MISS_UPDT> Matching coherence request:" 3847 3847 << " pop the FIFO, don't update the cache" << std::endl; 3848 3848 } 3849 3849 else 3850 3850 { 3851 std::cout << " <PROC .DCACHE_MISS_UPDT> Matching coherence request:"3851 std::cout << " <PROC " << name() << ".DCACHE_MISS_UPDT> Matching coherence request:" 3852 3852 << " last word : send a cleanup request " << std::endl; 3853 3853 } … … 3855 3855 else 3856 3856 { 3857 std::cout << " <PROC .DCACHE_MISS_UPDT> Write one word:"3857 std::cout << " <PROC " << name() << ".DCACHE_MISS_UPDT> Write one word:" 3858 3858 << " address = " << std::hex << r_dcache_vci_paddr.read() 3859 3859 << " / data = " << r_vci_rsp_fifo_dcache.read() … … 3977 3977 if ( m_debug_dcache_fsm ) 3978 3978 { 3979 std::cout << " <PROC .DCACHE_DIRTY_GET_PTE> Get PTE in dcache" << std::hex3979 std::cout << " <PROC " << name() << ".DCACHE_DIRTY_GET_PTE> Get PTE in dcache" << std::hex 3980 3980 << " / PTE_PADDR = " << r_dcache_dirty_paddr.read() 3981 3981 << " / PTE_VALUE = " << pte << std::dec … … 4016 4016 if ( m_debug_dcache_fsm ) 4017 4017 { 4018 std::cout << " <PROC .DCACHE_DIRTY_SC_WAIT> Dirty bit successfully set"4018 std::cout << " <PROC " << name() << ".DCACHE_DIRTY_SC_WAIT> Dirty bit successfully set" 4019 4019 << std::endl; 4020 4020 } … … 4027 4027 if ( m_debug_dcache_fsm ) 4028 4028 { 4029 std::cout << " <PROC .DCACHE_DIRTY_SC_WAIT> PTE modified : Inval cache line & TLBs"4029 std::cout << " <PROC " << name() << ".DCACHE_DIRTY_SC_WAIT> PTE modified : Inval cache line & TLBs" 4030 4030 << std::endl; 4031 4031 } … … 4093 4093 if ( m_debug_dcache_fsm ) 4094 4094 { 4095 std::cout << " <PROC .DCACHE_CC_CHECK> Coherence request matching a pending miss:"4095 std::cout << " <PROC " << name() << ".DCACHE_CC_CHECK> Coherence request matching a pending miss:" 4096 4096 << " address = " << std::hex << paddr << std::endl; 4097 4097 } … … 4138 4138 { 4139 4139 4140 std::cout << " <PROC .DCACHE_CC_CHECK> Coherence request received :"4140 std::cout << " <PROC " << name() << ".DCACHE_CC_CHECK> Coherence request received :" 4141 4141 << " address = " << std::hex << paddr << std::dec; 4142 4142 if ( hit ) … … 4189 4189 if ( m_debug_dcache_fsm ) 4190 4190 { 4191 std::cout << " <PROC .DCACHE_CC_INVAL> Invalidate cache line" << std::dec4191 std::cout << " <PROC " << name() << ".DCACHE_CC_INVAL> Invalidate cache line" << std::dec 4192 4192 << " / WAY = " << way 4193 4193 << " / SET = " << set << std::endl; … … 4238 4238 if ( m_debug_dcache_fsm ) 4239 4239 { 4240 std::cout << " <PROC .DCACHE_CC_UPDT> Update one word" << std::dec4240 std::cout << " <PROC " << name() << ".DCACHE_CC_UPDT> Update one word" << std::dec 4241 4241 << " / WAY = " << way 4242 4242 << " / SET = " << set … … 4283 4283 if ( m_debug_dcache_fsm and ok ) 4284 4284 { 4285 std::cout << " <PROC .DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex4285 std::cout << " <PROC " << name() << ".DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex 4286 4286 << " line = " << line << std::dec 4287 4287 << " / set = " << set … … 4296 4296 if ( m_debug_dcache_fsm and ok ) 4297 4297 { 4298 std::cout << " <PROC .DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry:" << std::hex4298 std::cout << " <PROC " << name() << ".DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry:" << std::hex 4299 4299 << " line = " << line << std::dec 4300 4300 << " / set = " << set … … 4328 4328 std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl 4329 4329 << " stop at cycle " << m_cpt_total_cycles << std::endl 4330 << " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles 4331 << std::endl;4330 << " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles << std::endl; 4331 r_iss.dump(); 4332 4332 exit(1); 4333 4333 } … … 4767 4767 if ( m_debug_cleanup_fsm ) 4768 4768 { 4769 std::cout << " <PROC .CLEANUP_DATA_GO> Cleanup request for icache:" << std::hex4769 std::cout << " <PROC " << name() << ".CLEANUP_DATA_GO> Cleanup request for icache:" << std::hex 4770 4770 << " address = " << (r_dcache_cleanup_line.read()*m_dcache_words*4) 4771 4771 << " / trdid = " << std::dec << r_cleanup_trdid.read() << std::endl; … … 4786 4786 if ( m_debug_cleanup_fsm ) 4787 4787 { 4788 std::cout << " <PROC .CLEANUP_INS_GO> Cleanup request for dcache:" << std::hex4788 std::cout << " <PROC " << name() << ".CLEANUP_INS_GO> Cleanup request for dcache:" << std::hex 4789 4789 << " address = " << (r_icache_cleanup_line.read()*m_icache_words*4) 4790 4790 << " / trdid = " << std::dec << r_cleanup_trdid.read() << std::endl;
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