Index: trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/include/tsarv4_cluster_mmu.h
===================================================================
--- trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/include/tsarv4_cluster_mmu.h	(revision 249)
+++ trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/include/tsarv4_cluster_mmu.h	(revision 255)
@@ -6,20 +6,4 @@
 // This program is released under the GNU public license
 //////////////////////////////////////////////////////////////////////////////
-// This file define a TSAR cluster architecture with virtual memory:
-// - It uses the virtual_dspin_router  as distributed global interconnect 
-// - It uses the vci_local_crossbar as local interconnect 
-// - It uses the vci_cc_vcache_wrapper_v4
-// - It uses the vci_mem_cache_v4
-// - It contains a private RAM with a variable latency to emulate the L3 cache
-// - It can contains 1, 2 or 4 processors
-// - Each processor has a private dma channel (vci_multi_dma)
-// - It uses the vci_xicu interrupt controller
-// - The peripherals MTTY, BDEV, FBUF, and the boot BROM are in the cluster 
-//   containing address 0xBFC00000.
-// - The Multi-TTY component controls 4 terminals. 
-// - The nprocs dma irqs are connected to IRQ_IN[0]...IRQ_IN[3]
-// - The four tty irqs are connected to IRQ_IN[4]...IRQ_IN[7]
-// - The bdev irq is connected to IRQ_IN[8]
-////////////////////////////////////////////////////////////////////////////////// 
 
 #ifndef SOCLIB_CABA_TSAR_CLUSTER_V4_MMU_H
@@ -62,19 +46,16 @@
 
 	// Ports
-    	sc_in<bool>                             		p_clk;
-    	sc_in<bool>                             		p_resetn;
+    sc_in<bool>                             		p_clk;
+    sc_in<bool>                             		p_resetn;
 	soclib::caba::DspinOutput<cmd_width>   			**p_cmd_out;
 	soclib::caba::DspinInput<cmd_width>    			**p_cmd_in;
-        soclib::caba::DspinOutput<rsp_width>                   	**p_rsp_out;
-        soclib::caba::DspinInput<rsp_width>                   	**p_rsp_in;
+    soclib::caba::DspinOutput<rsp_width>           	**p_rsp_out;
+    soclib::caba::DspinInput<rsp_width>            	**p_rsp_in;
 
-        // interrupt signals
-	sc_signal<bool>     		signal_false;
-	sc_signal<bool> 		signal_proc_it[4];
-	sc_signal<bool> 		signal_irq_mdma[4];
-	sc_signal<bool>			signal_irq_tty0;
-	sc_signal<bool>			signal_irq_tty1;
-	sc_signal<bool>			signal_irq_tty2;
-	sc_signal<bool>			signal_irq_tty3;
+    // interrupt signals
+	sc_signal<bool>     	signal_false;
+	sc_signal<bool> 		signal_proc_it[8];
+	sc_signal<bool> 		signal_irq_mdma[8];
+	sc_signal<bool>			signal_irq_mtty[23];
 	sc_signal<bool> 		signal_irq_bdev;
 	
@@ -117,57 +98,60 @@
 	VciSignals<vci_param> 		signal_vci_xram;
 	
-        // Components
+    // Components
 
-        VciCcVCacheWrapperV4<vci_param, iss_t>*                 	proc[4];
-        VciMemCacheV4<vci_param>*                               	memc;
-        VciXicu<vci_param>*                                     	xicu;
-        VciLocalCrossbar<vci_param>*        				xbard;
-        VciLocalCrossbar<vci_param>*        				xbarc;
-        VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>*		tgtwrapperd;
-        VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>*	iniwrapperd;
-        VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>*		tgtwrapperc;
-        VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>*	iniwrapperc;
-        VirtualDspinRouter<cmd_width>*   	                	cmdrouter;
-        VirtualDspinRouter<rsp_width>*	                        	rsprouter;
-        VciSimpleRam<vci_param>*                 			brom;
-        VciMultiTty<vci_param>*                  			mtty;
-        VciFrameBuffer<vci_param>*               			fbuf;
-        VciBlockDeviceTsarV4<vci_param>*         			bdev;
-        VciMultiDma<vci_param>*                 			mdma;
-        VciSimpleRam<vci_param>*					xram;
+    VciCcVCacheWrapperV4<vci_param, iss_t>*                 	proc[8];
+    VciMemCacheV4<vci_param>*                               	memc;
+    VciXicu<vci_param>*                                     	xicu;
+    VciLocalCrossbar<vci_param>*                                xbard;
+    VciLocalCrossbar<vci_param>*                                xbarc;
+    VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>*      tgtwrapperd;
+    VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>*   iniwrapperd;
+    VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>*      tgtwrapperc;
+    VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>*   iniwrapperc;
+    VirtualDspinRouter<cmd_width>*                              cmdrouter;
+    VirtualDspinRouter<rsp_width>*	                        	rsprouter;
+    VciSimpleRam<vci_param>*                                    brom;
+    VciMultiTty<vci_param>*                                     mtty;
+    VciFrameBuffer<vci_param>*                                  fbuf;
+    VciBlockDeviceTsarV4<vci_param>*                            bdev;
+    VciMultiDma<vci_param>*                                     mdma;
+    VciSimpleRam<vci_param>*                                    xram;
 
-	TsarV4ClusterMmu(sc_module_name  insname,
-                        size_t           nprocs,			    // number of processors 
-			size_t           n_x,				    // x coordinate
-			size_t           n_y,				    // y coordinate
-			size_t           n_cluster,			    // y + ymax*x
-			const            soclib::common::MappingTable &mtd, // direct mapping table
-			const            soclib::common::MappingTable &mtc, // coherence mapping table
-			const            soclib::common::MappingTable &mtx, // xram mapping table
-			size_t	         x_width,			    // x field number of bits
-			size_t	         y_width,			    // y field number of bits
-                        size_t	         tgtid_memc,
-                        size_t	         tgtid_xicu,
-                        size_t	         tgtid_fbuf,
-                        size_t           tgtid_mtty,
-                        size_t           tgtid_brom,
-                        size_t           tgtid_bdev,
-                        size_t           tgtid_mdma,
-                        size_t           memc_ways,			    // number of ways for MEMC
-                        size_t           memc_sets,			    // number of sets for MEMC
-                        size_t           l1_i_ways,			    // number of ways for L1 ICACHE
-                        size_t           l1_i_sets,			    // number of sets for L1 ICACHE
-                        size_t           l1_d_ways,			    // number of ways for L1 DCACHE
-                        size_t           l1_d_sets,			    // number of sets for L1 DCACHE
-                        size_t           xram_latency,			    // external ram latency
-			bool             io,				    // I/O cluster if true
-                        size_t           xfb,				    // frame buffer pixels
-                        size_t           yfb,				    // frame buffer lines
-                        char*            disk_name,			    // virtual disk name for BDEV
-                        size_t           block_size,			    // block size for BDEV
-			const Loader    &loader, 			    // loader for BROM
-                        uint32_t         frozen_cycles,			    // max frozen cycles
-                        uint32_t         start_debug_cycle,
-                        bool             debug_ok); 
+	TsarV4ClusterMmu(sc_module_name                     insname,
+                     size_t                             nb_procs,      // number of processors 
+                     size_t                             nb_ttys,       // number of TTY terminals 
+                     size_t                             nb_dmas,       // number of DMA channels 
+                     size_t                             x,             // x coordinate
+                     size_t                             y,             // y coordinate
+                     size_t                             cluster,       // y + ymax*x
+                     const soclib::common::MappingTable &mtd,          // direct mapping table
+                     const soclib::common::MappingTable &mtc,          // coherence mapping table
+                     const soclib::common::MappingTable &mtx,          // xram mapping table
+                     size_t	                            x_width,       // x field number of bits
+                     size_t	                            y_width,       // y field number of bits
+                     size_t	                            tgtid_memc,
+                     size_t	                            tgtid_xicu,
+                     size_t	                            tgtid_fbuf,
+                     size_t                             tgtid_mtty,
+                     size_t                             tgtid_brom,
+                     size_t                             tgtid_bdev,
+                     size_t                             tgtid_mdma,
+                     size_t                             memc_ways,
+                     size_t                             memc_sets,
+                     size_t                             l1_i_ways,
+                     size_t                             l1_i_sets, 
+                     size_t                             l1_d_ways,
+                     size_t                             l1_d_sets,	
+                     size_t                             xram_latency,  // external ram latency
+                     bool                               io,	           // I/O cluster if true
+                     size_t                             xfb,           // frame buffer pixels
+                     size_t                             yfb,           // frame buffer lines
+                     char*                              disk_name,     // virtual disk name for BDEV
+                     size_t                             block_size,    // block size for BDEV
+			         const Loader                       &loader,       // loader for BROM
+                     uint32_t                           frozen_cycles, // max frozen cycles
+                     uint32_t                           start_debug_cycle,
+                     bool                               memc_debug_ok, 
+                     bool                               proc_debug_ok); 
 
 	~TsarV4ClusterMmu();
Index: trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/src/tsarv4_cluster_mmu.cpp
===================================================================
--- trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/src/tsarv4_cluster_mmu.cpp	(revision 249)
+++ trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/src/tsarv4_cluster_mmu.cpp	(revision 255)
@@ -1,2 +1,27 @@
+//////////////////////////////////////////////////////////////////////////////
+// File: tsarv4_cluster_mmu.c
+// Author: Alain Greiner 
+// Copyright: UPMC/LIP6
+// Date : march 2011
+// This program is released under the GNU public license
+//////////////////////////////////////////////////////////////////////////////
+// This file define a TSAR cluster architecture with virtual memory:
+// - It uses the virtual_dspin_router as distributed global interconnect 
+// - It uses the vci_local_crossbar as local interconnect 
+// - It uses the vci_cc_vcache_wrapper_v4
+// - It uses the vci_mem_cache_v4
+// - It contains a private RAM with a variable latency to emulate the L3 cache
+// - It can contains 1, 2 or 4 processors
+// - Each processor has a private dma channel (vci_multi_dma)
+// - It uses the vci_xicu interrupt controller
+// - The peripherals MTTY, BDEV, FBUF, and the boot BROM are in the cluster 
+//   containing address 0xBFC00000.
+// - The Multi-TTY component controls up to 15 terminals. 
+// - Each Multi-DMA component controls up to 8 DMA channels.
+// - The DMA IRQs are connected to IRQ_IN[8]...IRQ_IN[15]
+// - The TTY IRQs are connected to IRQ_IN[16]...IRQ_IN[30]
+// - The BDEV IRQ is connected to IRQ_IN[31]
+////////////////////////////////////////////////////////////////////////////////// 
+
 #include "../include/tsarv4_cluster_mmu.h"
 
@@ -8,137 +33,115 @@
 //////////////////////////////////////////////////////////////////////////
 template<typename vci_param, typename iss_t, int cmd_width, int rsp_width>
-   TsarV4ClusterMmu<vci_param, iss_t, cmd_width, rsp_width>::TsarV4ClusterMmu(
-         sc_module_name  insname,
-         size_t          nprocs,
-         size_t          x_id,
-         size_t          y_id,
-         size_t          cluster_id,
-         const           soclib::common::MappingTable &mtd,
-         const           soclib::common::MappingTable &mtc, 
-         const           soclib::common::MappingTable &mtx, 
-         size_t          x_width,
-         size_t          y_width,
-         size_t          tgtid_memc,
-         size_t          tgtid_xicu,
-         size_t          tgtid_fbuf,
-         size_t          tgtid_mtty,
-         size_t          tgtid_brom,
-         size_t          tgtid_bdev,
-         size_t          tgtid_mdma,
-         size_t          memc_ways,
-         size_t          memc_sets,
-         size_t          l1_i_ways,
-         size_t          l1_i_sets,
-         size_t          l1_d_ways,
-         size_t          l1_d_sets,
-         size_t          xram_latency,
-         bool            io,
-         size_t          xfb,
-         size_t          yfb,
-         char*           disk_name,
-         size_t          block_size,
-         const Loader   &loader,
-         uint32_t        frozen_cycles,
-         uint32_t        debug_start_cycle,
-         bool            debug_ok)
+TsarV4ClusterMmu<vci_param, iss_t, cmd_width, rsp_width>::TsarV4ClusterMmu(
+         sc_module_name                     insname,
+         size_t                             nb_procs,
+         size_t                             nb_ttys,
+         size_t                             nb_dmas,
+         size_t                             x_id,
+         size_t                             y_id,
+         size_t                             cluster_id,
+         const soclib::common::MappingTable &mtd,
+         const soclib::common::MappingTable &mtc, 
+         const soclib::common::MappingTable &mtx, 
+         size_t                             x_width,
+         size_t                             y_width,
+         size_t                             tgtid_memc,
+         size_t                             tgtid_xicu,
+         size_t                             tgtid_fbuf,
+         size_t                             tgtid_mtty,
+         size_t                             tgtid_brom,
+         size_t                             tgtid_bdev,
+         size_t                             tgtid_mdma,
+         size_t                             memc_ways,
+         size_t                             memc_sets,
+         size_t                             l1_i_ways,
+         size_t                             l1_i_sets,
+         size_t                             l1_d_ways,
+         size_t                             l1_d_sets,
+         size_t                             xram_latency,
+         bool                               io,
+         size_t                             xfb,
+         size_t                             yfb,
+         char*                              disk_name,
+         size_t                             block_size,
+         const Loader                      &loader,
+         uint32_t                           frozen_cycles,
+         uint32_t                           debug_start_cycle,
+         bool                               memc_debug_ok,
+         bool                               proc_debug_ok)
             : soclib::caba::BaseModule(insname),
             p_clk("clk"),
-            p_resetn("resetn"),
-
-            signal_dspin_cmd_l2g_d("signal_dspin_cmd_l2g_d"),
-            signal_dspin_cmd_g2l_d("signal_dspin_cmd_g2l_d"),
-            signal_dspin_cmd_l2g_c("signal_dspin_cmd_l2g_c"),
-            signal_dspin_cmd_g2l_c("signal_dspin_cmd_g2l_c"),
-            signal_dspin_rsp_l2g_d("signal_dspin_rsp_l2g_d"),
-            signal_dspin_rsp_g2l_d("signal_dspin_rsp_g2l_d"),
-            signal_dspin_rsp_l2g_c("signal_dspin_rsp_l2g_c"),
-            signal_dspin_rsp_g2l_c("signal_dspin_rsp_g2l_c"),
-
-            signal_vci_ini_d_bdev("signal_vci_ini_d_bdev"),
-            signal_vci_ini_d_mdma("signal_vci_ini_d_mdma"),
-
-            signal_vci_tgt_d_memc("signal_vci_tgt_d_memc"),
-            signal_vci_tgt_d_mtty("signal_vci_tgt_d_mtty"),
-            signal_vci_tgt_d_xicu("signal_vci_tgt_d_xicu"),
-            signal_vci_tgt_d_bdev("signal_vci_tgt_d_bdev"),
-            signal_vci_tgt_d_mdma("signal_vci_tgt_d_mdma"),
-            signal_vci_tgt_d_brom("signal_vci_tgt_d_brom"),
-            signal_vci_tgt_d_fbuf("signal_vci_tgt_d_fbuf"),
-
-            signal_vci_ini_c_memc("signal_vci_ini_c_memc"), 
-            signal_vci_tgt_c_memc("signal_vci_tgt_c_memc"),
-
-            signal_vci_xram("signal_vci_xram")
-
-            {
-               // Vectors of ports definition
-
-               p_cmd_in        = alloc_elems<DspinInput<cmd_width> >("p_cmd_in", 2, 4);
-               p_cmd_out       = alloc_elems<DspinOutput<cmd_width> >("p_cmd_out", 2, 4);
-               p_rsp_in        = alloc_elems<DspinInput<rsp_width> >("p_rsp_in", 2, 4);
-               p_rsp_out       = alloc_elems<DspinOutput<rsp_width> >("p_rsp_out", 2, 4);
-
-               // Components definition 
-
-               // on direct network : local srcid[proc] in [0...nprocs-1]
-               // on direct network : local srcid[mdma] = nprocs
-               // on direct network : local srcid[bdev] = nprocs + 1
-
-               // on coherence network : local srcid[proc] in [0...nprocs-1]
-               // on coherence network : local srcid[memc] = nprocs
-
-               std::cout << "  - building proc_" << x_id << "_" << y_id << "-*" << std::endl;
-
-               for (size_t p = 0; p < nprocs; p++){ 
-                  std::ostringstream sproc;
-                  sproc << "proc_" << x_id << "_" << y_id << "_" << p;
-                  proc[p] = new VciCcVCacheWrapperV4<vci_param, iss_t>(
-                        sproc.str().c_str(),
-                        cluster_id*nprocs + p,
-                        mtd,                            // Mapping Table Direct
-                        mtc,                            // Mapping Table Coherence
-                        IntTab(cluster_id,p),           // SRCID_D
-                        IntTab(cluster_id,p),           // SRCID_C
-                        IntTab(cluster_id,p),           // TGTID_C
-                        8,                              // ITLB ways
-                        8,                              // ITLB sets
-                        8,                              // DTLB ways
-                        8,                              // DTLB sets
-                        l1_i_ways,l1_i_sets,16,         // ICACHE size
-                        l1_d_ways,l1_d_sets,16,         // DCACHE size
-                        4,                              // WBUF width
-                        4,                              // WBUF depth
-                        x_width,                        // X Width
-                        y_width,                        // Y Width
-                        nprocs,                         // Memory Cache Local Id (coherence)
-                        frozen_cycles,                  // max frozen cycles
-                        debug_start_cycle,
-                        debug_ok);
-               }
-
-               std::cout << "  - building memc_" << x_id << "_" << y_id << std::endl;
-
-               std::ostringstream smemc;
-               smemc << "memc_" << x_id << "_" << y_id;
-               memc = new VciMemCacheV4<vci_param>(
+            p_resetn("resetn")
+
+{
+    // Vectors of ports definition
+
+    p_cmd_in        = alloc_elems<DspinInput<cmd_width> >("p_cmd_in", 2, 4);
+    p_cmd_out       = alloc_elems<DspinOutput<cmd_width> >("p_cmd_out", 2, 4);
+    p_rsp_in        = alloc_elems<DspinInput<rsp_width> >("p_rsp_in", 2, 4);
+    p_rsp_out       = alloc_elems<DspinOutput<rsp_width> >("p_rsp_out", 2, 4);
+
+    // Components definition 
+
+    // on direct network : local srcid[proc] in [0..nb_procs-1]
+    // on direct network : local srcid[mdma] = nb_procs
+    // on direct network : local srcid[bdev] = nb_procs + 1
+
+    // on coherence network : local srcid[proc] in [0...nb_procs-1]
+    // on coherence network : local srcid[memc] = nb_procs
+
+    std::cout << "  - building proc_" << x_id << "_" << y_id << "-*" << std::endl;
+
+    for (size_t p = 0; p < nb_procs; p++)
+    { 
+        std::ostringstream sproc;
+        sproc << "proc_" << x_id << "_" << y_id << "_" << p;
+        proc[p] = new VciCcVCacheWrapperV4<vci_param, iss_t>(
+                      sproc.str().c_str(),
+                      cluster_id*nb_procs + p,
+                      mtd,                            // Mapping Table Direct
+                      mtc,                            // Mapping Table Coherence
+                      IntTab(cluster_id,p),           // SRCID_D
+                      IntTab(cluster_id,p),           // SRCID_C
+                      IntTab(cluster_id,p),           // TGTID_C
+                      8,                              // ITLB ways
+                      8,                              // ITLB sets
+                      8,                              // DTLB ways
+                      8,                              // DTLB sets
+                      l1_i_ways,l1_i_sets,16,         // ICACHE size
+                      l1_d_ways,l1_d_sets,16,         // DCACHE size
+                      4,                              // WBUF nlines
+                      4,                              // WBUF nwords
+                      x_width,
+                      y_width,
+                      nb_procs,                       // MEMC local index
+                      frozen_cycles,                  // max frozen cycles
+                      debug_start_cycle,
+                      proc_debug_ok);
+    }
+
+    std::cout << "  - building memc_" << x_id << "_" << y_id << std::endl;
+
+    std::ostringstream smemc;
+    smemc << "memc_" << x_id << "_" << y_id;
+    memc = new VciMemCacheV4<vci_param>(
                      smemc.str().c_str(),
                      mtd, mtc, mtx,
-                     IntTab(cluster_id),                  // SRCID_X
-                     IntTab(cluster_id, nprocs),          // SRCID_C
-                     IntTab(cluster_id, tgtid_memc),      // TGTID_D
-                     IntTab(cluster_id, nprocs),          // TGTID_C
-                     memc_ways, memc_sets, 16,            // CACHE SIZE
-                     4096,                                // HEAP SIZE
-                     8,                                   // TRANSACTION TABLE DEPTH
-                     8,                                   // UPDATE TABLE DEPTH
+                     IntTab(cluster_id),              // SRCID_X
+                     IntTab(cluster_id, nb_procs),    // SRCID_C
+                     IntTab(cluster_id, tgtid_memc),  // TGTID_D
+                     IntTab(cluster_id, nb_procs),    // TGTID_C
+                     memc_ways, memc_sets, 16,        // CACHE SIZE
+                     4096,                            // HEAP SIZE
+                     8,                               // TRANSACTION TABLE DEPTH
+                     8,                               // UPDATE TABLE DEPTH
                      debug_start_cycle,
-                     debug_ok);
-
-
-               std::cout << "  - building xram_" << x_id << "_" << y_id << std::endl;
-
-               std::ostringstream sxram;
-               sxram << "xram_" << x_id << "_" << y_id;
-               xram = new VciSimpleRam<vci_param>(
+                     memc_debug_ok);
+
+    std::cout << "  - building xram_" << x_id << "_" << y_id << std::endl;
+
+    std::ostringstream sxram;
+    sxram << "xram_" << x_id << "_" << y_id;
+    xram = new VciSimpleRam<vci_param>(
                      sxram.str().c_str(),
                      IntTab(cluster_id),
@@ -147,106 +150,99 @@
                      xram_latency);
 
-               std::cout << "  - building xicu_" << x_id << "_" << y_id << std::endl;
-
-               size_t  nhwi = 4;                               // always 4 (or 9) ports, even if 
-               if (io){
-                  nhwi = 9;                      // there if less than 4 processors
-               }
-               std::ostringstream sicu;
-               sicu << "xicu_" << x_id << "_" << y_id;
-               xicu = new VciXicu<vci_param>(
+    std::cout << "  - building xicu_" << x_id << "_" << y_id << std::endl;
+
+    std::ostringstream sicu;
+    sicu << "xicu_" << x_id << "_" << y_id;
+    xicu = new VciXicu<vci_param>(
                      sicu.str().c_str(),
-                     mtd,                                  // mapping table
-                     IntTab(cluster_id, tgtid_xicu),       // TGTID_D
-                     0,                                    // number of timer IRQs
-                     nhwi,                                 // number of hard IRQs
-                     0,                                    // number of soft IRQs
-                     nprocs);                              // number of output IRQs
-
-               std::cout << "  - building dma_" << x_id << "_" << y_id << std::endl;
-
-               // dma multi-canaux
-               std::ostringstream sdma;
-               sdma << "dma_" << x_id << "_" << y_id;
-               mdma = new VciMultiDma<vci_param>(
+                     mtd,                               // mapping table
+                     IntTab(cluster_id, tgtid_xicu),    // TGTID_D
+                     nb_procs,                          // number of timer IRQs
+                     32,                                // number of hard IRQs
+                     0,                                 // number of soft IRQs
+                     nb_procs);                         // number of output IRQs
+
+    std::cout << "  - building dma_" << x_id << "_" << y_id << std::endl;
+
+    std::ostringstream sdma;
+    sdma << "dma_" << x_id << "_" << y_id;
+    mdma = new VciMultiDma<vci_param>(
                      sdma.str().c_str(),
                      mtd,
-                     IntTab(cluster_id, nprocs),          // SRCID
+                     IntTab(cluster_id, nb_procs),        // SRCID
                      IntTab(cluster_id, tgtid_mdma),      // TGTID
                      64,                                  // burst size
-                     nprocs);                             // number of IRQs
-
-               std::cout << "  - building xbard_" << x_id << "_" << y_id << std::endl;
-
-               // direct local crossbar
-               size_t nb_direct_initiators      = nprocs + 1;
-               size_t nb_direct_targets         = 3;
-               if (io){
-                  nb_direct_initiators         = nprocs + 2;
-                  nb_direct_targets            = 7;
-               }
-               std::ostringstream sd;
-               sd << "xbard_" << x_id << "_" << y_id;
-               xbard = new VciLocalCrossbar<vci_param>(
+                     nb_procs);                           // number of IRQs
+
+    std::cout << "  - building xbard_" << x_id << "_" << y_id << std::endl;
+
+    size_t nb_direct_initiators      = nb_procs + 1;
+    size_t nb_direct_targets         = 3;
+    if ( io )
+    {
+        nb_direct_initiators         = nb_procs + 2;
+        nb_direct_targets            = 7;
+    }
+    std::ostringstream sd;
+    sd << "xbard_" << x_id << "_" << y_id;
+    xbard = new VciLocalCrossbar<vci_param>(
                      sd.str().c_str(),
                      mtd,
-                     IntTab(cluster_id),                 // cluster initiator index
-                     IntTab(cluster_id),                 // cluster target index
-                     nb_direct_initiators,               // number of initiators
-                     nb_direct_targets);                 // number of targets      
-
-               std::cout << "  - building xbarc_" << x_id << "_" << y_id << std::endl;
-
-               // coherence local crossbar
-               std::ostringstream sc;
-               sc << "xbarc_" << x_id << "_" << y_id;
-               xbarc = new VciLocalCrossbar<vci_param>(
+                     IntTab(cluster_id),           // cluster initiator index
+                     IntTab(cluster_id),           // cluster target index
+                     nb_direct_initiators,         // number of initiators
+                     nb_direct_targets);           // number of targets      
+
+    std::cout << "  - building xbarc_" << x_id << "_" << y_id << std::endl;
+
+    std::ostringstream sc;
+    sc << "xbarc_" << x_id << "_" << y_id;
+    xbarc = new VciLocalCrossbar<vci_param>(
                      sc.str().c_str(),
                      mtc,
-                     IntTab(cluster_id),                 // cluster initiator index
-                     IntTab(cluster_id),                 // cluster target index
-                     nprocs + 1,                         // number of initiators
-                     nprocs + 1);                        // number of targets
-
-               std::cout << "  - building wrappers in cluster_" << x_id << "_" << y_id << std::endl;
-
-               // direct initiator wrapper
-               std::ostringstream wid;
-               wid << "iniwrapperd_" << x_id << "_" << y_id;
-               iniwrapperd = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>(
+                     IntTab(cluster_id),           // cluster initiator index
+                     IntTab(cluster_id),           // cluster target index
+                     nb_procs + 1,                 // number of initiators
+                     nb_procs + 1);                // number of targets
+
+    std::cout << "  - building wrappers in cluster_" << x_id << "_" << y_id << std::endl;
+
+    // direct initiator wrapper
+    std::ostringstream wid;
+    wid << "iniwrapperd_" << x_id << "_" << y_id;
+    iniwrapperd = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>(
                      wid.str().c_str(),
                      4,                            // cmd fifo depth
                      4);                           // rsp fifo depth
 
-               // direct target wrapper
-               std::ostringstream wtd;
-               wtd << "tgtwrapperd_" << x_id << "_" << y_id;
-               tgtwrapperd = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>(
+    // direct target wrapper
+    std::ostringstream wtd;
+    wtd << "tgtwrapperd_" << x_id << "_" << y_id;
+    tgtwrapperd = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>(
                      wtd.str().c_str(),
                      4,                            // cmd fifo depth
                      4);                           // rsp fifo depth
 
-               // coherence initiator wrapper
-               std::ostringstream wic;
-               wic << "iniwrapperc_" << x_id << "_" << y_id;
-               iniwrapperc = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>(
+    // coherence initiator wrapper
+    std::ostringstream wic;
+    wic << "iniwrapperc_" << x_id << "_" << y_id;
+    iniwrapperc = new VciVdspinInitiatorWrapper<vci_param,cmd_width,rsp_width>(
                      wic.str().c_str(),
                      4,                            // cmd fifo depth
                      4);                           // rsp fifo depth
 
-               // coherence target wrapper
-               std::ostringstream wtc;
-               wtc << "tgtwrapperc_" << x_id << "_" << y_id;
-               tgtwrapperc = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>(
-                     wtc.str().c_str(),
+    // coherence target wrapper
+    std::ostringstream wtc;
+    wtc << "tgtwrapperc_" << x_id << "_" << y_id;
+    tgtwrapperc = new VciVdspinTargetWrapper<vci_param,cmd_width,rsp_width>(
+    wtc.str().c_str(),
                      4,                            // cmd fifo depth
                      4);                           // rsp fifo depth
 
-               std::cout << "  - building cmdrouter_" << x_id << "_" << y_id << std::endl;
-
-               // CMD router
-               std::ostringstream scmd;
-               scmd << "cmdrouter_" << x_id << "_" << y_id;
-               cmdrouter = new VirtualDspinRouter<cmd_width>(
+    std::cout << "  - building cmdrouter_" << x_id << "_" << y_id << std::endl;
+
+    std::ostringstream scmd;
+    scmd << "cmdrouter_" << x_id << "_" << y_id;
+    cmdrouter = new VirtualDspinRouter<cmd_width>(
                      scmd.str().c_str(),
                      x_id,y_id,                    // coordinate in the mesh
@@ -254,10 +250,10 @@
                      4,4);                         // input & output fifo depths
 
-               std::cout << "  - building rsprouter_" << x_id << "_" << y_id << std::endl;
-
-               // RSP router
-               std::ostringstream srsp;
-               srsp << "rsprouter_" << x_id << "_" << y_id;
-               rsprouter = new VirtualDspinRouter<rsp_width>(
+    std::cout << "  - building rsprouter_" << x_id << "_" << y_id << std::endl;
+
+    // RSP router
+    std::ostringstream srsp;
+    srsp << "rsprouter_" << x_id << "_" << y_id;
+    rsprouter = new VirtualDspinRouter<rsp_width>(
                      srsp.str().c_str(),
                      x_id,y_id,                    // coordinates in mesh
@@ -265,7 +261,10 @@
                      4,4);                         // input & output fifo depths
 
-               // IO cluster components
-               if (io){
-                  brom = new VciSimpleRam<vci_param>(
+    // IO cluster components
+    if ( io )
+    {
+        std::cout << "  - building brom" << std::endl;
+
+        brom = new VciSimpleRam<vci_param>(
                         "brom",
                         IntTab(cluster_id, tgtid_brom),
@@ -273,5 +272,7 @@
                         loader);
 
-                  fbuf = new VciFrameBuffer<vci_param>(
+        std::cout << "  - building fbuf" << std::endl;
+
+        fbuf = new VciFrameBuffer<vci_param>(
                         "fbuf",
                         IntTab(cluster_id, tgtid_fbuf),
@@ -279,199 +280,250 @@
                         xfb, yfb); 
 
-                  bdev = new VciBlockDeviceTsarV4<vci_param>(
+        std::cout << "  - building fbuf" << std::endl;
+
+        bdev = new VciBlockDeviceTsarV4<vci_param>(
                         "bdev",
                         mtd,
-                        IntTab(cluster_id, nprocs+1),
+                        IntTab(cluster_id, nb_procs+1),
                         IntTab(cluster_id, tgtid_bdev),
                         disk_name,
-                        block_size);
-
-                  mtty = new VciMultiTty<vci_param>(
+                        block_size,
+                        4);            // burst size
+
+        std::cout << "  - building mtty" << std::endl;
+
+        std::vector<std::string> vect_names;
+        for( size_t tid = 0 ; tid < (nb_ttys) ; tid++ )
+        {
+            std::ostringstream term_name;
+            term_name <<  "term" << tid;
+            vect_names.push_back(term_name.str().c_str());
+        }
+        mtty = new VciMultiTty<vci_param>(
                         "mtty",
                         IntTab(cluster_id, tgtid_mtty),
                         mtd, 
-                        "tty0", "tty1", "tty2", "tty3", NULL);
-               }
-
-               std::cout << "  - all components constructed" << std::endl;
-
-               ////////////////////////////////////
-               // Connections are defined here
-               ////////////////////////////////////
-
-               // CMDROUTER and RSPROUTER
-               cmdrouter->p_clk                        (this->p_clk);
-               cmdrouter->p_resetn                     (this->p_resetn);
-               rsprouter->p_clk                        (this->p_clk);
-               rsprouter->p_resetn                     (this->p_resetn);
-               for (int x = 0; x < 2; x++){
-                  for(int y = 0; y < 4; y++){
-                     cmdrouter->p_out[x][y]            (this->p_cmd_out[x][y]);
-                     cmdrouter->p_in[x][y]             (this->p_cmd_in[x][y]);
-                     rsprouter->p_out[x][y]            (this->p_rsp_out[x][y]);
-                     rsprouter->p_in[x][y]             (this->p_rsp_in[x][y]);
-                  }
-               }
-
-               cmdrouter->p_out[0][4]                  (signal_dspin_cmd_g2l_d);
-               cmdrouter->p_out[1][4]                  (signal_dspin_cmd_g2l_c);
-               cmdrouter->p_in[0][4]                   (signal_dspin_cmd_l2g_d);
-               cmdrouter->p_in[1][4]                   (signal_dspin_cmd_l2g_c);
-
-               rsprouter->p_out[0][4]                  (signal_dspin_rsp_g2l_d);
-               rsprouter->p_out[1][4]                  (signal_dspin_rsp_g2l_c);
-               rsprouter->p_in[0][4]                   (signal_dspin_rsp_l2g_d);
-               rsprouter->p_in[1][4]                   (signal_dspin_rsp_l2g_c);
-
-               // VCI/DSPIN WRAPPERS
-               iniwrapperd->p_clk                      (this->p_clk);
-               iniwrapperd->p_resetn                   (this->p_resetn);
-               iniwrapperd->p_vci                      (signal_vci_l2g_d);
-               iniwrapperd->p_dspin_out                (signal_dspin_cmd_l2g_d);
-               iniwrapperd->p_dspin_in                 (signal_dspin_rsp_g2l_d);
-
-               tgtwrapperd->p_clk                      (this->p_clk);
-               tgtwrapperd->p_resetn                   (this->p_resetn);
-               tgtwrapperd->p_vci                      (signal_vci_g2l_d);
-               tgtwrapperd->p_dspin_out                (signal_dspin_rsp_l2g_d);
-               tgtwrapperd->p_dspin_in                 (signal_dspin_cmd_g2l_d);
-
-               iniwrapperc->p_clk                      (this->p_clk);
-               iniwrapperc->p_resetn                   (this->p_resetn);
-               iniwrapperc->p_vci                      (signal_vci_l2g_c);
-               iniwrapperc->p_dspin_out                (signal_dspin_cmd_l2g_c);
-               iniwrapperc->p_dspin_in                 (signal_dspin_rsp_g2l_c);
-
-               tgtwrapperc->p_clk                      (this->p_clk);
-               tgtwrapperc->p_resetn                   (this->p_resetn);
-               tgtwrapperc->p_vci                      (signal_vci_g2l_c);
-               tgtwrapperc->p_dspin_out                (signal_dspin_rsp_l2g_c);
-               tgtwrapperc->p_dspin_in                 (signal_dspin_cmd_g2l_c);
-
-               // CROSSBAR direct
-               xbard->p_clk                            (this->p_clk);
-               xbard->p_resetn                         (this->p_resetn);
-               xbard->p_initiator_to_up                (signal_vci_l2g_d);
-               xbard->p_target_to_up                   (signal_vci_g2l_d);
-
-               xbard->p_to_target[tgtid_memc]          (signal_vci_tgt_d_memc);
-               xbard->p_to_target[tgtid_xicu]          (signal_vci_tgt_d_xicu);
-               xbard->p_to_target[tgtid_mdma]          (signal_vci_tgt_d_mdma);
-
-               xbard->p_to_initiator[nprocs]           (signal_vci_ini_d_mdma);
-
-               for (size_t p = 0; p < nprocs; p++){
-                  xbard->p_to_initiator[p]            (signal_vci_ini_d_proc[p]);
-               }
-
-               if (io){
-                  xbard->p_to_target[tgtid_mtty]      (signal_vci_tgt_d_mtty);
-                  xbard->p_to_target[tgtid_brom]      (signal_vci_tgt_d_brom);
-                  xbard->p_to_target[tgtid_bdev]      (signal_vci_tgt_d_bdev);
-                  xbard->p_to_target[tgtid_fbuf]      (signal_vci_tgt_d_fbuf);
-
-                  xbard->p_to_initiator[nprocs+1]     (signal_vci_ini_d_bdev);
-               }
-
-               // CROSSBAR coherence
-               xbarc->p_clk                            (this->p_clk);
-               xbarc->p_resetn                         (this->p_resetn);
-               xbarc->p_initiator_to_up                (signal_vci_l2g_c);
-               xbarc->p_target_to_up                   (signal_vci_g2l_c);
-               xbarc->p_to_initiator[nprocs]           (signal_vci_ini_c_memc);
-               xbarc->p_to_target[nprocs]              (signal_vci_tgt_c_memc);
-               for (size_t p = 0; p < nprocs; p++) {
-                  xbarc->p_to_target[p]                (signal_vci_tgt_c_proc[p]);
-                  xbarc->p_to_initiator[p]             (signal_vci_ini_c_proc[p]);
-               }
-
-               // Processors
-               for (size_t p = 0; p < nprocs; p++){
-                  proc[p]->p_clk                       (this->p_clk);
-                  proc[p]->p_resetn                    (this->p_resetn);
-                  proc[p]->p_vci_ini_d                 (signal_vci_ini_d_proc[p]);
-                  proc[p]->p_vci_ini_c                 (signal_vci_ini_c_proc[p]);
-                  proc[p]->p_vci_tgt_c                 (signal_vci_tgt_c_proc[p]);
-                  proc[p]->p_irq[0]                    (signal_proc_it[p]);
-                  for ( size_t j = 1 ; j < 6 ; j++){
-                     proc[p]->p_irq[j]                 (signal_false);
-                  }
-               }
-
-               // XICU
-               xicu->p_clk                             (this->p_clk);
-               xicu->p_resetn                          (this->p_resetn);
-               xicu->p_vci                             (signal_vci_tgt_d_xicu);
-               for (size_t p = 0; p < nprocs; p++){
-                  xicu->p_irq[p] (signal_proc_it[p]);
-               }
-               for (size_t p = 0; p < nprocs; p++){
-                  xicu->p_hwi[p] (signal_irq_mdma[p]);
-               }
-               for (size_t x = nprocs; x < 4; x++){
-                  xicu->p_hwi[x] (signal_false);
-               }
-
-               if (io){
-                  xicu->p_hwi[4]         (signal_irq_tty0);
-                  xicu->p_hwi[5]         (signal_irq_tty1);
-                  xicu->p_hwi[6]         (signal_irq_tty2);
-                  xicu->p_hwi[7]         (signal_irq_tty3);
-
-                  xicu->p_hwi[8]         (signal_irq_bdev);
-               }
-
-               // MEMC
-               memc->p_clk                             (this->p_clk);
-               memc->p_resetn                          (this->p_resetn);
-               memc->p_vci_ixr                         (signal_vci_xram);
-               memc->p_vci_tgt                         (signal_vci_tgt_d_memc);
-               memc->p_vci_ini                         (signal_vci_ini_c_memc);
-               memc->p_vci_tgt_cleanup                 (signal_vci_tgt_c_memc);
-
-               // XRAM
-               xram->p_clk                             (this->p_clk);
-               xram->p_resetn                          (this->p_resetn);
-               xram->p_vci                             (signal_vci_xram);
-
-               // CDMA
-               mdma->p_clk                             (this->p_clk);
-               mdma->p_resetn                          (this->p_resetn);
-               mdma->p_vci_target                      (signal_vci_tgt_d_mdma);
-               mdma->p_vci_initiator                   (signal_vci_ini_d_mdma);
-               for (size_t p = 0; p < nprocs; p++){
-                  mdma->p_irq[p]                       (signal_irq_mdma[p]);
-               }
-
-               // Components in IO cluster
-
-               if (io){
-                  // BDEV            
-                  bdev->p_clk                         (this->p_clk);
-                  bdev->p_resetn                      (this->p_resetn);
-                  bdev->p_irq                         (signal_irq_bdev);
-                  bdev->p_vci_target                  (signal_vci_tgt_d_bdev);
-                  bdev->p_vci_initiator               (signal_vci_ini_d_bdev);
-
-                  // FBUF
-                  fbuf->p_clk                         (this->p_clk);
-                  fbuf->p_resetn                      (this->p_resetn);
-                  fbuf->p_vci                         (signal_vci_tgt_d_fbuf);
-
-                  // BROM
-                  brom->p_clk                         (this->p_clk);
-                  brom->p_resetn                      (this->p_resetn);
-                  brom->p_vci                         (signal_vci_tgt_d_brom);
-
-                  // MTTY
-                  mtty->p_clk                         (this->p_clk);
-                  mtty->p_resetn                      (this->p_resetn);
-                  mtty->p_vci                         (signal_vci_tgt_d_mtty);
-                  mtty->p_irq[0]                      (signal_irq_tty0);
-                  mtty->p_irq[1]                      (signal_irq_tty1);
-                  mtty->p_irq[2]                      (signal_irq_tty2);
-                  mtty->p_irq[3]                      (signal_irq_tty3);
-               }
-            } // end constructor
+                        vect_names);
+    }
+
+    std::cout << std::endl;
+
+    ////////////////////////////////////
+    // Connections are defined here
+    ////////////////////////////////////
+
+    // CMDROUTER and RSPROUTER
+    cmdrouter->p_clk                        (this->p_clk);
+    cmdrouter->p_resetn                     (this->p_resetn);
+    rsprouter->p_clk                        (this->p_clk);
+    rsprouter->p_resetn                     (this->p_resetn);
+    for (int x = 0; x < 2; x++)
+    {
+        for(int y = 0; y < 4; y++)
+        {
+            cmdrouter->p_out[x][y]          (this->p_cmd_out[x][y]);
+            cmdrouter->p_in[x][y]           (this->p_cmd_in[x][y]);
+            rsprouter->p_out[x][y]          (this->p_rsp_out[x][y]);
+            rsprouter->p_in[x][y]           (this->p_rsp_in[x][y]);
+        }
+    }
+
+    cmdrouter->p_out[0][4]                  (signal_dspin_cmd_g2l_d);
+    cmdrouter->p_out[1][4]                  (signal_dspin_cmd_g2l_c);
+    cmdrouter->p_in[0][4]                   (signal_dspin_cmd_l2g_d);
+    cmdrouter->p_in[1][4]                   (signal_dspin_cmd_l2g_c);
+
+    rsprouter->p_out[0][4]                  (signal_dspin_rsp_g2l_d);
+    rsprouter->p_out[1][4]                  (signal_dspin_rsp_g2l_c);
+    rsprouter->p_in[0][4]                   (signal_dspin_rsp_l2g_d);
+    rsprouter->p_in[1][4]                   (signal_dspin_rsp_l2g_c);
+
+    std::cout << "  - CMD & RSP routers connected" << std::endl;
+
+    // VCI/DSPIN WRAPPERS
+    iniwrapperd->p_clk                      (this->p_clk);
+    iniwrapperd->p_resetn                   (this->p_resetn);
+    iniwrapperd->p_vci                      (signal_vci_l2g_d);
+    iniwrapperd->p_dspin_out                (signal_dspin_cmd_l2g_d);
+    iniwrapperd->p_dspin_in                 (signal_dspin_rsp_g2l_d);
+
+    tgtwrapperd->p_clk                      (this->p_clk);
+    tgtwrapperd->p_resetn                   (this->p_resetn);
+    tgtwrapperd->p_vci                      (signal_vci_g2l_d);
+    tgtwrapperd->p_dspin_out                (signal_dspin_rsp_l2g_d);
+    tgtwrapperd->p_dspin_in                 (signal_dspin_cmd_g2l_d);
+
+    iniwrapperc->p_clk                      (this->p_clk);
+    iniwrapperc->p_resetn                   (this->p_resetn);
+    iniwrapperc->p_vci                      (signal_vci_l2g_c);
+    iniwrapperc->p_dspin_out                (signal_dspin_cmd_l2g_c);
+    iniwrapperc->p_dspin_in                 (signal_dspin_rsp_g2l_c);
+
+    tgtwrapperc->p_clk                      (this->p_clk);
+    tgtwrapperc->p_resetn                   (this->p_resetn);
+    tgtwrapperc->p_vci                      (signal_vci_g2l_c);
+    tgtwrapperc->p_dspin_out                (signal_dspin_rsp_l2g_c);
+    tgtwrapperc->p_dspin_in                 (signal_dspin_cmd_g2l_c);
+
+    std::cout << "  - VCI/DSPIN wrappers connected" << std::endl;
+
+    // CROSSBAR direct
+    xbard->p_clk                            (this->p_clk);
+    xbard->p_resetn                         (this->p_resetn);
+    xbard->p_initiator_to_up                (signal_vci_l2g_d);
+    xbard->p_target_to_up                   (signal_vci_g2l_d);
+
+    xbard->p_to_target[tgtid_memc]          (signal_vci_tgt_d_memc);
+    xbard->p_to_target[tgtid_xicu]          (signal_vci_tgt_d_xicu);
+    xbard->p_to_target[tgtid_mdma]          (signal_vci_tgt_d_mdma);
+
+    xbard->p_to_initiator[nb_procs]         (signal_vci_ini_d_mdma);
+
+    for (size_t p = 0; p < nb_procs; p++)
+    {
+        xbard->p_to_initiator[p]            (signal_vci_ini_d_proc[p]);
+    }
+
+    if ( io )
+    {
+        xbard->p_to_target[tgtid_mtty]      (signal_vci_tgt_d_mtty);
+        xbard->p_to_target[tgtid_brom]      (signal_vci_tgt_d_brom);
+        xbard->p_to_target[tgtid_bdev]      (signal_vci_tgt_d_bdev);
+        xbard->p_to_target[tgtid_fbuf]      (signal_vci_tgt_d_fbuf);
+
+        xbard->p_to_initiator[nb_procs+1]   (signal_vci_ini_d_bdev);
+    }
+
+    std::cout << "  - Direct crossbar connected" << std::endl;
+
+    // CROSSBAR coherence
+    xbarc->p_clk                            (this->p_clk);
+    xbarc->p_resetn                         (this->p_resetn);
+    xbarc->p_initiator_to_up                (signal_vci_l2g_c);
+    xbarc->p_target_to_up                   (signal_vci_g2l_c);
+    xbarc->p_to_initiator[nb_procs]         (signal_vci_ini_c_memc);
+    xbarc->p_to_target[nb_procs]            (signal_vci_tgt_c_memc);
+    for (size_t p = 0; p < nb_procs; p++) 
+    {
+        xbarc->p_to_target[p]               (signal_vci_tgt_c_proc[p]);
+        xbarc->p_to_initiator[p]            (signal_vci_ini_c_proc[p]);
+    }
+
+    std::cout << "  - Coherence crossbar connected" << std::endl;
+
+    // Processors
+    for (size_t p = 0; p < nb_procs; p++)
+    {
+        proc[p]->p_clk                      (this->p_clk);
+        proc[p]->p_resetn                   (this->p_resetn);
+        proc[p]->p_vci_ini_d                (signal_vci_ini_d_proc[p]);
+        proc[p]->p_vci_ini_c                (signal_vci_ini_c_proc[p]);
+        proc[p]->p_vci_tgt_c                (signal_vci_tgt_c_proc[p]);
+        proc[p]->p_irq[0]                   (signal_proc_it[p]);
+        for ( size_t j = 1 ; j < 6 ; j++)
+        {
+            proc[p]->p_irq[j]               (signal_false);
+        }
+    }
+
+    std::cout << "  - Processors connected" << std::endl;
+
+    // XICU
+    xicu->p_clk                     	(this->p_clk);
+    xicu->p_resetn                  	(this->p_resetn);
+    xicu->p_vci                     	(signal_vci_tgt_d_xicu);
+    for ( size_t p=0 ; p<nb_procs ; p++)
+    {
+        xicu->p_irq[p]              	(signal_proc_it[p]);
+    }
+    for ( size_t i=0 ; i<32 ; i++)
+    {
+        if ( io ) // I/O cluster
+        {
+            if      (i < 8)                  xicu->p_hwi[i] (signal_false);
+            else if (i < (8 + nb_dmas))      xicu->p_hwi[i]	(signal_irq_mdma[i-8]);
+            else if (i < 16)                 xicu->p_hwi[i] (signal_false);
+            else if (i < (16 + nb_ttys))     xicu->p_hwi[i] (signal_irq_mtty[i-16]);
+            else if (i < 31)                 xicu->p_hwi[i]	(signal_false);
+            else                             xicu->p_hwi[i] (signal_irq_bdev);
+        }
+        else      // other clusters
+        {
+            if      (i < 8)                  xicu->p_hwi[i] (signal_false);
+            else if (i < (8 + nb_dmas))      xicu->p_hwi[i]	(signal_irq_mdma[i-8]);
+            else                             xicu->p_hwi[i]	(signal_false);
+        }
+    }
+
+    std::cout << "  - XICU connected" << std::endl;
+
+    // MEMC
+    memc->p_clk                     	(this->p_clk);
+    memc->p_resetn                  	(this->p_resetn);
+    memc->p_vci_ixr                 	(signal_vci_xram);
+    memc->p_vci_tgt                 	(signal_vci_tgt_d_memc);
+    memc->p_vci_ini                 	(signal_vci_ini_c_memc);
+    memc->p_vci_tgt_cleanup         	(signal_vci_tgt_c_memc);
+
+    std::cout << "  - MEMC connected" << std::endl;
+
+    // XRAM
+    xram->p_clk                     	(this->p_clk);
+    xram->p_resetn                  	(this->p_resetn);
+    xram->p_vci                 		(signal_vci_xram);
+
+    std::cout << "  - XRAM connected" << std::endl;
+
+    // CDMA
+    mdma->p_clk                       	(this->p_clk);
+    mdma->p_resetn                    	(this->p_resetn);
+    mdma->p_vci_target                	(signal_vci_tgt_d_mdma);
+    mdma->p_vci_initiator             	(signal_vci_ini_d_mdma);
+    for (size_t i=0 ; i<nb_dmas ; i++)
+    {
+        mdma->p_irq[i]                  (signal_irq_mdma[i]);
+    }
+
+    std::cout << "  - MDMA connected" << std::endl;
+
+	 // Components in I/O cluster
+
+	 if ( io )
+	 {
+        // BDEV            
+	     bdev->p_clk                      	(this->p_clk);
+        bdev->p_resetn                   	(this->p_resetn);
+        bdev->p_irq                      	(signal_irq_bdev);
+        bdev->p_vci_target               	(signal_vci_tgt_d_bdev);
+        bdev->p_vci_initiator            	(signal_vci_ini_d_bdev);
+
+        std::cout << "  - BDEV connected" << std::endl;
+
+        // FBUF
+        fbuf->p_clk                       	(this->p_clk);
+        fbuf->p_resetn                    	(this->p_resetn);
+        fbuf->p_vci                       	(signal_vci_tgt_d_fbuf);
+
+        std::cout << "  - FBUF connected" << std::endl;
+
+        // BROM
+        brom->p_clk                       	(this->p_clk);
+        brom->p_resetn                    	(this->p_resetn);
+        brom->p_vci                       	(signal_vci_tgt_d_brom);
+
+        std::cout << "  - BROM connected" << std::endl;
+
+        // MTTY
+        mtty->p_clk                       	(this->p_clk);
+        mtty->p_resetn                    	(this->p_resetn);
+        mtty->p_vci                       	(signal_vci_tgt_d_mtty);
+        for ( size_t i=0 ; i<nb_ttys ; i++ )
+        {
+            mtty->p_irq[i]           		(signal_irq_mtty[i]);
+        }
+
+        std::cout << "  - MTTY connected" << std::endl;
+   }
+} // end constructor
 
 ///////////////////////////////////////////////////////////////////////////
@@ -479,5 +531,5 @@
 ///////////////////////////////////////////////////////////////////////////
 template<typename vci_param, typename iss_t, int cmd_width, int rsp_width>
-   TsarV4ClusterMmu<vci_param, iss_t, cmd_width, rsp_width>::~TsarV4ClusterMmu() {}
+TsarV4ClusterMmu<vci_param, iss_t, cmd_width, rsp_width>::~TsarV4ClusterMmu() {}
 
 }
