Changeset 260 for trunk/modules/vci_block_device_tsar_v4/caba/source/src/vci_block_device_tsar_v4.cpp
- Timestamp:
- Sep 4, 2012, 6:47:24 PM (12 years ago)
- File:
-
- 1 edited
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trunk/modules/vci_block_device_tsar_v4/caba/source/src/vci_block_device_tsar_v4.cpp
r256 r260 45 45 { 46 46 r_initiator_fsm = M_IDLE; 47 r_target_fsm = T_IDLE;48 r_irq_enable = true;49 r_go = false;50 47 r_target_fsm = T_IDLE; 48 r_irq_enable = true; 49 r_go = false; 50 return; 51 51 } 52 52 … … 57 57 58 58 switch(r_target_fsm) { 59 //////////// 59 60 case T_IDLE: 60 61 { … … 64 65 r_trdid = p_vci_target.trdid.read(); 65 66 r_pktid = p_vci_target.pktid.read(); 66 67 sc_dt::sc_uint<vci_param::N> address = p_vci_target.address.read(); 67 68 bool read = (p_vci_target.cmd.read() == vci_param::CMD_READ); 68 69 uint32_t cell = (uint32_t)((address & 0x1F)>>2); 69 70 70 if ( !read && !m_segment.contains(address) ) r_target_fsm = T_WRITE_ERROR; 71 else if( read && !m_segment.contains(address) ) r_target_fsm = T_READ_ERROR; 72 else if( !read && !p_vci_target.eop.read() ) r_target_fsm = T_WRITE_ERROR; 73 else if( read && !p_vci_target.eop.read() ) r_target_fsm = T_READ_ERROR; 74 else if( !read && (cell == BLOCK_DEVICE_BUFFER) ) r_target_fsm = T_WRITE_BUFFER; 75 else if( read && (cell == BLOCK_DEVICE_BUFFER) ) r_target_fsm = T_READ_BUFFER; 76 else if( !read && (cell == BLOCK_DEVICE_COUNT) ) r_target_fsm = T_WRITE_COUNT; 77 else if( read && (cell == BLOCK_DEVICE_COUNT) ) r_target_fsm = T_READ_COUNT; 78 else if( !read && (cell == BLOCK_DEVICE_LBA) ) r_target_fsm = T_WRITE_LBA; 79 else if( read && (cell == BLOCK_DEVICE_LBA) ) r_target_fsm = T_READ_LBA; 80 else if( !read && (cell == BLOCK_DEVICE_OP) ) r_target_fsm = T_WRITE_OP; 81 else if( read && (cell == BLOCK_DEVICE_STATUS) ) r_target_fsm = T_READ_STATUS; 82 else if( !read && (cell == BLOCK_DEVICE_IRQ_ENABLE) ) r_target_fsm = T_WRITE_IRQEN; 83 else if( read && (cell == BLOCK_DEVICE_IRQ_ENABLE) ) r_target_fsm = T_READ_IRQEN; 84 else if( read && (cell == BLOCK_DEVICE_SIZE) ) r_target_fsm = T_READ_SIZE; 85 else if( read && (cell == BLOCK_DEVICE_BLOCK_SIZE) ) r_target_fsm = T_READ_BLOCK; 86 } 87 break; 88 } 71 if ( !read && !m_segment.contains(address) ) r_target_fsm = T_WRITE_ERROR; 72 else if( read && !m_segment.contains(address) ) r_target_fsm = T_READ_ERROR; 73 else if( !read && !p_vci_target.eop.read() ) r_target_fsm = T_WRITE_ERROR; 74 else if( read && !p_vci_target.eop.read() ) r_target_fsm = T_READ_ERROR; 75 else if( !read && (cell == BLOCK_DEVICE_BUFFER) ) r_target_fsm = T_WRITE_BUFFER; 76 else if( read && (cell == BLOCK_DEVICE_BUFFER) ) r_target_fsm = T_READ_BUFFER; 77 else if( !read && (cell == BLOCK_DEVICE_COUNT) ) r_target_fsm = T_WRITE_COUNT; 78 else if( read && (cell == BLOCK_DEVICE_COUNT) ) r_target_fsm = T_READ_COUNT; 79 else if( !read && (cell == BLOCK_DEVICE_LBA) ) r_target_fsm = T_WRITE_LBA; 80 else if( read && (cell == BLOCK_DEVICE_LBA) ) r_target_fsm = T_READ_LBA; 81 else if( !read && (cell == BLOCK_DEVICE_OP) ) r_target_fsm = T_WRITE_OP; 82 else if( read && (cell == BLOCK_DEVICE_STATUS) ) r_target_fsm = T_READ_STATUS; 83 else if( !read && (cell == BLOCK_DEVICE_IRQ_ENABLE) ) r_target_fsm = T_WRITE_IRQEN; 84 else if( read && (cell == BLOCK_DEVICE_IRQ_ENABLE) ) r_target_fsm = T_READ_IRQEN; 85 else if( read && (cell == BLOCK_DEVICE_SIZE) ) r_target_fsm = T_READ_SIZE; 86 else if( read && (cell == BLOCK_DEVICE_BLOCK_SIZE) ) r_target_fsm = T_READ_BLOCK; 87 } 88 break; 89 } 90 //////////////////// 89 91 case T_WRITE_BUFFER: 90 92 { … … 93 95 break; 94 96 } 97 /////////////////// 95 98 case T_WRITE_COUNT: 96 99 { … … 99 102 break; 100 103 } 104 ///////////////// 101 105 case T_WRITE_LBA: 102 106 { … … 105 109 break; 106 110 } 111 //////////////// 107 112 case T_WRITE_OP: 108 113 { … … 123 128 break; 124 129 } 130 /////////////////// 125 131 case T_WRITE_IRQEN: 126 132 { … … 129 135 break; 130 136 } 137 /////////////////// 131 138 case T_READ_BUFFER: 132 139 case T_READ_COUNT: … … 141 148 break; 142 149 } 150 /////////////////// 143 151 case T_READ_STATUS: 144 152 { … … 155 163 } // end switch target fsm 156 164 157 ///////////////////////////////////////////////////////////////////////// 158 // The initiator FSM controls the following registers : 159 // r_initiator_fsm, r_flit_count, r_block_count, m_local_buffer 160 ///////////////////////////////////////////////////////////////////////// 161 switch(r_initiator_fsm) { 162 case M_IDLE : // waiting for activation 163 { 164 if ( r_go ) 165 { 165 ////////////////////////////////////////////////////////////////////////////// 166 // The initiator FSM executes a loop, transfering one block per iteration. 167 // Each block is split in bursts, and the number of bursts depends 168 // on the memory buffer alignment on a burst boundary: 169 // - If buffer aligned, all burst have the same length (m_flits_per burst) 170 // and the number of bursts is (m_bursts_per_block). 171 // - If buffer not aligned, the number of bursts is (m_bursts_per_block + 1) 172 // and first and last burst are shorter, because all flits in a burst 173 // must be contained in a single cache line. 174 // first burst => nflits = m_flits_per_burst - offset 175 // last burst => nflits = offset 176 // other burst => nflits = m_flits_per_burst 177 ////////////////////////////////////////////////////////////////////////////// 178 179 switch( r_initiator_fsm.read() ) { 180 //////////// 181 case M_IDLE: // check buffer alignment to compute the number of bursts 182 { 183 if ( r_go.read() ) 184 { 185 r_index = 0; 166 186 r_block_count = 0; 167 187 r_burst_count = 0; … … 169 189 r_latency_count = m_latency; 170 190 171 if ( r_read ) r_initiator_fsm = M_READ_BLOCK; 172 else r_initiator_fsm = M_WRITE_CMD; 173 } 174 break; 175 } 191 // compute r_burst_offset (zero when buffer aligned) 192 r_burst_offset = (r_buf_address.read()>>2) % m_flits_per_burst; 193 194 // start tranfer 195 if ( r_read.read() ) r_initiator_fsm = M_READ_BLOCK; 196 else r_initiator_fsm = M_WRITE_BURST; 197 } 198 break; 199 } 200 ////////////////// 176 201 case M_READ_BLOCK: // read one block from disk after waiting m_latency cycles 202 { 203 if ( r_latency_count.read() == 0 ) 204 { 205 r_latency_count = m_latency; 206 ::lseek(m_fd, (r_lba + r_block_count)*m_flits_per_block*4, SEEK_SET); 207 if( ::read(m_fd, r_local_buffer, m_flits_per_block*4) < 0 ) 208 { 209 r_initiator_fsm = M_READ_ERROR; 210 } 211 else 212 { 213 r_burst_count = 0; 214 r_flit_count = 0; 215 r_initiator_fsm = M_READ_BURST; 216 } 217 } 218 else 219 { 220 r_latency_count = r_latency_count.read() - 1; 221 } 222 break; 223 } 224 ////////////////// 225 case M_READ_BURST: // Compute the number of flits in the burst 226 { 227 uint32_t offset = r_burst_offset.read(); 228 229 if ( offset ) // buffer not aligned 230 { 231 if ( r_burst_count.read() == 0 ) r_burst_nflits = m_flits_per_burst - offset; 232 else if ( r_burst_count.read() == m_bursts_per_block ) r_burst_nflits = offset; 233 else r_burst_nflits = m_flits_per_burst; 234 } 235 else // buffer aligned 236 { 237 r_burst_nflits = m_flits_per_burst; 238 } 239 r_initiator_fsm = M_READ_CMD; 240 break; 241 } 242 //////////////// 243 case M_READ_CMD: // Send a multi-flits VCI WRITE command 244 { 245 if ( p_vci_initiator.cmdack.read() ) 246 { 247 if ( r_flit_count == (r_burst_nflits.read() - 1) ) // last flit in a burst 248 { 249 r_initiator_fsm = M_READ_RSP; 250 r_flit_count = 0; 251 } 252 else // not the last flit 253 { 254 r_flit_count = r_flit_count.read() + 1; 255 } 256 257 // compute next flit address and next local buffer index 258 r_buf_address = r_buf_address.read() + 4; 259 r_index = r_index.read() + 1; 260 } 261 break; 262 } 263 //////////////// 264 case M_READ_RSP: // Wait a single flit VCI WRITE response 265 { 266 if ( p_vci_initiator.rspval.read() ) 267 { 268 bool aligned = (r_burst_offset.read() == 0); 269 270 if ( (p_vci_initiator.rerror.read()&0x1) != 0 ) 271 { 272 r_initiator_fsm = M_READ_ERROR; 273 } 274 else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or 275 (aligned and (r_burst_count.read() == (m_bursts_per_block-1))) ) 276 { 277 if ( r_block_count.read() == (r_nblocks.read()-1) ) // last burst of last block 278 { 279 r_initiator_fsm = M_READ_SUCCESS; 280 } 281 else // last burst not last block 282 { 283 r_index = 0; 284 r_burst_count = 0; 285 r_block_count = r_block_count.read() + 1; 286 r_initiator_fsm = M_READ_BLOCK; 287 } 288 } 289 else // not the last burst 290 { 291 r_burst_count = r_burst_count.read() + 1; 292 r_initiator_fsm = M_READ_BURST; 293 } 294 } 295 break; 296 } 297 /////////////////// 298 case M_READ_SUCCESS: 299 case M_READ_ERROR: 300 { 301 if( !r_go ) r_initiator_fsm = M_IDLE; 302 break; 303 } 304 /////////////////// 305 case M_WRITE_BURST: // Compute the number of flits in the burst 306 { 307 uint32_t offset = r_burst_offset.read(); 308 309 if ( offset ) // buffer not aligned 310 { 311 if ( r_burst_count.read() == 0 ) r_burst_nflits = m_flits_per_burst - offset; 312 else if ( r_burst_count.read() == m_bursts_per_block ) r_burst_nflits = offset; 313 else r_burst_nflits = m_flits_per_burst; 314 } 315 else // buffer aligned 316 { 317 r_burst_nflits = m_flits_per_burst; 318 } 319 r_initiator_fsm = M_WRITE_CMD; 320 break; 321 } 322 ///////////////// 323 case M_WRITE_CMD: // This is actually a single flit VCI READ command 324 { 325 if ( p_vci_initiator.cmdack.read() ) r_initiator_fsm = M_WRITE_RSP; 326 break; 327 } 328 ///////////////// 329 case M_WRITE_RSP: // This is actually a multi-flits VCI READ response 330 { 331 bool aligned = (r_burst_offset.read() == 0); 332 333 if ( p_vci_initiator.rspval.read() ) 334 { 335 r_local_buffer[r_index.read()] = (uint32_t)p_vci_initiator.rdata.read(); 336 r_index = r_index.read() + 1; 337 338 if ( p_vci_initiator.reop.read() ) // last flit of the burst 339 { 340 r_flit_count = 0; 341 r_buf_address = r_buf_address.read() + r_burst_nflits.read()<<2; 342 343 if( (p_vci_initiator.rerror.read()&0x1) != 0 ) 344 { 345 r_initiator_fsm = M_WRITE_ERROR; 346 } 347 else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or 348 (aligned and (r_burst_count.read() == (m_bursts_per_block-1))) ) // last burst 349 { 350 r_burst_count = 0; 351 r_block_count = r_block_count.read() + 1; 352 r_initiator_fsm = M_WRITE_BLOCK; 353 } 354 else // not the last burst 355 { 356 r_burst_count = r_burst_count.read() + 1; 357 r_initiator_fsm = M_WRITE_BURST; 358 } 359 } 360 else 361 { 362 r_flit_count = r_flit_count.read() + 1; 363 } 364 } 365 break; 366 } 367 /////////////////// 368 case M_WRITE_BLOCK: // write a block to disk after waiting m_latency cycles 177 369 { 178 370 if ( r_latency_count == 0 ) … … 180 372 r_latency_count = m_latency; 181 373 ::lseek(m_fd, (r_lba + r_block_count)*m_flits_per_block*vci_param::B, SEEK_SET); 182 if( ::read(m_fd, m_local_buffer, m_flits_per_block*vci_param::B) < 0 ) 183 { 184 r_initiator_fsm = M_READ_ERROR; 185 } 186 else 187 { 188 r_initiator_fsm = M_READ_CMD; 189 } 190 } 191 else 192 { 193 r_latency_count = r_latency_count - 1; 194 } 195 break; 196 } 197 case M_READ_CMD: // This is actually a multi-flits VCI WRITE command 198 { 199 if ( p_vci_initiator.cmdack.read() ) 200 { 201 if ( r_flit_count == (m_flits_per_burst - 1) ) 202 { 203 r_initiator_fsm = M_READ_RSP; 204 r_flit_count = 0; 374 if( ::write(m_fd, r_local_buffer, m_flits_per_block*vci_param::B) < 0 ) 375 { 376 r_initiator_fsm = M_WRITE_ERROR; 377 } 378 else if ( r_block_count.read() == r_nblocks.read() ) 379 { 380 r_initiator_fsm = M_WRITE_SUCCESS; 205 381 } 206 382 else 207 383 { 208 r_flit_count = r_flit_count + 1; 209 } 210 } 211 break; 212 } 213 case M_READ_RSP: // This is actually a single flit VCI WRITE response 214 { 215 if ( p_vci_initiator.rspval.read() ) 216 { 217 if ( (p_vci_initiator.rerror.read()&0x1) == 0 ) r_initiator_fsm = M_READ_TEST; 218 else r_initiator_fsm = M_READ_ERROR; 219 } 220 break; 221 } 222 case M_READ_TEST: 223 { 224 if ( r_burst_count.read() == (m_bursts_per_block - 1) ) 225 { 226 if ( r_block_count.read() == (r_nblocks.read() - 1) ) // last burst of the last block 227 { 228 r_burst_count = 0; 229 r_block_count = 0; 230 r_initiator_fsm = M_READ_SUCCESS; 231 } 232 else // last burst but not last block 233 { 234 r_burst_count = 0; 235 r_block_count = r_block_count.read() + 1; 236 r_initiator_fsm = M_READ_BLOCK; 237 } 238 } 239 else // not the last burst of the block 240 { 241 r_burst_count = r_burst_count.read() + 1; 242 r_initiator_fsm = M_READ_CMD; 243 } 244 break; 245 } 246 case M_READ_SUCCESS: 247 { 248 if( !r_go ) r_initiator_fsm = M_IDLE; 249 break; 250 } 251 case M_READ_ERROR: 252 { 253 if( !r_go ) r_initiator_fsm = M_IDLE; 254 break; 255 } 256 case M_WRITE_CMD: // This is actually a single flit VCI READ command 257 { 258 if ( p_vci_initiator.cmdack.read() ) r_initiator_fsm = M_WRITE_RSP; 259 break; 260 } 261 case M_WRITE_RSP: // This is actually a multi-flits VCI READ response 262 { 263 if ( p_vci_initiator.rspval.read() ) 264 { 265 uint32_t index = (r_burst_count.read()*m_flits_per_burst) + r_flit_count.read(); 266 m_local_buffer[index] = (uint32_t)p_vci_initiator.rdata.read(); 267 if ( p_vci_initiator.reop.read() ) 268 { 269 r_flit_count = 0; 270 if( (p_vci_initiator.rerror.read()&0x1) == 0 ) r_initiator_fsm = M_WRITE_TEST; 271 else r_initiator_fsm = M_WRITE_ERROR; 272 } 273 else 274 { 275 r_flit_count = r_flit_count.read() + 1; 276 } 277 } 278 break; 279 } 280 case M_WRITE_TEST: 281 { 282 if ( r_burst_count.read() == (m_bursts_per_block - 1) ) // last burst of the block 283 { 284 r_burst_count = 0; 285 r_block_count = r_block_count.read() + 1; 286 r_initiator_fsm = M_WRITE_BLOCK; 287 } 288 else // not the last burst 289 { 290 r_burst_count = r_burst_count.read() + 1; 291 r_initiator_fsm = M_WRITE_CMD; 292 } 293 break; 294 } 295 case M_WRITE_BLOCK: // write a block to disk after waiting m_latency cycles 296 { 297 if ( r_latency_count == 0 ) 298 { 299 r_latency_count = m_latency; 300 ::lseek(m_fd, (r_lba + r_block_count)*m_flits_per_block*vci_param::B, SEEK_SET); 301 if( ::write(m_fd, m_local_buffer, m_flits_per_block*vci_param::B) < 0 ) 302 { 303 r_initiator_fsm = M_WRITE_ERROR; 304 } 305 else if ( r_block_count.read() == r_nblocks.read() ) 306 { 307 r_initiator_fsm = M_WRITE_SUCCESS; 308 } 309 else 310 { 311 r_initiator_fsm = M_WRITE_CMD; 384 r_initiator_fsm = M_WRITE_BURST; 312 385 } 313 386 } … … 318 391 break; 319 392 } 393 ///////////////////// 320 394 case M_WRITE_SUCCESS: 321 {322 if( !r_go ) r_initiator_fsm = M_IDLE;323 break;324 }325 395 case M_WRITE_ERROR: 326 396 { … … 334 404 tmpl(void)::genMoore() 335 405 { 336 sc_dt::sc_uint<vci_param::N> offset;337 uint32_t index;338 339 406 // p_vci_target port 340 407 p_vci_target.rsrcid = (sc_dt::sc_uint<vci_param::S>)r_srcid.read(); … … 346 413 case T_IDLE: 347 414 p_vci_target.cmdack = true; 348 415 p_vci_target.rspval = false; 349 416 break; 350 417 case T_READ_STATUS: 351 418 p_vci_target.cmdack = false; 352 353 if (r_initiator_fsm == M_IDLE)p_vci_target.rdata = BLOCK_DEVICE_IDLE;354 else if(r_initiator_fsm == M_READ_SUCCESS) 355 else if(r_initiator_fsm == M_WRITE_SUCCESS) 419 p_vci_target.rspval = true; 420 if (r_initiator_fsm == M_IDLE) p_vci_target.rdata = BLOCK_DEVICE_IDLE; 421 else if(r_initiator_fsm == M_READ_SUCCESS) p_vci_target.rdata = BLOCK_DEVICE_READ_SUCCESS; 422 else if(r_initiator_fsm == M_WRITE_SUCCESS) p_vci_target.rdata = BLOCK_DEVICE_WRITE_SUCCESS; 356 423 else if(r_initiator_fsm == M_READ_ERROR) p_vci_target.rdata = BLOCK_DEVICE_READ_ERROR; 357 424 else if(r_initiator_fsm == M_WRITE_ERROR) p_vci_target.rdata = BLOCK_DEVICE_WRITE_ERROR; … … 361 428 case T_READ_BUFFER: 362 429 p_vci_target.cmdack = false; 363 364 p_vci_target.rdata = (uint32_t)r_buf_address ;430 p_vci_target.rspval = true; 431 p_vci_target.rdata = (uint32_t)r_buf_address.read(); 365 432 p_vci_target.rerror = VCI_READ_OK; 366 433 break; 367 434 case T_READ_COUNT: 368 435 p_vci_target.cmdack = false; 369 370 p_vci_target.rdata = (uint32_t)r_nblocks ;436 p_vci_target.rspval = true; 437 p_vci_target.rdata = (uint32_t)r_nblocks.read(); 371 438 p_vci_target.rerror = VCI_READ_OK; 372 439 break; 373 440 case T_READ_LBA: 374 441 p_vci_target.cmdack = false; 375 376 p_vci_target.rdata = (uint32_t)r_lba ;442 p_vci_target.rspval = true; 443 p_vci_target.rdata = (uint32_t)r_lba.read(); 377 444 p_vci_target.rerror = VCI_READ_OK; 378 445 break; 379 446 case T_READ_IRQEN: 380 447 p_vci_target.cmdack = false; 381 382 p_vci_target.rdata = (uint32_t)r_irq_enable ;448 p_vci_target.rspval = true; 449 p_vci_target.rdata = (uint32_t)r_irq_enable.read(); 383 450 p_vci_target.rerror = VCI_READ_OK; 384 451 break; 385 452 case T_READ_SIZE: 386 453 p_vci_target.cmdack = false; 387 454 p_vci_target.rspval = true; 388 455 p_vci_target.rdata = (uint32_t)m_device_size; 389 456 p_vci_target.rerror = VCI_READ_OK; … … 391 458 case T_READ_BLOCK: 392 459 p_vci_target.cmdack = false; 393 460 p_vci_target.rspval = true; 394 461 p_vci_target.rdata = (uint32_t)m_flits_per_block*vci_param::B; 395 462 p_vci_target.rerror = VCI_READ_OK; … … 397 464 case T_READ_ERROR: 398 465 p_vci_target.cmdack = false; 399 466 p_vci_target.rspval = true; 400 467 p_vci_target.rdata = 0; 401 468 p_vci_target.rerror = VCI_READ_ERROR; … … 403 470 case T_WRITE_ERROR: 404 471 p_vci_target.cmdack = false; 405 472 p_vci_target.rspval = true; 406 473 p_vci_target.rdata = 0; 407 474 p_vci_target.rerror = VCI_WRITE_ERROR; … … 427 494 switch (r_initiator_fsm) { 428 495 case M_WRITE_CMD: // It is actually a single flit VCI read command 429 offset = (r_block_count.read()*m_flits_per_block +430 r_burst_count.read()*m_flits_per_burst) * vci_param::B;431 496 p_vci_initiator.rspack = false; 432 497 p_vci_initiator.cmdval = true; 433 p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read() + offset;498 p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read(); 434 499 p_vci_initiator.cmd = vci_param::CMD_READ; 435 500 p_vci_initiator.wdata = 0; 436 501 p_vci_initiator.be = (uint32_t)0xF; 437 p_vci_initiator.plen = (sc_dt::sc_uint<vci_param::K>) m_flits_per_burst*vci_param::B;502 p_vci_initiator.plen = (sc_dt::sc_uint<vci_param::K>)(r_burst_nflits.read()<<2); 438 503 p_vci_initiator.eop = true; 439 504 break; 440 505 case M_READ_CMD: // It is actually a multi-flits VCI WRITE command 441 offset = ( r_block_count.read()*m_flits_per_block +442 r_burst_count.read()*m_flits_per_burst +443 r_flit_count.read() ) * vci_param::B;444 index = (r_burst_count.read()*m_flits_per_burst) + r_flit_count.read();445 506 p_vci_initiator.rspack = false; 446 507 p_vci_initiator.cmdval = true; 447 p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read() + offset;508 p_vci_initiator.address = (sc_dt::sc_uint<vci_param::N>)r_buf_address.read(); 448 509 p_vci_initiator.cmd = vci_param::CMD_WRITE; 449 p_vci_initiator.wdata = (uint32_t) m_local_buffer[index];510 p_vci_initiator.wdata = (uint32_t)r_local_buffer[r_index.read()]; 450 511 p_vci_initiator.be = 0xF; 451 p_vci_initiator.plen = (sc_dt::sc_uint<vci_param::K>) m_flits_per_burst*vci_param::B;452 p_vci_initiator.eop = ( r_flit_count.read() == ( m_flits_per_burst- 1) );512 p_vci_initiator.plen = (sc_dt::sc_uint<vci_param::K>)(r_burst_nflits.read()<<2); 513 p_vci_initiator.eop = ( r_flit_count.read() == (r_burst_nflits.read() - 1) ); 453 514 break; 454 515 case M_READ_RSP: … … 456 517 p_vci_initiator.rspack = true; 457 518 p_vci_initiator.cmdval = false; 458 519 break; 459 520 default: 460 461 462 521 p_vci_initiator.rspack = false; 522 p_vci_initiator.cmdval = false; 523 break; 463 524 } 464 525 … … 472 533 473 534 ////////////////////////////////////////////////////////////////////////////// 474 tmpl(/**/)::VciBlockDeviceTsarV4( sc_core::sc_module_namename,475 const soclib::common::MappingTable&mt,476 const soclib::common::IntTab&srcid,477 const soclib::common::IntTab&tgtid,478 const std::string&filename,479 const uint32_tblock_size,480 const uint32_tburst_size,481 const uint32_tlatency)535 tmpl(/**/)::VciBlockDeviceTsarV4( sc_core::sc_module_name name, 536 const soclib::common::MappingTable &mt, 537 const soclib::common::IntTab &srcid, 538 const soclib::common::IntTab &tgtid, 539 const std::string &filename, 540 const uint32_t block_size, 541 const uint32_t burst_size, 542 const uint32_t latency) 482 543 483 544 : caba::BaseModule(name), … … 512 573 exit(1); 513 574 } 575 if( (burst_size != 1 ) && 576 (burst_size != 2 ) && 577 (burst_size != 4 ) && 578 (burst_size != 8 ) && 579 (burst_size != 16) && 580 (burst_size != 32) && 581 (burst_size != 64) ) 582 { 583 std::cout << "Error in component VciBlockDeviceTsarV4 : " << name << std::endl; 584 std::cout << "The burst size must be 1, 2, 4, 8, 16, 32 or 64 bytes" << std::endl; 585 exit(1); 586 } 514 587 if ( m_segment.size() < 32 ) 515 588 { … … 522 595 std::cout << "Error in component VciBlockDeviceTsarV4 : " << name << std::endl; 523 596 std::cout << "The base address of the segment must be multiple of 32 bytes" << std::endl; 524 exit(1);525 }526 if ( block_size%burst_size != 0 )527 {528 std::cout << "Error in component VciBlockDeviceTsarV4 : " << name << std::endl;529 std::cout << "The block_size parameter must be a multiple of the burst_size" << std::endl;530 597 exit(1); 531 598 } … … 552 619 } 553 620 554 m_local_buffer = new uint32_t[m_flits_per_block]; 555 /* 556 std::cout << std::endl << "Instanciation of VciBlockDeviceTsarV4 : " << name << std::endl; 557 std::cout << " file_name = " << filename << std::endl; 558 std::cout << " burst_size = " << std::dec << m_flits_per_burst*vci_param::B << std::endl; 559 std::cout << " block_size = " << std::dec << m_flits_per_block*vci_param::B << std::endl; 560 std::cout << " latency = " << std::dec << m_latency << std::endl; 561 std::cout << " segment " << m_segment.name() 562 << " | base = 0x" << std::hex << m_segment.baseAddress() 563 << " | size = " << std::dec << m_segment.size() << std::endl; 564 */ 621 r_local_buffer = new uint32_t[m_flits_per_block]; 622 565 623 } // end constructor 566 624 … … 569 627 { 570 628 const char* initiator_str[] = { 571 "IDLE ", 572 "READ_BLOCK ", 573 "READ_CMD ", 574 "READ_RSP ", 575 "READ_TEST ", 576 "READ_SUCCESS ", 577 "READ_ERROR ", 578 "WRITE_BLOCK ", 579 "WRITE_CMD ", 580 "WRITE_RSP ", 581 "WRITE_TEST ", 629 "IDLE", 630 631 "READ_BLOCK", 632 "READ_BURST", 633 "READ_CMD", 634 "READ_RSP", 635 "READ_TEST", 636 "READ_SUCCESS", 637 "READ_ERROR", 638 639 "WRITE_BURST", 640 "WRITE_CMD", 641 "WRITE_RSP", 642 "WRITE_BLOCK", 582 643 "WRITE_SUCCESS", 583 "WRITE_ERROR 644 "WRITE_ERROR", 584 645 }; 585 646 const char* target_str[] = {
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