Changeset 263
- Timestamp:
- Sep 19, 2012, 10:55:24 AM (12 years ago)
- Location:
- trunk/platforms/tsarv4_generic_mmu
- Files:
-
- 4 edited
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top.cpp (modified) (34 diffs)
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tsarv4_cluster_mmu/caba/metadata/tsarv4_cluster_mmu.sd (modified) (1 diff)
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tsarv4_cluster_mmu/caba/source/include/tsarv4_cluster_mmu.h (modified) (6 diffs)
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tsarv4_cluster_mmu/caba/source/src/tsarv4_cluster_mmu.cpp (modified) (12 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/platforms/tsarv4_generic_mmu/top.cpp
r261 r263 7 7 ///////////////////////////////////////////////////////////////////////// 8 8 // This file define a generic TSAR architecture with virtual memory. 9 // The physical address space is 32 bits. 10 // The number of clusters cannot be larger than 256. 11 // The number of processors per cluster cannot be larger than 8. 12 // 9 13 // - It uses vci_local_crossbar as local interconnect 10 14 // - It uses virtual_dspin as global interconnect … … 12 16 // - It uses the vci_mem_cache_v4 13 17 // - It contains one vci_xicu and one vci_multi_dma per cluster. 14 // The peripherals BDEV, FBUF, MTTY, and the boot BROM 15 // are in the cluster containing address 0xBFC00000. 18 // 19 // All clusters are identical, but the cluster containing address 20 // 0xBFC00000 (called io_cluster), that contains 5 extra components: 21 // - the boot rom (BROM) 22 // - the disk controller (BDEV) 23 // - the multi-channel network controller (MNIC) 24 // - the multi-channel tty controller (MTTY) 25 // - the frame buffer controller (FBUF) 16 26 // 17 27 // It is build with one single component implementing a cluster: … … 25 35 // - The BDEV IRQ is connected to IRQ_IN[31] in I/O cluster. 26 36 // 27 // The physical address space is 32 bits. 28 // The number of clusters cannot be larger than 256. 29 // The number of processors per cluster cannot be larger than 8. 37 // The main hardware parameters must be defined in the hard_config.h file : 38 // - CLUSTER_X : number of clusters in a row (power of 2) 39 // - CLUSTER_Y : number of clusters in a column (power of 2) 40 // - CLUSTER_SIZE : size of the segment allocated to a cluster 41 // - NB_PROCS_MAX : number of processors per cluster (power of 2) 42 // - NB_DMAS_MAX : number of DMA channels per cluster (< 9) 43 // - NB_TTYS : number of TTY channels in I/O cluster (< 16) 44 // - NB_NICS : number of NIC channels in I/O cluster (< 9) 45 // 46 // Some secondary hardware parameters must be defined in this top.cpp file: 47 // - XRAM_LATENCY : external ram latency 48 // - MEMC_WAYS : L2 cache number of ways 49 // - MEMC_SETS : L2 cache number of sets 50 // - L1_IWAYS 51 // - L1_ISETS 52 // - L1_DWAYS 53 // - L1_DSETS 54 // - FBUF_X_SIZE : width of frame buffer (pixels) 55 // - FBUF_Y_SIZE : heigth of frame buffer (lines) 56 // - BDEV_SECTOR_SIZE : block size for block drvice 57 // - BDEV_IMAGE_NAME : file pathname for block device 58 // - NIC_RX_NAME : file pathname for NIC received packets 59 // - NIC_TX_NAME : file pathname for NIC transmited packets 60 // - NIC_TIMEOUT : max number of cycles before closing a container 30 61 // 31 // The hardware parameters are :32 // - xmax : number of clusters in a row (power of 2)33 // - ymax : number of clusters in a column (power of 2)34 // - nb_procs : number of processors per cluster (power of 2)35 // - nb_dmas : number of DMA channels per cluster (< 9)36 // - nb_ttys : number of TTYs in I/O cluster (< 16)37 //38 62 // General policy for 32 bits physical address decoding: 39 63 // All segments base addresses are multiple of 64 Kbytes … … 75 99 #include <omp.h> 76 100 #endif 77 ///////////////////////////////////////////////////78 101 79 102 // cluster index (computed from x,y coordinates) 80 #define cluster(x,y) (y + ymax*x)103 #define cluster(x,y) (y + CLUSTER_Y*x) 81 104 82 105 // flit widths for the DSPIN network … … 96 119 #define wrplen_width 1 97 120 98 /////////////////////////////////////////////////// 99 // Parameters default values 100 /////////////////////////////////////////////////// 101 102 #define MESH_XMAX 2 103 #define MESH_YMAX 2 104 105 #define NB_PROCS 1 106 #define NB_TTYS 2 107 #define NB_DMAS 1 121 //////////////////////////////////////////////////////////// 122 // Main Hardware Parameters values 123 //////////////////////i///////////////////////////////////// 124 125 #include "/Users/alain/Documents/licence/almo_svn_2011/soft/giet_vm/hard_config.h" 126 127 //////////////////////////////////////////////////////////// 128 // Secondary Hardware Parameters values 129 //////////////////////i///////////////////////////////////// 108 130 109 131 #define XRAM_LATENCY 0 … … 122 144 123 145 #define BDEV_SECTOR_SIZE 512 124 #define BDEV_IMAGE_NAME "hdd-img.bin" 125 126 #define BOOT_SOFT_NAME "soft.bin" 146 #define BDEV_IMAGE_NAME "/Users/alain/Documents/licence/almo_svn_2011/soft/giet_vm/display/images.raw" 147 148 #define NIC_RX_NAME "/Users/alain/Documents/licence/almo_svn_2011/soft/giet_vm/nic/rx_data.txt" 149 #define NIC_TX_NAME "/Users/alain/Documents/licence/almo_svn_2011/soft/giet_vm/nic/tx_data.txt" 150 #define NIC_TIMEOUT 10000 151 152 //////////////////////////////////////////////////////////// 153 // Software to be loaded in ROM & RAM 154 //////////////////////i///////////////////////////////////// 155 156 #define BOOT_SOFT_NAME "/Users/alain/Documents/licence/almo_svn_2011/soft/giet_vm/soft.elf" 157 158 //////////////////////////////////////////////////////////// 159 // DEBUG Parameters default values 160 //////////////////////i///////////////////////////////////// 127 161 128 162 #define MAX_FROZEN_CYCLES 10000 … … 134 168 // Physical segments definition 135 169 ///////////////////////////////////////////////////////// 136 // There is 3 segments replicated in all clusters: 137 // - seg_memc -> MEMC / BASE = 0x**000000 (12 M bytes) 138 // - seg_icu -> ICU / BASE = 0x**F00000 139 // - seg_dma -> CDMA / BASE = 0x**F30000 140 // 141 // There is 4 specific segments in the "IO" cluster 170 // There is 3 segments replicated in all clusters 171 // and 5 specific segments in the "IO" cluster 142 172 // (containing address 0xBF000000) 143 // - seg_reset -> BROM / BASE = 0xBFC00000 (1 Mbytes) 144 // - seg_fbuf -> FBUF / BASE = 0xBFD00000 (2 M bytes) 145 // - seg_bdev -> BDEV / BASE = 0xBFF10000 146 // - seg_tty -> MTTY / BASE = 0x**F20000 147 // 148 // There is one special segment corresponding to 149 // the processors in the coherence address space 150 // - seg_proc -> PROC / BASE = 0x**B0 to 0xBF 151 /////////////////////////////////////////////////// 173 ///////////////////////////////////////////////////////// 152 174 153 175 // specific segments in "IO" cluster : absolute physical address 154 176 155 177 #define BROM_BASE 0xBFC00000 156 #define BROM_SIZE 0x00100000 157 158 #define FBUF_BASE 0x80D00000 159 #define FBUF_SIZE 0x00200000 160 161 #define BDEV_BASE 0x80F10000 162 #define BDEV_SIZE 0x00001000 163 164 #define MTTY_BASE 0x80F20000 165 #define MTTY_SIZE 0x00001000 166 167 // replicated segments : physical address is incremented by an offset 178 #define BROM_SIZE 0x00100000 // 1 Mbytes 179 180 #define FBUF_BASE 0xBFD00000 181 #define FBUF_SIZE 0x00200000 // 2 Mbytes 182 183 #define BDEV_BASE 0xBFF10000 184 #define BDEV_SIZE 0x00001000 // 4 Kbytes 185 186 #define MTTY_BASE 0xBFF20000 187 #define MTTY_SIZE 0x00001000 // 4 Kbytes 188 189 #define MNIC_BASE 0xBFF80000 190 #define MNIC_SIZE 0x00002000 * (NB_NICS + 1) // 8 Kbytes per channel + 8 Kbytes 191 192 // replicated segments : address is incremented by a cluster offset 168 193 // offset = cluster(x,y) << (address_width-x_width-y_width); 169 194 170 195 #define MEMC_BASE 0x00000000 171 #define MEMC_SIZE 0x00C00000 196 #define MEMC_SIZE 0x00C00000 // 12 Mbytes 172 197 173 198 #define XICU_BASE 0x00F00000 174 #define XICU_SIZE 0x00001000 199 #define XICU_SIZE 0x00001000 // 4 Kbytes 175 200 176 201 #define CDMA_BASE 0x00F30000 177 #define CDMA_SIZE 0x0000 8000202 #define CDMA_SIZE 0x00001000 * NB_DMAS_MAX // 4 Kbytes per channel 178 203 179 204 //////////////////////////////////////////////////////////////////// … … 189 214 #define BROM_TGTID 5 190 215 #define BDEV_TGTID 6 216 #define MNIC_TGTID 7 191 217 192 218 ///////////////////////////////// … … 198 224 199 225 200 char soft_name[256] = BOOT_SOFT_NAME; // pathname to binary code 201 size_t ncycles = 1000000000; // simulated cycles 202 size_t xmax = MESH_XMAX; // number of clusters in a row 203 size_t ymax = MESH_YMAX; // number of clusters in a column 204 size_t nb_procs = NB_PROCS; // number of processors per cluster 205 size_t nb_dmas = NB_DMAS; // number of RDMA channels per cluster 206 size_t nb_ttys = NB_TTYS; // number of TTY terminals in I/O cluster 207 size_t xfb = FBUF_X_SIZE; // frameBuffer column number 208 size_t yfb = FBUF_Y_SIZE; // frameBuffer lines number 209 size_t memc_ways = MEMC_WAYS; 210 size_t memc_sets = MEMC_SETS; 211 size_t l1_d_ways = L1_DWAYS; 212 size_t l1_d_sets = L1_DSETS; 213 size_t l1_i_ways = L1_IWAYS; 214 size_t l1_i_sets = L1_ISETS; 215 char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image 216 size_t blk_size = BDEV_SECTOR_SIZE; // block size (in bytes) 217 size_t xram_latency = XRAM_LATENCY; // external RAM latency 218 ssize_t threads_nr = 1; // simulator's threads number 219 bool debug_ok = false; // trace activated 220 size_t debug_period = 1; // trace period 221 size_t debug_memc_id = TRACE_MEMC_ID; // index of memc to be traced (cluster_id) 222 size_t debug_proc_id = TRACE_PROC_ID; // index of proc to be traced 223 uint32_t debug_from = 0; // trace start cycle 224 uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor 226 char soft_name[256] = BOOT_SOFT_NAME; // pathname to binary code 227 size_t ncycles = 1000000000; // simulated cycles 228 char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image 229 char nic_rx_name[256] = NIC_RX_NAME; // pathname to the rx packets file 230 char nic_tx_name[256] = NIC_TX_NAME; // pathname to the tx packets file 231 ssize_t threads_nr = 1; // simulator's threads number 232 bool debug_ok = false; // trace activated 233 size_t debug_period = 1; // trace period 234 size_t debug_memc_id = TRACE_MEMC_ID; // index of memc to be traced (cluster_id) 235 size_t debug_proc_id = TRACE_PROC_ID; // index of proc to be traced 236 uint32_t debug_from = 0; // trace start cycle 237 uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor 225 238 226 239 ////////////// command line arguments ////////////////////// … … 233 246 ncycles = atoi(argv[n+1]); 234 247 } 235 else if ((strcmp(argv[n],"-NPROCS") == 0) && (n+1<argc))236 {237 nb_procs = atoi(argv[n+1]);238 assert( ((nb_procs == 1) || (nb_procs == 2) ||239 (nb_procs == 4) || (nb_procs == 8)) &&240 "NPROCS must be equal to 1, 2, 4, or 8");241 }242 else if ((strcmp(argv[n],"-NTTYS") == 0) && (n+1<argc))243 {244 nb_ttys = atoi(argv[n+1]);245 assert( (nb_ttys < 16) &&246 "The number of TTY terminals cannot be larger than 15");247 }248 else if ((strcmp(argv[n],"-NDMAS") == 0) && (n+1<argc))249 {250 nb_dmas = atoi(argv[n+1]);251 assert( (nb_dmas < 9) &&252 "The number of DMA channels per cluster cannot be larger than 8");253 }254 else if ((strcmp(argv[n],"-XMAX") == 0) && (n+1<argc))255 {256 xmax = atoi(argv[n+1]);257 assert( ((xmax == 1) || (xmax == 2) || (xmax == 4) || (xmax == 8) || (xmax == 16))258 && "The XMAX parameter must be 2, 4, 8, or 16" );259 }260 261 else if ((strcmp(argv[n],"-YMAX") == 0) && (n+1<argc))262 {263 ymax = atoi(argv[n+1]);264 assert( ((ymax == 1) || (ymax == 2) || (ymax == 4) || (ymax == 8) || (ymax == 16))265 && "The YMAX parameter must be 2, 4, 8, or 16" );266 }267 else if ((strcmp(argv[n],"-XFB") == 0) && (n+1<argc))268 {269 xfb = atoi(argv[n+1]);270 }271 else if ((strcmp(argv[n],"-YFB") == 0) && (n+1<argc) )272 {273 yfb = atoi(argv[n+1]);274 }275 248 else if ((strcmp(argv[n],"-SOFT") == 0) && (n+1<argc) ) 276 249 { … … 281 254 strcpy(disk_name, argv[n+1]); 282 255 } 283 else if ((strcmp(argv[n],"-BLKSZ") == 0) && ((n+1) < argc)) 284 { 285 blk_size = atoi(argv[n+1]); 286 } 287 else if ((strcmp(argv[n],"-TRACE") == 0) && (n+1<argc) ) 256 else if ((strcmp(argv[n],"-DEBUG") == 0) && (n+1<argc) ) 288 257 { 289 258 debug_ok = true; … … 293 262 { 294 263 debug_memc_id = atoi(argv[n+1]); 295 assert( (debug_memc_id < ( xmax*ymax) ) &&264 assert( (debug_memc_id < (CLUSTER_X*CLUSTER_Y) ) && 296 265 "debug_memc_id larger than XMAX * YMAX" ); 297 266 } … … 299 268 { 300 269 debug_proc_id = atoi(argv[n+1]); 301 assert( (debug_proc_id < (xmax*ymax*nb_procs) ) && 302 "debug_proc_id larger than XMAX * YMAX * BN_PROCS" ); 303 } 304 else if ((strcmp(argv[n], "-MCWAYS") == 0) && (n+1 < argc)) 305 { 306 memc_ways = atoi(argv[n+1]); 307 } 308 else if ((strcmp(argv[n], "-MCSETS") == 0) && (n+1 < argc)) 309 { 310 memc_sets = atoi(argv[n+1]); 311 } 312 else if ((strcmp(argv[n], "-XLATENCY") == 0) && (n+1 < argc)) 313 { 314 xram_latency = atoi(argv[n+1]); 270 assert( (debug_proc_id < (CLUSTER_X * CLUSTER_Y * NB_PROCS_MAX) ) && 271 "debug_proc_id larger than XMAX * YMAX * NB_PROCS" ); 315 272 } 316 273 else if ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc)) … … 334 291 std::cout << " -SOFT pathname_for_embedded_soft" << std::endl; 335 292 std::cout << " -DISK pathname_for_disk_image" << std::endl; 336 std::cout << " -BLKSZ disk sector size" << std::endl;337 293 std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl; 338 std::cout << " -NPROCS number_of_processors_per_cluster" << std::endl; 339 std::cout << " -NTTYS total_number_of_TTY_terminals" << std::endl; 340 std::cout << " -NDMAS number_of_DMA_channels_per_cluster" << std::endl; 341 std::cout << " -XMAX number_of_clusters_in_a_row" << std::endl; 342 std::cout << " -YMAX number_of_clusters_in_a_column" << std::endl; 343 std::cout << " -TRACE debug_start_cycle" << std::endl; 344 std::cout << " -MCWAYS memory_cache_number_of_ways" << std::endl; 345 std::cout << " -MCSETS memory_cache_number_of_sets" << std::endl; 346 std::cout << " -XLATENCY external_ram_latency_value" << std::endl; 347 std::cout << " -XFB fram_buffer_number_of_pixels" << std::endl; 348 std::cout << " -YFB fram_buffer_number_of_lines" << std::endl; 294 std::cout << " -DEBUG debug_start_cycle" << std::endl; 349 295 std::cout << " -THREADS simulator's threads number" << std::endl; 350 296 std::cout << " -FROZEN max_number_of_lines" << std::endl; … … 357 303 } 358 304 305 // checking hardware parameters 306 assert( ( (CLUSTER_X == 1) or (CLUSTER_X == 2) or (CLUSTER_X == 4) or 307 (CLUSTER_X == 8) or (CLUSTER_X == 16) ) and 308 "The CLUSTER_X parameter must be 1, 2, 4, 8 or 16" ); 309 310 assert( ( (CLUSTER_Y == 1) or (CLUSTER_Y == 2) or (CLUSTER_Y == 4) or 311 (CLUSTER_Y == 8) or (CLUSTER_Y == 16) ) and 312 "The CLUSTER_Y parameter must be 1, 2, 4, 8 or 16" ); 313 314 assert( ( (NB_PROCS_MAX == 1) or (NB_PROCS_MAX == 2) or 315 (NB_PROCS_MAX == 4) or (NB_PROCS_MAX == 8) ) and 316 "The NB_PROCS_MAX parameter must be 1, 2, 4 or 8" ); 317 318 assert( (NB_DMAS_MAX < 9) and 319 "The NB_DMAS_MAX parameter must be smaller than 9" ); 320 321 assert( (NB_TTYS < 15) and 322 "The NB_TTYS parameter must be smaller than 15" ); 323 324 assert( (NB_NICS < 9) and 325 "The NB_NICS parameter must be smaller than 9" ); 326 359 327 std::cout << std::endl; 360 std::cout << " - NB_CLUSTERS = " << xmax*ymax << std::endl; 361 std::cout << " - NB_PROCS = " << nb_procs << std::endl; 362 std::cout << " - NB_TTYS = " << nb_ttys << std::endl; 363 std::cout << " - NB_DMAS = " << nb_dmas << std::endl; 364 std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl; 365 std::cout << " - MEMC_WAYS = " << memc_ways << std::endl; 366 std::cout << " - MEMC_SETS = " << memc_sets << std::endl; 367 std::cout << " - RAM_LATENCY = " << xram_latency << std::endl; 328 std::cout << " - CLUSTER_X = " << CLUSTER_X << std::endl; 329 std::cout << " - CLUSTER_Y = " << CLUSTER_Y << std::endl; 330 std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl; 331 std::cout << " - NB_DMAS_MAX = " << NB_DMAS_MAX << std::endl; 332 std::cout << " - NB_TTYS = " << NB_TTYS << std::endl; 333 std::cout << " - NB_NICS = " << NB_NICS << std::endl; 334 std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl; 335 std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl; 336 std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl; 337 std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl; 368 338 369 339 std::cout << std::endl; … … 392 362 size_t y_width; 393 363 394 if ( xmax== 1) x_width = 0;395 else if ( xmax== 2) x_width = 1;396 else if ( xmax<= 4) x_width = 2;397 else if ( xmax<= 8) x_width = 3;398 else x_width = 4;399 400 if ( ymax== 1) y_width = 0;401 else if ( ymax== 2) y_width = 1;402 else if ( ymax<= 4) y_width = 2;403 else if ( ymax<= 8) y_width = 3;404 else y_width = 4;364 if (CLUSTER_X == 1) x_width = 0; 365 else if (CLUSTER_X == 2) x_width = 1; 366 else if (CLUSTER_X <= 4) x_width = 2; 367 else if (CLUSTER_X <= 8) x_width = 3; 368 else x_width = 4; 369 370 if (CLUSTER_Y == 1) y_width = 0; 371 else if (CLUSTER_Y == 2) y_width = 1; 372 else if (CLUSTER_Y <= 4) y_width = 2; 373 else if (CLUSTER_Y <= 8) y_width = 3; 374 else y_width = 4; 405 375 406 376 cluster_io_id = 0xBF >> (8 - x_width - y_width); … … 416 386 0x00FF0000); 417 387 418 for (size_t x = 0; x < xmax; x++)388 for (size_t x = 0; x < CLUSTER_X; x++) 419 389 { 420 for (size_t y = 0; y < ymax; y++)390 for (size_t y = 0; y < CLUSTER_Y; y++) 421 391 { 422 392 sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width); … … 439 409 maptabd.add(Segment("d_seg_fbuf", FBUF_BASE, FBUF_SIZE, IntTab(cluster(x,y),FBUF_TGTID), false)); 440 410 maptabd.add(Segment("d_seg_bdev", BDEV_BASE, BDEV_SIZE, IntTab(cluster(x,y),BDEV_TGTID), false)); 411 maptabd.add(Segment("d_seg_mnic", MNIC_BASE, MNIC_SIZE, IntTab(cluster(x,y),MNIC_TGTID), false)); 441 412 maptabd.add(Segment("d_seg_brom", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y),BROM_TGTID), true)); 442 413 } … … 447 418 // coherence network 448 419 // - tgtid_c_proc = srcid_c_proc = local procid 449 // - tgtid_c_memc = srcid_c_memc = nb_procs420 // - tgtid_c_memc = srcid_c_memc = NB_PROCS_MAX 450 421 MappingTable maptabc(address_width, 451 422 IntTab(x_width + y_width, srcid_width - x_width - y_width), … … 453 424 0x00FF0000); 454 425 455 for (size_t x = 0; x < xmax; x++)426 for (size_t x = 0; x < CLUSTER_X; x++) 456 427 { 457 for (size_t y = 0; y < ymax; y++)428 for (size_t y = 0; y < CLUSTER_Y; y++) 458 429 { 459 430 sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width); … … 462 433 std::ostringstream sh; 463 434 sh << "c_seg_memc_" << x << "_" << y; 464 maptabc.add(Segment(sh.str(), ( nb_procs<< (address_width - srcid_width)) + offset,465 0x10, IntTab(cluster(x,y), nb_procs), false));435 maptabc.add(Segment(sh.str(), (NB_PROCS_MAX << (address_width - srcid_width)) + offset, 436 0x10, IntTab(cluster(x,y), NB_PROCS_MAX), false)); 466 437 467 438 // update & invalidate requests must be routed to the proper processor 468 for ( size_t p = 0 ; p < nb_procs; p++)439 for ( size_t p = 0 ; p < NB_PROCS_MAX ; p++) 469 440 { 470 441 std::ostringstream sp; … … 480 451 MappingTable maptabx(address_width, IntTab(1), IntTab(x_width+y_width), 0xF0000000); 481 452 482 for (size_t x = 0; x < xmax; x++)453 for (size_t x = 0; x < CLUSTER_X; x++) 483 454 { 484 for (size_t y = 0; y < ymax; y++)455 for (size_t y = 0; y < CLUSTER_Y ; y++) 485 456 { 486 457 sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width); … … 502 473 // Horizontal inter-clusters DSPIN signals 503 474 DspinSignals<cmd_width>*** signal_dspin_h_cmd_inc = 504 alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_inc", xmax-1, ymax, 2);475 alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_inc", CLUSTER_X-1, CLUSTER_Y, 2); 505 476 DspinSignals<cmd_width>*** signal_dspin_h_cmd_dec = 506 alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_dec", xmax-1, ymax, 2);477 alloc_elems<DspinSignals<cmd_width> >("signal_dspin_h_cmd_dec", CLUSTER_X-1, CLUSTER_Y, 2); 507 478 DspinSignals<rsp_width>*** signal_dspin_h_rsp_inc = 508 alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_inc", xmax-1, ymax, 2);479 alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_inc", CLUSTER_X-1, CLUSTER_Y, 2); 509 480 DspinSignals<rsp_width>*** signal_dspin_h_rsp_dec = 510 alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_dec", xmax-1, ymax, 2);481 alloc_elems<DspinSignals<rsp_width> >("signal_dspin_h_rsp_dec", CLUSTER_X-1, CLUSTER_Y, 2); 511 482 512 483 // Vertical inter-clusters DSPIN signals 513 484 DspinSignals<cmd_width>*** signal_dspin_v_cmd_inc = 514 alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_inc", xmax, ymax-1, 2);485 alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_inc", CLUSTER_X, CLUSTER_Y-1, 2); 515 486 DspinSignals<cmd_width>*** signal_dspin_v_cmd_dec = 516 alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_dec", xmax, ymax-1, 2);487 alloc_elems<DspinSignals<cmd_width> >("signal_dspin_v_cmd_dec", CLUSTER_X, CLUSTER_Y-1, 2); 517 488 DspinSignals<rsp_width>*** signal_dspin_v_rsp_inc = 518 alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_inc", xmax, ymax-1, 2);489 alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_inc", CLUSTER_X, CLUSTER_Y-1, 2); 519 490 DspinSignals<rsp_width>*** signal_dspin_v_rsp_dec = 520 alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_dec", xmax, ymax-1, 2);491 alloc_elems<DspinSignals<rsp_width> >("signal_dspin_v_rsp_dec", CLUSTER_X, CLUSTER_Y-1, 2); 521 492 522 493 // Mesh boundaries DSPIN signals 523 494 DspinSignals<cmd_width>**** signal_dspin_false_cmd_in = 524 alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_in", xmax, ymax, 2, 4);495 alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_in", CLUSTER_X, CLUSTER_Y, 2, 4); 525 496 DspinSignals<cmd_width>**** signal_dspin_false_cmd_out = 526 alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_out", xmax, ymax, 2, 4);497 alloc_elems<DspinSignals<cmd_width> >("signal_dspin_false_cmd_out", CLUSTER_X, CLUSTER_Y, 2, 4); 527 498 DspinSignals<rsp_width>**** signal_dspin_false_rsp_in = 528 alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_in", xmax, ymax, 2, 4);499 alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_in", CLUSTER_X, CLUSTER_Y, 2, 4); 529 500 DspinSignals<rsp_width>**** signal_dspin_false_rsp_out = 530 alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_out", xmax, ymax, 2, 4);501 alloc_elems<DspinSignals<rsp_width> >("signal_dspin_false_rsp_out", CLUSTER_X, CLUSTER_Y, 2, 4); 531 502 532 503 533 504 //////////////////////////// 534 // Components505 // Loader 535 506 //////////////////////////// 536 507 537 508 #if USE_ALMOS 538 509 soclib::common::Loader loader(almos_bootloader_pathname, 539 almos_archinfo_pathname,540 almos_kernel_pathname);510 almos_archinfo_pathname, 511 almos_kernel_pathname); 541 512 #else 542 513 soclib::common::Loader loader(soft_name); … … 546 517 proc_iss::set_loader(loader); 547 518 548 TsarV4ClusterMmu<vci_param, proc_iss, cmd_width, rsp_width>* clusters[xmax][ymax]; 519 //////////////////////////// 520 // Clusters construction 521 //////////////////////////// 522 523 TsarV4ClusterMmu<vci_param, proc_iss, cmd_width, rsp_width>* clusters[CLUSTER_X][CLUSTER_Y]; 549 524 550 525 #if USE_OPENMP 551 552 526 #pragma omp parallel 553 {527 { 554 528 #pragma omp for 555 for(size_t i = 0; i < (xmax * ymax); i++) 556 { 557 size_t x = i / ymax; 558 size_t y = i % ymax; 529 #endif 530 for(size_t i = 0; i < (CLUSTER_X * CLUSTER_Y); i++) 531 { 532 size_t x = i / CLUSTER_Y; 533 size_t y = i % CLUSTER_Y; 534 535 #if USE_OPENMP 559 536 #pragma omp critical 560 561 std::cout << "building cluster_" << x << "_" << y << std::endl; 562 563 std::ostringstream sc; 564 sc << "cluster_" << x << "_" << y; 565 clusters[x][y] = new TsarV4ClusterMmu<vci_param, proc_iss, cmd_width, rsp_width> 566 (sc.str().c_str(), 567 nb_procs, 568 nb_ttys, 569 nb_dmas, 570 x, 571 y, 572 cluster(x,y), 573 maptabd, 574 maptabc, 575 maptabx, 576 x_width, 577 y_width, 578 MEMC_TGTID, 579 XICU_TGTID, 580 FBUF_TGTID, 581 MTTY_TGTID, 582 BROM_TGTID, 583 BDEV_TGTID, 584 CDMA_TGTID, 585 memc_ways, 586 memc_sets, 587 l1_i_ways, 588 l1_i_sets, 589 l1_d_ways, 590 l1_d_sets, 591 xram_latency, 592 (cluster(x,y) == cluster_io_id), 593 xfb, 594 yfb, 595 disk_name, 596 blk_size, 597 loader, 598 frozen_cycles, 599 debug_from, 600 debug_ok and (cluster(x,y) == debug_memc_id), 601 debug_ok and (cluster(x,y) == debug_proc_id) ); 602 603 std::cout << "cluster_" << x << "_" << y << " constructed" << std::endl; 604 605 } 606 } 607 608 #else // NO OPENMP 609 610 for (size_t x = 0; x < xmax; x++) 611 { 612 for (size_t y = 0; y < ymax; y++) 613 { 614 615 std::cout << "building cluster_" << x << "_" << y << std::endl; 616 617 std::ostringstream sc; 618 sc << "cluster_" << x << "_" << y; 619 clusters[x][y] = new TsarV4ClusterMmu<vci_param, proc_iss, cmd_width, rsp_width> 620 (sc.str().c_str(), 621 nb_procs, 622 nb_ttys, 623 nb_dmas, 624 x, 625 y, 626 cluster(x,y), 627 maptabd, 628 maptabc, 629 maptabx, 630 x_width, 631 y_width, 632 MEMC_TGTID, 633 XICU_TGTID, 634 FBUF_TGTID, 635 MTTY_TGTID, 636 BROM_TGTID, 637 BDEV_TGTID, 638 CDMA_TGTID, 639 memc_ways, 640 memc_sets, 641 l1_i_ways, 642 l1_i_sets, 643 l1_d_ways, 644 l1_d_sets, 645 xram_latency, 646 (cluster(x,y) == cluster_io_id), 647 xfb, 648 yfb, 649 disk_name, 650 blk_size, 651 loader, 652 frozen_cycles, 653 debug_from, 654 debug_ok and ( cluster(x,y) == debug_memc_id ), 655 debug_ok and ( cluster(x,y) == debug_proc_id ) ); 656 657 std::cout << "cluster_" << x << "_" << y << " constructed" << std::endl; 658 659 } 660 } 661 662 #endif // USE_OPENMP 537 { 538 #endif 539 std::ostringstream sc; 540 sc << "cluster_" << x << "_" << y; 541 clusters[x][y] = new TsarV4ClusterMmu<vci_param, proc_iss, cmd_width, rsp_width> 542 ( 543 sc.str().c_str(), 544 NB_PROCS_MAX, 545 NB_TTYS, 546 NB_DMAS_MAX, 547 x, 548 y, 549 cluster(x,y), 550 maptabd, 551 maptabc, 552 maptabx, 553 x_width, 554 y_width, 555 MEMC_TGTID, 556 XICU_TGTID, 557 CDMA_TGTID, 558 FBUF_TGTID, 559 MTTY_TGTID, 560 BROM_TGTID, 561 MNIC_TGTID, 562 BDEV_TGTID, 563 MEMC_WAYS, 564 MEMC_SETS, 565 L1_IWAYS, 566 L1_ISETS, 567 L1_DWAYS, 568 L1_DSETS, 569 XRAM_LATENCY, 570 (cluster(x,y) == cluster_io_id), 571 FBUF_X_SIZE, 572 FBUF_Y_SIZE, 573 disk_name, 574 BDEV_SECTOR_SIZE, 575 NB_NICS, 576 nic_rx_name, 577 nic_tx_name, 578 NIC_TIMEOUT, 579 loader, 580 frozen_cycles, 581 debug_from, 582 debug_ok and (cluster(x,y) == debug_memc_id), 583 debug_ok and (cluster(x,y) == debug_proc_id) 584 ); 585 586 std::cout << "cluster_" << x << "_" << y << " constructed" << std::endl; 587 #if USE_OPENMP 588 } // end critical 589 #endif 590 } // end for 591 #if USE_OPENMP 592 } 593 #endif 663 594 664 595 /////////////////////////////////////////////////////////////// … … 667 598 668 599 // Clock & RESET 669 for (size_t x = 0; x < ( xmax); x++){670 for (size_t y = 0; y < ymax; y++){600 for (size_t x = 0; x < (CLUSTER_X); x++){ 601 for (size_t y = 0; y < CLUSTER_Y; y++){ 671 602 clusters[x][y]->p_clk (signal_clk); 672 603 clusters[x][y]->p_resetn (signal_resetn); … … 675 606 676 607 // Inter Clusters horizontal connections 677 if ( xmax> 1){678 for (size_t x = 0; x < ( xmax-1); x++){679 for (size_t y = 0; y < ymax; y++){608 if (CLUSTER_X > 1){ 609 for (size_t x = 0; x < (CLUSTER_X-1); x++){ 610 for (size_t y = 0; y < CLUSTER_Y; y++){ 680 611 for (size_t k = 0; k < 2; k++){ 681 612 clusters[x][y]->p_cmd_out[k][EAST] (signal_dspin_h_cmd_inc[x][y][k]); … … 691 622 } 692 623 } 693 std::cout << "Horizontal connections established" << std::endl;624 std::cout << std::endl << "Horizontal connections established" << std::endl; 694 625 695 626 // Inter Clusters vertical connections 696 if ( ymax> 1) {697 for (size_t y = 0; y < ( ymax-1); y++){698 for (size_t x = 0; x < xmax; x++){627 if (CLUSTER_Y > 1) { 628 for (size_t y = 0; y < (CLUSTER_Y-1); y++){ 629 for (size_t x = 0; x < CLUSTER_X; x++){ 699 630 for (size_t k = 0; k < 2; k++){ 700 631 clusters[x][y]->p_cmd_out[k][NORTH] (signal_dspin_v_cmd_inc[x][y][k]); … … 713 644 714 645 // East & West boundary cluster connections 715 for (size_t y = 0; y < ymax; y++)646 for (size_t y = 0; y < CLUSTER_Y; y++) 716 647 { 717 648 for (size_t k = 0; k < 2; k++) … … 722 653 clusters[0][y]->p_rsp_out[k][WEST] (signal_dspin_false_rsp_out[0][y][k][WEST]); 723 654 724 clusters[ xmax-1][y]->p_cmd_in[k][EAST] (signal_dspin_false_cmd_in[xmax-1][y][k][EAST]);725 clusters[ xmax-1][y]->p_cmd_out[k][EAST] (signal_dspin_false_cmd_out[xmax-1][y][k][EAST]);726 clusters[ xmax-1][y]->p_rsp_in[k][EAST] (signal_dspin_false_rsp_in[xmax-1][y][k][EAST]);727 clusters[ xmax-1][y]->p_rsp_out[k][EAST] (signal_dspin_false_rsp_out[xmax-1][y][k][EAST]);655 clusters[CLUSTER_X-1][y]->p_cmd_in[k][EAST] (signal_dspin_false_cmd_in[CLUSTER_X-1][y][k][EAST]); 656 clusters[CLUSTER_X-1][y]->p_cmd_out[k][EAST] (signal_dspin_false_cmd_out[CLUSTER_X-1][y][k][EAST]); 657 clusters[CLUSTER_X-1][y]->p_rsp_in[k][EAST] (signal_dspin_false_rsp_in[CLUSTER_X-1][y][k][EAST]); 658 clusters[CLUSTER_X-1][y]->p_rsp_out[k][EAST] (signal_dspin_false_rsp_out[CLUSTER_X-1][y][k][EAST]); 728 659 } 729 660 } 730 661 731 662 // North & South boundary clusters connections 732 for (size_t x = 0; x < xmax; x++)663 for (size_t x = 0; x < CLUSTER_X; x++) 733 664 { 734 665 for (size_t k = 0; k < 2; k++) … … 739 670 clusters[x][0]->p_rsp_out[k][SOUTH] (signal_dspin_false_rsp_out[x][0][k][SOUTH]); 740 671 741 clusters[x][ ymax-1]->p_cmd_in[k][NORTH] (signal_dspin_false_cmd_in[x][ymax-1][k][NORTH]);742 clusters[x][ ymax-1]->p_cmd_out[k][NORTH] (signal_dspin_false_cmd_out[x][ymax-1][k][NORTH]);743 clusters[x][ ymax-1]->p_rsp_in[k][NORTH] (signal_dspin_false_rsp_in[x][ymax-1][k][NORTH]);744 clusters[x][ ymax-1]->p_rsp_out[k][NORTH] (signal_dspin_false_rsp_out[x][ymax-1][k][NORTH]);672 clusters[x][CLUSTER_Y-1]->p_cmd_in[k][NORTH] (signal_dspin_false_cmd_in[x][CLUSTER_Y-1][k][NORTH]); 673 clusters[x][CLUSTER_Y-1]->p_cmd_out[k][NORTH] (signal_dspin_false_cmd_out[x][CLUSTER_Y-1][k][NORTH]); 674 clusters[x][CLUSTER_Y-1]->p_rsp_in[k][NORTH] (signal_dspin_false_rsp_in[x][CLUSTER_Y-1][k][NORTH]); 675 clusters[x][CLUSTER_Y-1]->p_rsp_out[k][NORTH] (signal_dspin_false_rsp_out[x][CLUSTER_Y-1][k][NORTH]); 745 676 } 746 677 } … … 755 686 756 687 // network boundaries signals 757 for (size_t x = 0; x < xmax; x++){758 for (size_t y = 0; y < ymax; y++){688 for (size_t x = 0; x < CLUSTER_X ; x++){ 689 for (size_t y = 0; y < CLUSTER_Y ; y++){ 759 690 for (size_t k = 0; k < 2; k++){ 760 691 for (size_t a = 0; a < 4; a++){ … … 785 716 786 717 // trace proc[debug_proc_id] 787 if ( debug_proc_id < ( xmax * ymax * nb_procs) )788 { 789 size_t proc_x = debug_proc_id / ymax;790 size_t proc_y = debug_proc_id % ymax;718 if ( debug_proc_id < (CLUSTER_X * CLUSTER_Y * NB_PROCS_MAX) ) 719 { 720 size_t proc_x = debug_proc_id / CLUSTER_Y; 721 size_t proc_y = debug_proc_id % CLUSTER_Y; 791 722 792 723 clusters[proc_x][proc_y]->proc[0]->print_trace(); … … 798 729 799 730 // trace memc[debug_memc_id] 800 if ( debug_memc_id < ( xmax * ymax) )801 { 802 size_t memc_x = debug_memc_id / ymax;803 size_t memc_y = debug_memc_id % ymax;731 if ( debug_memc_id < (CLUSTER_X * CLUSTER_Y) ) 732 { 733 size_t memc_x = debug_memc_id / CLUSTER_Y; 734 size_t memc_y = debug_memc_id % CLUSTER_Y; 804 735 805 736 clusters[memc_x][memc_y]->memc->print_trace(); … … 810 741 } 811 742 812 // clusters[0][0]->signal_vci_tgt_d_xicu.print_trace("xicu_0_0"); 813 // clusters[0][1]->signal_vci_tgt_d_xicu.print_trace("xicu_0_1"); 814 // clusters[1][0]->signal_vci_tgt_d_xicu.print_trace("xicu_1_0"); 815 // clusters[1][1]->signal_vci_tgt_d_xicu.print_trace("xicu_1_1"); 816 817 // if ( clusters[1][1]->signal_irq_mdma[0].read() ) 818 // std::cout << std::endl << " IRQ_DMA_1_1 activated" << std::endl; 819 // if ( clusters[1][1]->signal_proc_it[0].read() ) 820 // std::cout << " IRQ_PROC_1_1 activated" << std::endl << std::endl; 821 822 // trace ioc component 823 size_t io_x = cluster_io_id / ymax; 824 size_t io_y = cluster_io_id % ymax; 825 // clusters[io_x][io_y]->bdev->print_trace(); 826 // clusters[io_x][io_y]->signal_vci_tgt_d_bdev.print_trace("bdev_1_0_tgt_d "); 827 // clusters[io_x][io_y]->signal_vci_ini_d_bdev.print_trace("bdev_1_0_ini_d "); 828 829 clusters[1][1]->mdma->print_trace(); 830 clusters[1][1]->signal_vci_tgt_d_mdma.print_trace("mdma_1_1_tgt_d "); 831 clusters[1][1]->signal_vci_ini_d_mdma.print_trace("mdma_1_1_ini_d "); 743 // clusters[0][0]->signal_vci_tgt_d_xicu.print_trace("xicu_0_0"); 744 // clusters[0][1]->signal_vci_tgt_d_xicu.print_trace("xicu_0_1"); 745 // clusters[1][0]->signal_vci_tgt_d_xicu.print_trace("xicu_1_0"); 746 // clusters[1][1]->signal_vci_tgt_d_xicu.print_trace("xicu_1_1"); 747 748 // if ( clusters[1][1]->signal_irq_mdma[0].read() ) 749 // std::cout << std::endl << " IRQ_DMA_1_1 activated" << std::endl; 750 // if ( clusters[1][1]->signal_proc_it[0].read() ) 751 // std::cout << " IRQ_PROC_1_1 activated" << std::endl << std::endl; 752 753 // trace ioc component 754 // size_t io_x = cluster_io_id / CLUSTER_Y; 755 // size_t io_y = cluster_io_id % CLUSTER_Y; 756 // clusters[io_x][io_y]->bdev->print_trace(); 757 // clusters[io_x][io_y]->signal_vci_tgt_d_bdev.print_trace("bdev_1_0_tgt_d "); 758 // clusters[io_x][io_y]->signal_vci_ini_d_bdev.print_trace("bdev_1_0_ini_d "); 759 760 // clusters[1][1]->mdma->print_trace(); 761 // clusters[1][1]->signal_vci_tgt_d_mdma.print_trace("mdma_1_1_tgt_d "); 762 // clusters[1][1]->signal_vci_ini_d_mdma.print_trace("mdma_1_1_ini_d "); 763 832 764 } 833 765 -
trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/metadata/tsarv4_cluster_mmu.sd
r255 r263 35 35 Uses('caba:vci_multi_tty'), 36 36 Uses('caba:vci_framebuffer'), 37 Uses('caba:vci_multi_nic'), 37 38 Uses('caba:vci_block_device_tsar_v4'), 38 39 Uses('caba:vci_multi_dma'), -
trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/include/tsarv4_cluster_mmu.h
r255 r263 27 27 #include "vci_vdspin_initiator_wrapper.h" 28 28 #include "vci_multi_tty.h" 29 #include "vci_multi_nic.h" 29 30 #include "vci_block_device_tsar_v4.h" 30 31 #include "vci_framebuffer.h" … … 58 59 sc_signal<bool> signal_irq_mdma[8]; 59 60 sc_signal<bool> signal_irq_mtty[23]; 61 sc_signal<bool> signal_irq_mnic_rx[8]; // unused 62 sc_signal<bool> signal_irq_mnic_tx[8]; // unused 60 63 sc_signal<bool> signal_irq_bdev; 61 64 … … 88 91 VciSignals<vci_param> signal_vci_tgt_d_brom; 89 92 VciSignals<vci_param> signal_vci_tgt_d_fbuf; 93 VciSignals<vci_param> signal_vci_tgt_d_mnic; 90 94 91 95 // Coherence VCi signals … … 114 118 VciMultiTty<vci_param>* mtty; 115 119 VciFrameBuffer<vci_param>* fbuf; 120 VciMultiNic<vci_param>* mnic; 116 121 VciBlockDeviceTsarV4<vci_param>* bdev; 117 122 VciMultiDma<vci_param>* mdma; … … 132 137 size_t tgtid_memc, 133 138 size_t tgtid_xicu, 139 size_t tgtid_mdma, 134 140 size_t tgtid_fbuf, 135 141 size_t tgtid_mtty, 136 142 size_t tgtid_brom, 143 size_t tgtid_mnic, 137 144 size_t tgtid_bdev, 138 size_t tgtid_mdma,139 145 size_t memc_ways, 140 146 size_t memc_sets, … … 149 155 char* disk_name, // virtual disk name for BDEV 150 156 size_t block_size, // block size for BDEV 157 size_t nic_channels, // number of channels 158 char* nic_rx_name, // file name rx packets 159 char* nic_tx_name, // file name tx packets 160 uint32_t nic_timeout, // number of cycles 151 161 const Loader &loader, // loader for BROM 152 162 uint32_t frozen_cycles, // max frozen cycles -
trunk/platforms/tsarv4_generic_mmu/tsarv4_cluster_mmu/caba/source/src/tsarv4_cluster_mmu.cpp
r261 r263 48 48 size_t tgtid_memc, 49 49 size_t tgtid_xicu, 50 size_t tgtid_mdma, 50 51 size_t tgtid_fbuf, 51 52 size_t tgtid_mtty, 52 53 size_t tgtid_brom, 54 size_t tgtid_mnic, 53 55 size_t tgtid_bdev, 54 size_t tgtid_mdma,55 56 size_t memc_ways, 56 57 size_t memc_sets, … … 65 66 char* disk_name, 66 67 size_t block_size, 68 size_t nic_channels, 69 char* nic_rx_name, 70 char* nic_tx_name, 71 uint32_t nic_timeout, 67 72 const Loader &loader, 68 73 uint32_t frozen_cycles, … … 182 187 { 183 188 nb_direct_initiators = nb_procs + 2; 184 nb_direct_targets = 7;189 nb_direct_targets = 8; 185 190 } 186 191 std::ostringstream sd; … … 208 213 std::cout << " - building wrappers in cluster_" << x_id << "_" << y_id << std::endl; 209 214 210 // direct initiator wrapper211 215 std::ostringstream wid; 212 216 wid << "iniwrapperd_" << x_id << "_" << y_id; … … 216 220 4); // rsp fifo depth 217 221 218 // direct target wrapper219 222 std::ostringstream wtd; 220 223 wtd << "tgtwrapperd_" << x_id << "_" << y_id; … … 224 227 4); // rsp fifo depth 225 228 226 // coherence initiator wrapper227 229 std::ostringstream wic; 228 230 wic << "iniwrapperc_" << x_id << "_" << y_id; … … 232 234 4); // rsp fifo depth 233 235 234 // coherence target wrapper235 236 std::ostringstream wtc; 236 237 wtc << "tgtwrapperc_" << x_id << "_" << y_id; … … 252 253 std::cout << " - building rsprouter_" << x_id << "_" << y_id << std::endl; 253 254 254 // RSP router255 255 std::ostringstream srsp; 256 256 srsp << "rsprouter_" << x_id << "_" << y_id; … … 291 291 64); // burst size 292 292 293 std::cout << " - building mnic" << std::endl; 294 295 mnic = new VciMultiNic<vci_param>( 296 "mnic", 297 IntTab(cluster_id, tgtid_mnic), 298 mtd, 299 nic_channels, 300 nic_rx_name, 301 nic_tx_name, 302 nic_timeout); 303 293 304 std::cout << " - building mtty" << std::endl; 294 305 … … 391 402 xbard->p_to_target[tgtid_bdev] (signal_vci_tgt_d_bdev); 392 403 xbard->p_to_target[tgtid_fbuf] (signal_vci_tgt_d_fbuf); 404 xbard->p_to_target[tgtid_mnic] (signal_vci_tgt_d_mnic); 393 405 394 406 xbard->p_to_initiator[nb_procs+1] (signal_vci_ini_d_bdev); … … 471 483 xram->p_clk (this->p_clk); 472 484 xram->p_resetn (this->p_resetn); 473 xram->p_vci 485 xram->p_vci (signal_vci_xram); 474 486 475 487 std::cout << " - XRAM connected" << std::endl; … … 492 504 { 493 505 // BDEV 494 bdev->p_clk 495 bdev->p_resetn 496 bdev->p_irq 497 bdev->p_vci_target 498 bdev->p_vci_initiator 506 bdev->p_clk (this->p_clk); 507 bdev->p_resetn (this->p_resetn); 508 bdev->p_irq (signal_irq_bdev); 509 bdev->p_vci_target (signal_vci_tgt_d_bdev); 510 bdev->p_vci_initiator (signal_vci_ini_d_bdev); 499 511 500 512 std::cout << " - BDEV connected" << std::endl; 501 513 502 514 // FBUF 503 fbuf->p_clk 504 fbuf->p_resetn 505 fbuf->p_vci 515 fbuf->p_clk (this->p_clk); 516 fbuf->p_resetn (this->p_resetn); 517 fbuf->p_vci (signal_vci_tgt_d_fbuf); 506 518 507 519 std::cout << " - FBUF connected" << std::endl; 508 520 521 // MNIC 522 mnic->p_clk (this->p_clk); 523 mnic->p_resetn (this->p_resetn); 524 mnic->p_vci (signal_vci_tgt_d_mnic); 525 for ( size_t i=0 ; i<nic_channels ; i++ ) 526 { 527 mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]); 528 mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]); 529 } 530 531 std::cout << " - MNIC connected" << std::endl; 532 509 533 // BROM 510 brom->p_clk 511 brom->p_resetn 512 brom->p_vci 534 brom->p_clk (this->p_clk); 535 brom->p_resetn (this->p_resetn); 536 brom->p_vci (signal_vci_tgt_d_brom); 513 537 514 538 std::cout << " - BROM connected" << std::endl; 515 539 516 540 // MTTY 517 mtty->p_clk 518 mtty->p_resetn 519 mtty->p_vci 541 mtty->p_clk (this->p_clk); 542 mtty->p_resetn (this->p_resetn); 543 mtty->p_vci (signal_vci_tgt_d_mtty); 520 544 for ( size_t i=0 ; i<nb_ttys ; i++ ) 521 545 { 522 mtty->p_irq[i] 546 mtty->p_irq[i] (signal_irq_mtty[i]); 523 547 } 524 548
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