- Timestamp:
- Nov 28, 2012, 11:51:48 AM (11 years ago)
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trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h
r245 r273 26 26 * 27 27 * Maintainers: alain eric.guthmuller@polytechnique.edu 28 */ 29 /* 28 * cesar.fuguet-tortolero@lip6.fr 30 29 * 31 30 * Modifications done by Christophe Choichillon on the 7/04/2009: … … 33 32 * - Adding a new VCI target port for the CLEANUP network 34 33 * - Adding new state in the ALLOC_UPT_FSM : ALLOC_UPT_CLEANUP 35 * 34 * 36 35 * Modifications to do : 37 36 * - Adding new variables used by the CLEANUP FSM … … 58 57 #include "update_tab_v4.h" 59 58 60 #define TRANSACTION_TAB_LINES 4// Number of lines in the transaction tab61 #define UPDATE_TAB_LINES 4// Number of lines in the update tab59 #define TRANSACTION_TAB_LINES 4 // Number of lines in the transaction tab 60 #define UPDATE_TAB_LINES 4 // Number of lines in the update tab 62 61 63 62 namespace soclib { namespace caba { … … 81 80 TGT_CMD_READ, 82 81 TGT_CMD_WRITE, 83 TGT_CMD_ATOMIC ,82 TGT_CMD_ATOMIC 84 83 }; 85 84 … … 97 96 TGT_RSP_XRAM, 98 97 TGT_RSP_INIT, 99 TGT_RSP_CLEANUP ,98 TGT_RSP_CLEANUP 100 99 }; 101 100 … … 115 114 INIT_CMD_SC_UPDT_INDEX, 116 115 INIT_CMD_SC_UPDT_DATA, 117 INIT_CMD_SC_UPDT_DATA_HIGH ,116 INIT_CMD_SC_UPDT_DATA_HIGH 118 117 }; 119 118 … … 123 122 INIT_RSP_UPT_LOCK, 124 123 INIT_RSP_UPT_CLEAR, 125 INIT_RSP_END ,124 INIT_RSP_END 126 125 }; 127 126 … … 129 128 enum read_fsm_state_e{ 130 129 READ_IDLE, 130 READ_DIR_REQ, 131 131 READ_DIR_LOCK, 132 132 READ_DIR_HIT, 133 READ_HEAP_REQ, 133 134 READ_HEAP_LOCK, 134 135 READ_HEAP_WRITE, … … 138 139 READ_TRT_LOCK, 139 140 READ_TRT_SET, 140 READ_TRT_REQ ,141 READ_TRT_REQ 141 142 }; 142 143 … … 145 146 WRITE_IDLE, 146 147 WRITE_NEXT, 148 WRITE_DIR_REQ, 147 149 WRITE_DIR_LOCK, 148 150 WRITE_DIR_READ, … … 163 165 WRITE_BC_CC_SEND, 164 166 WRITE_BC_XRAM_REQ, 165 WRITE_WAIT ,167 WRITE_WAIT 166 168 }; 167 169 … … 171 173 IXR_RSP_ACK, 172 174 IXR_RSP_TRT_ERASE, 173 IXR_RSP_TRT_READ ,175 IXR_RSP_TRT_READ 174 176 }; 175 177 … … 186 188 XRAM_RSP_INVAL, 187 189 XRAM_RSP_WRITE_DIRTY, 190 XRAM_RSP_HEAP_REQ, 188 191 XRAM_RSP_HEAP_ERASE, 189 192 XRAM_RSP_HEAP_LAST, 190 193 XRAM_RSP_ERROR_ERASE, 191 XRAM_RSP_ERROR_RSP ,194 XRAM_RSP_ERROR_RSP 192 195 }; 193 196 … … 201 204 IXR_CMD_WRITE_NLINE, 202 205 IXR_CMD_SC_NLINE, 203 IXR_CMD_XRAM_DATA ,206 IXR_CMD_XRAM_DATA 204 207 }; 205 208 … … 207 210 enum sc_fsm_state_e{ 208 211 SC_IDLE, 212 SC_DIR_REQ, 209 213 SC_DIR_LOCK, 210 214 SC_DIR_HIT_READ, … … 224 228 SC_MISS_TRT_SET, 225 229 SC_MISS_XRAM_REQ, 226 SC_WAIT ,230 SC_WAIT 227 231 }; 228 232 … … 230 234 enum cleanup_fsm_state_e{ 231 235 CLEANUP_IDLE, 236 CLEANUP_DIR_REQ, 232 237 CLEANUP_DIR_LOCK, 233 238 CLEANUP_DIR_WRITE, 239 CLEANUP_HEAP_REQ, 234 240 CLEANUP_HEAP_LOCK, 235 241 CLEANUP_HEAP_SEARCH, … … 239 245 CLEANUP_UPT_WRITE, 240 246 CLEANUP_WRITE_RSP, 241 CLEANUP_RSP ,247 CLEANUP_RSP 242 248 }; 243 249 244 250 /* States of the ALLOC_DIR fsm */ 245 251 enum alloc_dir_fsm_state_e{ 252 ALLOC_DIR_RESET, 246 253 ALLOC_DIR_READ, 247 254 ALLOC_DIR_WRITE, 248 255 ALLOC_DIR_SC, 249 256 ALLOC_DIR_CLEANUP, 250 ALLOC_DIR_XRAM_RSP ,257 ALLOC_DIR_XRAM_RSP 251 258 }; 252 259 … … 257 264 ALLOC_TRT_SC, 258 265 ALLOC_TRT_XRAM_RSP, 259 ALLOC_TRT_IXR_RSP ,266 ALLOC_TRT_IXR_RSP 260 267 }; 261 268 … … 266 273 ALLOC_UPT_INIT_RSP, 267 274 ALLOC_UPT_CLEANUP, 268 ALLOC_UPT_SC ,275 ALLOC_UPT_SC 269 276 }; 270 277 271 278 /* States of the ALLOC_HEAP fsm */ 272 279 enum alloc_heap_fsm_state_e{ 280 ALLOC_HEAP_RESET, 273 281 ALLOC_HEAP_READ, 274 282 ALLOC_HEAP_WRITE, 275 283 ALLOC_HEAP_SC, 276 284 ALLOC_HEAP_CLEANUP, 277 ALLOC_HEAP_XRAM_RSP ,285 ALLOC_HEAP_XRAM_RSP 278 286 }; 279 287 … … 301 309 302 310 // instrumentation counters 303 uint32_t m_cpt_cycles; // Counter of cycles304 uint32_t m_cpt_read;// Number of READ transactions305 uint32_t m_cpt_read_miss; // Number of MISS READ306 uint32_t m_cpt_write;// Number of WRITE transactions307 uint32_t m_cpt_write_miss;// Number of MISS WRITE308 uint32_t m_cpt_write_cells; 309 uint32_t m_cpt_write_dirty; 310 uint32_t m_cpt_update;// Number of UPDATE transactions311 uint32_t m_cpt_trt_rb; 312 uint32_t m_cpt_trt_full; 313 uint32_t m_cpt_update_mult;// Number of targets for UPDATE314 uint32_t m_cpt_inval;// Number of INVAL transactions315 uint32_t m_cpt_inval_mult; // Number of targets for INVAL316 uint32_t m_cpt_inval_brdcast; // Number of BROADCAST INVAL317 uint32_t m_cpt_cleanup;// Number of CLEANUP transactions318 uint32_t m_cpt_ll;// Number of LL transactions319 uint32_t m_cpt_sc;// Number of SC transactions311 uint32_t m_cpt_cycles; // Counter of cycles 312 uint32_t m_cpt_read; // Number of READ transactions 313 uint32_t m_cpt_read_miss; // Number of MISS READ 314 uint32_t m_cpt_write; // Number of WRITE transactions 315 uint32_t m_cpt_write_miss; // Number of MISS WRITE 316 uint32_t m_cpt_write_cells; // Cumulated length for WRITE transactions 317 uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions 318 uint32_t m_cpt_update; // Number of UPDATE transactions 319 uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt 320 uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt 321 uint32_t m_cpt_update_mult; // Number of targets for UPDATE 322 uint32_t m_cpt_inval; // Number of INVAL transactions 323 uint32_t m_cpt_inval_mult; // Number of targets for INVAL 324 uint32_t m_cpt_inval_brdcast; // Number of BROADCAST INVAL 325 uint32_t m_cpt_cleanup; // Number of CLEANUP transactions 326 uint32_t m_cpt_ll; // Number of LL transactions 327 uint32_t m_cpt_sc; // Number of SC transactions 320 328 321 329 size_t m_prev_count; … … 326 334 327 335 public: 328 sc_in<bool> 329 sc_in<bool> 330 soclib::caba::VciTarget<vci_param> 331 soclib::caba::VciTarget<vci_param> 332 soclib::caba::VciInitiator<vci_param> p_vci_ini;333 soclib::caba::VciInitiator<vci_param> 336 sc_in<bool> p_clk; 337 sc_in<bool> p_resetn; 338 soclib::caba::VciTarget<vci_param> p_vci_tgt; 339 soclib::caba::VciTarget<vci_param> p_vci_tgt_cleanup; 340 soclib::caba::VciInitiator<vci_param> p_vci_ini; 341 soclib::caba::VciInitiator<vci_param> p_vci_ixr; 334 342 335 343 VciMemCacheV4( 336 sc_module_name name, // Instance Name 344 sc_module_name name, // Instance Name 337 345 const soclib::common::MappingTable &mtp, // Mapping table for primary requets 338 346 const soclib::common::MappingTable &mtc, // Mapping table for coherence requets … … 342 350 const soclib::common::IntTab &vci_tgt_index, // VCI port to PROC (target) 343 351 const soclib::common::IntTab &vci_tgt_index_cleanup,// VCI port to PROC (target) for cleanup 344 size_t nways, // Number of ways per set 352 size_t nways, // Number of ways per set 345 353 size_t nsets, // Number of sets 346 354 size_t nwords, // Number of words per line … … 348 356 size_t transaction_tab_lines=TRANSACTION_TAB_LINES, // Size of the TRT 349 357 size_t update_tab_lines=UPDATE_TAB_LINES, // Size of the UPT 350 size_t debug_start_cycle=0, 358 size_t debug_start_cycle=0, 351 359 bool debug_ok=false); 352 360 … … 366 374 367 375 // Component attributes 368 const size_t m_initiators; // Number of initiators 369 const size_t m_heap_size; // Size of the heap 370 const size_t m_ways; // Number of ways in a set 371 const size_t m_sets; // Number of cache sets 372 const size_t m_words; // Number of words in a line 373 const size_t m_srcid_ixr; // Srcid for requests to XRAM 374 const size_t m_srcid_ini; // Srcid for requests to processors 375 std::list<soclib::common::Segment> m_seglist; // memory cached into the cache 376 std::list<soclib::common::Segment> m_cseglist; // coherence segment for the cache 377 vci_addr_t *m_coherence_table; // address(srcid) 378 uint32_t m_transaction_tab_lines; 379 TransactionTab m_transaction_tab; // xram transaction table 380 uint32_t m_update_tab_lines; 381 UpdateTab m_update_tab; // pending update & invalidate 382 CacheDirectory m_cache_directory; // data cache directory 383 HeapDirectory m_heap; // heap for copies 384 385 data_t ***m_cache_data; // data array[set][way][word] 376 std::list<soclib::common::Segment> m_seglist; // memory cached into the cache 377 std::list<soclib::common::Segment> m_cseglist; // coherence segment for the cache 378 379 const size_t m_initiators; // Number of initiators 380 const size_t m_heap_size; // Size of the heap 381 const size_t m_ways; // Number of ways in a set 382 const size_t m_sets; // Number of cache sets 383 const size_t m_words; // Number of words in a line 384 const size_t m_srcid_ixr; // Srcid for requests to XRAM 385 const size_t m_srcid_ini; // Srcid for requests to processors 386 387 uint32_t m_transaction_tab_lines; 388 TransactionTab m_transaction_tab; // xram transaction table 389 uint32_t m_update_tab_lines; 390 UpdateTab m_update_tab; // pending update & invalidate 391 CacheDirectory m_cache_directory; // data cache directory 392 HeapDirectory m_heap; // heap for copies 393 394 data_t *** m_cache_data; // data array[set][way][word] 386 395 387 396 // adress masks 388 const soclib::common::AddressMaskingTable<vci_addr_t> 389 const soclib::common::AddressMaskingTable<vci_addr_t> 390 const soclib::common::AddressMaskingTable<vci_addr_t> 391 const soclib::common::AddressMaskingTable<vci_addr_t> m_nline;397 const soclib::common::AddressMaskingTable<vci_addr_t> m_x; 398 const soclib::common::AddressMaskingTable<vci_addr_t> m_y; 399 const soclib::common::AddressMaskingTable<vci_addr_t> m_z; 400 const soclib::common::AddressMaskingTable<vci_addr_t> m_nline; 392 401 393 402 // broadcast address 394 vci_addr_t 403 vci_addr_t m_broadcast_address; 395 404 396 405 ////////////////////////////////////////////////// 397 406 // Others registers 398 407 ////////////////////////////////////////////////// 399 sc_signal<size_t> 400 sc_signal<size_t> 408 sc_signal<size_t> r_copies_limit; // Limit of the number of copies for one line 409 sc_signal<size_t> xxx_count; 401 410 402 411 ////////////////////////////////////////////////// … … 411 420 GenericFifo<size_t> m_cmd_read_pktid_fifo; 412 421 413 // Fifo between TGT_CMD fsm and WRITE fsm 422 // Fifo between TGT_CMD fsm and WRITE fsm 414 423 GenericFifo<uint64_t> m_cmd_write_addr_fifo; 415 424 GenericFifo<bool> m_cmd_write_eop_fifo; … … 418 427 GenericFifo<size_t> m_cmd_write_pktid_fifo; 419 428 GenericFifo<data_t> m_cmd_write_data_fifo; 420 GenericFifo<be_t> 429 GenericFifo<be_t> m_cmd_write_be_fifo; 421 430 422 431 // Fifo between TGT_CMD fsm and SC fsm … … 434 443 soclib::common::Segment **m_seg; 435 444 soclib::common::Segment **m_cseg; 436 437 445 /////////////////////////////////////////////////////// 438 446 // Registers controlled by the READ fsm 439 447 /////////////////////////////////////////////////////// 440 448 441 sc_signal<int> r_read_fsm; // FSM state442 sc_signal<size_t> 443 sc_signal<size_t> 444 sc_signal<bool> 445 sc_signal<tag_t> r_read_tag;// cache line tag (in directory)446 sc_signal<bool> r_read_is_cnt;// is_cnt bit (in directory)447 sc_signal<bool> r_read_lock;// lock bit (in directory)448 sc_signal<bool> r_read_dirty;// dirty bit (in directory)449 sc_signal<size_t> 450 sc_signal<size_t> 451 sc_signal<data_t> *r_read_data; // data (one cache line)452 sc_signal<size_t> 453 sc_signal<size_t> 454 sc_signal<size_t> 455 sc_signal<bool> 456 457 // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM) 458 sc_signal<bool> r_read_to_ixr_cmd_req;// valid request459 sc_signal<addr_t> r_read_to_ixr_cmd_nline;// cache line index460 sc_signal<size_t> r_read_to_ixr_cmd_trdid;// index in Transaction Table449 sc_signal<int> r_read_fsm; // FSM state 450 sc_signal<size_t> r_read_copy; // Srcid of the first copy 451 sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy 452 sc_signal<bool> r_read_copy_inst; // Type of the first copy 453 sc_signal<tag_t> r_read_tag; // cache line tag (in directory) 454 sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory) 455 sc_signal<bool> r_read_lock; // lock bit (in directory) 456 sc_signal<bool> r_read_dirty; // dirty bit (in directory) 457 sc_signal<size_t> r_read_count; // number of copies 458 sc_signal<size_t> r_read_ptr; // pointer to the heap 459 sc_signal<data_t> * r_read_data; // data (one cache line) 460 sc_signal<size_t> r_read_way; // associative way (in cache) 461 sc_signal<size_t> r_read_trt_index; // Transaction Table index 462 sc_signal<size_t> r_read_next_ptr; // Next entry to point to 463 sc_signal<bool> r_read_last_free; // Last free entry 464 465 // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM) 466 sc_signal<bool> r_read_to_ixr_cmd_req; // valid request 467 sc_signal<addr_t> r_read_to_ixr_cmd_nline; // cache line index 468 sc_signal<size_t> r_read_to_ixr_cmd_trdid; // index in Transaction Table 461 469 462 470 // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache) 463 sc_signal<bool> r_read_to_tgt_rsp_req;// valid request464 sc_signal<size_t> r_read_to_tgt_rsp_srcid;// Transaction srcid465 sc_signal<size_t> r_read_to_tgt_rsp_trdid;// Transaction trdid466 sc_signal<size_t> r_read_to_tgt_rsp_pktid;// Transaction pktid467 sc_signal<data_t> *r_read_to_tgt_rsp_data;// data (one cache line)468 sc_signal<size_t> r_read_to_tgt_rsp_word;// first word of the response469 sc_signal<size_t> r_read_to_tgt_rsp_length;// length of the response471 sc_signal<bool> r_read_to_tgt_rsp_req; // valid request 472 sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid 473 sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid 474 sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid 475 sc_signal<data_t> * r_read_to_tgt_rsp_data; // data (one cache line) 476 sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response 477 sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response 470 478 471 479 /////////////////////////////////////////////////////////////// … … 473 481 /////////////////////////////////////////////////////////////// 474 482 475 sc_signal<int> r_write_fsm;// FSM state476 sc_signal<addr_t> r_write_address;// first word address477 sc_signal<size_t> r_write_word_index;// first word index in line478 sc_signal<size_t> r_write_word_count;// number of words in line479 sc_signal<size_t> r_write_srcid;// transaction srcid480 sc_signal<size_t> r_write_trdid;// transaction trdid481 sc_signal<size_t> r_write_pktid;// transaction pktid482 sc_signal<data_t> *r_write_data; // data (one cache line)483 sc_signal<be_t> *r_write_be;// one byte enable per word484 sc_signal<bool> r_write_byte;// (BE != 0X0) and (BE != 0xF)485 sc_signal<bool> r_write_is_cnt;// is_cnt bit (in directory)486 sc_signal<bool> r_write_lock;// lock bit (in directory)487 sc_signal<tag_t> r_write_tag;// cache line tag (in directory)488 sc_signal<size_t> r_write_copy;// first owner of the line489 sc_signal<size_t> r_write_copy_cache;// first owner of the line490 sc_signal<bool> r_write_copy_inst;// is this owner a ICache ?491 sc_signal<size_t> r_write_count;// number of copies492 sc_signal<size_t> r_write_ptr;// pointer to the heap493 sc_signal<size_t> r_write_next_ptr;// next pointer to the heap494 sc_signal<bool> r_write_to_dec;// need to decrement update counter495 sc_signal<size_t> r_write_way;// way of the line496 sc_signal<size_t> r_write_trt_index;// index in Transaction Table497 sc_signal<size_t> r_write_upt_index;// index in Update Table483 sc_signal<int> r_write_fsm; // FSM state 484 sc_signal<addr_t> r_write_address; // first word address 485 sc_signal<size_t> r_write_word_index; // first word index in line 486 sc_signal<size_t> r_write_word_count; // number of words in line 487 sc_signal<size_t> r_write_srcid; // transaction srcid 488 sc_signal<size_t> r_write_trdid; // transaction trdid 489 sc_signal<size_t> r_write_pktid; // transaction pktid 490 sc_signal<data_t> * r_write_data; // data (one cache line) 491 sc_signal<be_t> * r_write_be; // one byte enable per word 492 sc_signal<bool> r_write_byte; // (BE != 0X0) and (BE != 0xF) 493 sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory) 494 sc_signal<bool> r_write_lock; // lock bit (in directory) 495 sc_signal<tag_t> r_write_tag; // cache line tag (in directory) 496 sc_signal<size_t> r_write_copy; // first owner of the line 497 sc_signal<size_t> r_write_copy_cache; // first owner of the line 498 sc_signal<bool> r_write_copy_inst; // is this owner a ICache ? 499 sc_signal<size_t> r_write_count; // number of copies 500 sc_signal<size_t> r_write_ptr; // pointer to the heap 501 sc_signal<size_t> r_write_next_ptr; // next pointer to the heap 502 sc_signal<bool> r_write_to_dec; // need to decrement update counter 503 sc_signal<size_t> r_write_way; // way of the line 504 sc_signal<size_t> r_write_trt_index; // index in Transaction Table 505 sc_signal<size_t> r_write_upt_index; // index in Update Table 498 506 499 507 // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1) 500 sc_signal<bool> r_write_to_tgt_rsp_req;// valid request501 sc_signal<size_t> r_write_to_tgt_rsp_srcid;// transaction srcid502 sc_signal<size_t> r_write_to_tgt_rsp_trdid;// transaction trdid503 sc_signal<size_t> r_write_to_tgt_rsp_pktid;// transaction pktid504 505 // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM) 506 sc_signal<bool> r_write_to_ixr_cmd_req;// valid request507 sc_signal<bool> r_write_to_ixr_cmd_write;// write request508 sc_signal<addr_t> r_write_to_ixr_cmd_nline;// cache line index509 sc_signal<data_t> *r_write_to_ixr_cmd_data;// cache line data510 sc_signal<size_t> r_write_to_ixr_cmd_trdid;// index in Transaction Table508 sc_signal<bool> r_write_to_tgt_rsp_req; // valid request 509 sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid 510 sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid 511 sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid 512 513 // Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM) 514 sc_signal<bool> r_write_to_ixr_cmd_req; // valid request 515 sc_signal<bool> r_write_to_ixr_cmd_write; // write request 516 sc_signal<addr_t> r_write_to_ixr_cmd_nline; // cache line index 517 sc_signal<data_t> * r_write_to_ixr_cmd_data; // cache line data 518 sc_signal<size_t> r_write_to_ixr_cmd_trdid; // index in Transaction Table 511 519 512 520 // Buffer between WRITE fsm and INIT_CMD fsm (Update/Invalidate L1 caches) 513 sc_signal<bool> r_write_to_init_cmd_multi_req;// valid multicast request514 sc_signal<bool> r_write_to_init_cmd_brdcast_req;// valid brdcast request515 sc_signal<addr_t> r_write_to_init_cmd_nline;// cache line index516 sc_signal<size_t> r_write_to_init_cmd_trdid;// index in Update Table517 sc_signal<data_t> *r_write_to_init_cmd_data;// data (one cache line)518 sc_signal<be_t> *r_write_to_init_cmd_be;// word enable519 sc_signal<size_t> r_write_to_init_cmd_count;// number of words in line520 sc_signal<size_t> r_write_to_init_cmd_index;// index of first word in line521 GenericFifo<bool> m_write_to_init_cmd_inst_fifo;// fifo for the L1 type522 GenericFifo<size_t> m_write_to_init_cmd_srcid_fifo;// fifo for srcids523 GenericFifo<size_t> m_write_to_init_cmd_cache_id_fifo;// fifo for srcids521 sc_signal<bool> r_write_to_init_cmd_multi_req; // valid multicast request 522 sc_signal<bool> r_write_to_init_cmd_brdcast_req; // valid brdcast request 523 sc_signal<addr_t> r_write_to_init_cmd_nline; // cache line index 524 sc_signal<size_t> r_write_to_init_cmd_trdid; // index in Update Table 525 sc_signal<data_t> * r_write_to_init_cmd_data; // data (one cache line) 526 sc_signal<be_t> * r_write_to_init_cmd_be; // word enable 527 sc_signal<size_t> r_write_to_init_cmd_count; // number of words in line 528 sc_signal<size_t> r_write_to_init_cmd_index; // index of first word in line 529 GenericFifo<bool> m_write_to_init_cmd_inst_fifo; // fifo for the L1 type 530 GenericFifo<size_t> m_write_to_init_cmd_srcid_fifo; // fifo for srcids 531 GenericFifo<size_t> m_write_to_init_cmd_cache_id_fifo; // fifo for srcids 524 532 525 533 // Buffer between WRITE fsm and INIT_RSP fsm (Decrement UPT entry) 526 sc_signal<bool> r_write_to_init_rsp_req;// valid request527 sc_signal<size_t> r_write_to_init_rsp_upt_index;// index in update table534 sc_signal<bool> r_write_to_init_rsp_req; // valid request 535 sc_signal<size_t> r_write_to_init_rsp_upt_index; // index in update table 528 536 529 537 ///////////////////////////////////////////////////////// … … 531 539 ////////////////////////////////////////////////////////// 532 540 533 sc_signal<int> r_init_rsp_fsm;// FSM state534 sc_signal<size_t> r_init_rsp_upt_index;// index in the Update Table535 sc_signal<size_t> r_init_rsp_srcid; // pending write srcid536 sc_signal<size_t> r_init_rsp_trdid; // pending write trdid537 sc_signal<size_t> r_init_rsp_pktid; // pending write pktid538 sc_signal<addr_t> r_init_rsp_nline; // pending write nline541 sc_signal<int> r_init_rsp_fsm; // FSM state 542 sc_signal<size_t> r_init_rsp_upt_index; // index in the Update Table 543 sc_signal<size_t> r_init_rsp_srcid; // pending write srcid 544 sc_signal<size_t> r_init_rsp_trdid; // pending write trdid 545 sc_signal<size_t> r_init_rsp_pktid; // pending write pktid 546 sc_signal<addr_t> r_init_rsp_nline; // pending write nline 539 547 540 548 // Buffer between INIT_RSP fsm and TGT_RSP fsm (complete write/update transaction) 541 sc_signal<bool> r_init_rsp_to_tgt_rsp_req;// valid request542 sc_signal<size_t> r_init_rsp_to_tgt_rsp_srcid;// Transaction srcid543 sc_signal<size_t> r_init_rsp_to_tgt_rsp_trdid;// Transaction trdid544 sc_signal<size_t> r_init_rsp_to_tgt_rsp_pktid;// Transaction pktid549 sc_signal<bool> r_init_rsp_to_tgt_rsp_req; // valid request 550 sc_signal<size_t> r_init_rsp_to_tgt_rsp_srcid; // Transaction srcid 551 sc_signal<size_t> r_init_rsp_to_tgt_rsp_trdid; // Transaction trdid 552 sc_signal<size_t> r_init_rsp_to_tgt_rsp_pktid; // Transaction pktid 545 553 546 554 /////////////////////////////////////////////////////// … … 548 556 /////////////////////////////////////////////////////// 549 557 550 sc_signal<int> r_cleanup_fsm;// FSM state551 sc_signal<size_t> r_cleanup_srcid;// transaction srcid552 sc_signal<size_t> r_cleanup_trdid;// transaction trdid553 sc_signal<size_t> r_cleanup_pktid;// transaction pktid554 sc_signal<addr_t> r_cleanup_nline;// cache line index555 556 sc_signal<copy_t> r_cleanup_copy;// first copy557 sc_signal<copy_t> r_cleanup_copy_cache;// first copy558 sc_signal<size_t> r_cleanup_copy_inst;// type of the first copy559 sc_signal<copy_t> r_cleanup_count; // number of copies560 sc_signal<size_t> r_cleanup_ptr;// pointer to the heap561 sc_signal<size_t> r_cleanup_prev_ptr;// previous pointer to the heap562 sc_signal<size_t> r_cleanup_prev_srcid;// srcid of previous heap entry563 sc_signal<size_t> r_cleanup_prev_cache_id;// srcid of previous heap entry564 sc_signal<bool> r_cleanup_prev_inst;// inst bit of previous heap entry565 sc_signal<size_t> r_cleanup_next_ptr;// next pointer to the heap566 sc_signal<tag_t> r_cleanup_tag;// cache line tag (in directory)567 sc_signal<bool> r_cleanup_is_cnt;// inst bit (in directory)568 sc_signal<bool> r_cleanup_lock;// lock bit (in directory)569 sc_signal<bool> r_cleanup_dirty;// dirty bit (in directory)570 sc_signal<size_t> r_cleanup_way;// associative way (in cache)571 572 sc_signal<size_t> r_cleanup_write_srcid;// srcid of write response573 sc_signal<size_t> r_cleanup_write_trdid;// trdid of write rsp574 sc_signal<size_t> r_cleanup_write_pktid;// pktid of write rsp575 sc_signal<bool> r_cleanup_need_rsp;// needs a write rsp576 577 sc_signal<size_t> r_cleanup_index;// index of the INVAL line (in the UPT)558 sc_signal<int> r_cleanup_fsm; // FSM state 559 sc_signal<size_t> r_cleanup_srcid; // transaction srcid 560 sc_signal<size_t> r_cleanup_trdid; // transaction trdid 561 sc_signal<size_t> r_cleanup_pktid; // transaction pktid 562 sc_signal<addr_t> r_cleanup_nline; // cache line index 563 564 sc_signal<copy_t> r_cleanup_copy; // first copy 565 sc_signal<copy_t> r_cleanup_copy_cache; // first copy 566 sc_signal<size_t> r_cleanup_copy_inst; // type of the first copy 567 sc_signal<copy_t> r_cleanup_count; // number of copies 568 sc_signal<size_t> r_cleanup_ptr; // pointer to the heap 569 sc_signal<size_t> r_cleanup_prev_ptr; // previous pointer to the heap 570 sc_signal<size_t> r_cleanup_prev_srcid; // srcid of previous heap entry 571 sc_signal<size_t> r_cleanup_prev_cache_id; // srcid of previous heap entry 572 sc_signal<bool> r_cleanup_prev_inst; // inst bit of previous heap entry 573 sc_signal<size_t> r_cleanup_next_ptr; // next pointer to the heap 574 sc_signal<tag_t> r_cleanup_tag; // cache line tag (in directory) 575 sc_signal<bool> r_cleanup_is_cnt; // inst bit (in directory) 576 sc_signal<bool> r_cleanup_lock; // lock bit (in directory) 577 sc_signal<bool> r_cleanup_dirty; // dirty bit (in directory) 578 sc_signal<size_t> r_cleanup_way; // associative way (in cache) 579 580 sc_signal<size_t> r_cleanup_write_srcid; // srcid of write response 581 sc_signal<size_t> r_cleanup_write_trdid; // trdid of write rsp 582 sc_signal<size_t> r_cleanup_write_pktid; // pktid of write rsp 583 sc_signal<bool> r_cleanup_need_rsp; // needs a write rsp 584 585 sc_signal<size_t> r_cleanup_index; // index of the INVAL line (in the UPT) 578 586 579 587 // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1) 580 sc_signal<bool> r_cleanup_to_tgt_rsp_req;// valid request581 sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid;// transaction srcid582 sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid;// transaction trdid583 sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid;// transaction pktid588 sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request 589 sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid 590 sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid 591 sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid 584 592 585 593 /////////////////////////////////////////////////////// … … 587 595 /////////////////////////////////////////////////////// 588 596 589 sc_signal<int> r_sc_fsm;// FSM state590 sc_signal<data_t> r_sc_wdata;// write data word591 sc_signal<data_t> *r_sc_rdata;// read data word592 sc_signal<uint32_t> r_sc_lfsr;// lfsr for random introducing593 sc_signal<size_t> r_sc_cpt;// size of command594 sc_signal<copy_t> r_sc_copy;// Srcid of the first copy595 sc_signal<copy_t> r_sc_copy_cache;// Srcid of the first copy596 sc_signal<bool> r_sc_copy_inst;// Type of the first copy597 sc_signal<size_t> r_sc_count;// number of copies598 sc_signal<size_t> r_sc_ptr;// pointer to the heap599 sc_signal<size_t> r_sc_next_ptr;// next pointer to the heap600 sc_signal<bool> r_sc_is_cnt;// is_cnt bit (in directory)601 sc_signal<bool> r_sc_dirty;// dirty bit (in directory)602 sc_signal<size_t> r_sc_way;// way in directory603 sc_signal<size_t> r_sc_set;// set in directory604 sc_signal<data_t> r_sc_tag;// cache line tag (in directory)605 sc_signal<size_t> r_sc_trt_index;// Transaction Table index606 sc_signal<size_t> r_sc_upt_index;// Update Table index607 608 // Buffer between SC fsm and INIT_CMD fsm (XRAM read) 609 sc_signal<bool> r_sc_to_ixr_cmd_req;// valid request610 sc_signal<addr_t> r_sc_to_ixr_cmd_nline;// cache line index611 sc_signal<size_t> r_sc_to_ixr_cmd_trdid;// index in Transaction Table612 sc_signal<bool> r_sc_to_ixr_cmd_write;// write request613 sc_signal<data_t> *r_sc_to_ixr_cmd_data;// cache line data597 sc_signal<int> r_sc_fsm; // FSM state 598 sc_signal<data_t> r_sc_wdata; // write data word 599 sc_signal<data_t> * r_sc_rdata; // read data word 600 sc_signal<uint32_t> r_sc_lfsr; // lfsr for random introducing 601 sc_signal<size_t> r_sc_cpt; // size of command 602 sc_signal<copy_t> r_sc_copy; // Srcid of the first copy 603 sc_signal<copy_t> r_sc_copy_cache; // Srcid of the first copy 604 sc_signal<bool> r_sc_copy_inst; // Type of the first copy 605 sc_signal<size_t> r_sc_count; // number of copies 606 sc_signal<size_t> r_sc_ptr; // pointer to the heap 607 sc_signal<size_t> r_sc_next_ptr; // next pointer to the heap 608 sc_signal<bool> r_sc_is_cnt; // is_cnt bit (in directory) 609 sc_signal<bool> r_sc_dirty; // dirty bit (in directory) 610 sc_signal<size_t> r_sc_way; // way in directory 611 sc_signal<size_t> r_sc_set; // set in directory 612 sc_signal<data_t> r_sc_tag; // cache line tag (in directory) 613 sc_signal<size_t> r_sc_trt_index; // Transaction Table index 614 sc_signal<size_t> r_sc_upt_index; // Update Table index 615 616 // Buffer between SC fsm and INIT_CMD fsm (XRAM read) 617 sc_signal<bool> r_sc_to_ixr_cmd_req; // valid request 618 sc_signal<addr_t> r_sc_to_ixr_cmd_nline; // cache line index 619 sc_signal<size_t> r_sc_to_ixr_cmd_trdid; // index in Transaction Table 620 sc_signal<bool> r_sc_to_ixr_cmd_write; // write request 621 sc_signal<data_t> * r_sc_to_ixr_cmd_data; // cache line data 614 622 615 623 616 624 // Buffer between SC fsm and TGT_RSP fsm 617 sc_signal<bool> r_sc_to_tgt_rsp_req;// valid request618 sc_signal<data_t> r_sc_to_tgt_rsp_data;// read data word619 sc_signal<size_t> r_sc_to_tgt_rsp_srcid;// Transaction srcid620 sc_signal<size_t> r_sc_to_tgt_rsp_trdid;// Transaction trdid621 sc_signal<size_t> r_sc_to_tgt_rsp_pktid;// Transaction pktid625 sc_signal<bool> r_sc_to_tgt_rsp_req; // valid request 626 sc_signal<data_t> r_sc_to_tgt_rsp_data; // read data word 627 sc_signal<size_t> r_sc_to_tgt_rsp_srcid; // Transaction srcid 628 sc_signal<size_t> r_sc_to_tgt_rsp_trdid; // Transaction trdid 629 sc_signal<size_t> r_sc_to_tgt_rsp_pktid; // Transaction pktid 622 630 623 631 // Buffer between SC fsm and INIT_CMD fsm (Update/Invalidate L1 caches) 624 sc_signal<bool> r_sc_to_init_cmd_multi_req;// valid request625 sc_signal<bool> r_sc_to_init_cmd_brdcast_req;// brdcast request626 sc_signal<addr_t> r_sc_to_init_cmd_nline;// cache line index627 sc_signal<size_t> r_sc_to_init_cmd_trdid;// index in Update Table628 sc_signal<data_t> r_sc_to_init_cmd_wdata;// data (one word)629 sc_signal<bool> r_sc_to_init_cmd_is_long;// it is a 64 bits SC630 sc_signal<data_t> r_sc_to_init_cmd_wdata_high;// data high (one word)631 sc_signal<size_t> r_sc_to_init_cmd_index;// index of the word in line632 GenericFifo<bool> m_sc_to_init_cmd_inst_fifo;// fifo for the L1 type633 GenericFifo<size_t> m_sc_to_init_cmd_srcid_fifo;// fifo for srcids634 GenericFifo<size_t> m_sc_to_init_cmd_cache_id_fifo;// fifo for srcids632 sc_signal<bool> r_sc_to_init_cmd_multi_req; // valid request 633 sc_signal<bool> r_sc_to_init_cmd_brdcast_req; // brdcast request 634 sc_signal<addr_t> r_sc_to_init_cmd_nline; // cache line index 635 sc_signal<size_t> r_sc_to_init_cmd_trdid; // index in Update Table 636 sc_signal<data_t> r_sc_to_init_cmd_wdata; // data (one word) 637 sc_signal<bool> r_sc_to_init_cmd_is_long; // it is a 64 bits SC 638 sc_signal<data_t> r_sc_to_init_cmd_wdata_high; // data high (one word) 639 sc_signal<size_t> r_sc_to_init_cmd_index; // index of the word in line 640 GenericFifo<bool> m_sc_to_init_cmd_inst_fifo; // fifo for the L1 type 641 GenericFifo<size_t> m_sc_to_init_cmd_srcid_fifo; // fifo for srcids 642 GenericFifo<size_t> m_sc_to_init_cmd_cache_id_fifo; // fifo for srcids 635 643 636 644 // Buffer between SC fsm and INIT_RSP fsm (Decrement UPT entry) 637 sc_signal<bool> r_sc_to_init_rsp_req;// valid request638 sc_signal<size_t> r_sc_to_init_rsp_upt_index;// index in update table645 sc_signal<bool> r_sc_to_init_rsp_req; // valid request 646 sc_signal<size_t> r_sc_to_init_rsp_upt_index; // index in update table 639 647 640 648 //////////////////////////////////////////////////// … … 642 650 //////////////////////////////////////////////////// 643 651 644 sc_signal<int> 645 sc_signal<size_t> r_ixr_rsp_trt_index;// TRT entry index646 sc_signal<size_t> r_ixr_rsp_cpt;// word counter652 sc_signal<int> r_ixr_rsp_fsm; // FSM state 653 sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index 654 sc_signal<size_t> r_ixr_rsp_cpt; // word counter 647 655 648 656 // Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM) 649 sc_signal<bool> *r_ixr_rsp_to_xram_rsp_rok;// A xram response is ready657 sc_signal<bool> * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready 650 658 651 659 //////////////////////////////////////////////////// … … 653 661 //////////////////////////////////////////////////// 654 662 655 sc_signal<int> r_xram_rsp_fsm;// FSM state656 sc_signal<size_t> r_xram_rsp_trt_index;// TRT entry index657 TransactionTabEntry r_xram_rsp_trt_buf;// TRT entry local buffer658 sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate659 sc_signal<bool> r_xram_rsp_victim_is_cnt;// victim line inst bit660 sc_signal<bool> r_xram_rsp_victim_dirty;// victim line dirty bit661 sc_signal<size_t> r_xram_rsp_victim_way;// victim line way662 sc_signal<size_t> r_xram_rsp_victim_set;// victim line set663 sc_signal<addr_t> r_xram_rsp_victim_nline;// victim line index664 sc_signal<copy_t> r_xram_rsp_victim_copy;// victim line first copy665 sc_signal<copy_t> r_xram_rsp_victim_copy_cache;// victim line first copy666 sc_signal<bool> r_xram_rsp_victim_copy_inst;// victim line type of first copy667 sc_signal<size_t> r_xram_rsp_victim_count;// victim line number of copies668 sc_signal<size_t> r_xram_rsp_victim_ptr;// victim line pointer to the heap669 sc_signal<data_t> *r_xram_rsp_victim_data;// victim line data670 sc_signal<size_t> r_xram_rsp_upt_index;// UPT entry index671 sc_signal<size_t> r_xram_rsp_next_ptr;// Next pointer to the heap663 sc_signal<int> r_xram_rsp_fsm; // FSM state 664 sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index 665 TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer 666 sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate 667 sc_signal<bool> r_xram_rsp_victim_is_cnt; // victim line inst bit 668 sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit 669 sc_signal<size_t> r_xram_rsp_victim_way; // victim line way 670 sc_signal<size_t> r_xram_rsp_victim_set; // victim line set 671 sc_signal<addr_t> r_xram_rsp_victim_nline; // victim line index 672 sc_signal<copy_t> r_xram_rsp_victim_copy; // victim line first copy 673 sc_signal<copy_t> r_xram_rsp_victim_copy_cache; // victim line first copy 674 sc_signal<bool> r_xram_rsp_victim_copy_inst; // victim line type of first copy 675 sc_signal<size_t> r_xram_rsp_victim_count; // victim line number of copies 676 sc_signal<size_t> r_xram_rsp_victim_ptr; // victim line pointer to the heap 677 sc_signal<data_t> * r_xram_rsp_victim_data; // victim line data 678 sc_signal<size_t> r_xram_rsp_upt_index; // UPT entry index 679 sc_signal<size_t> r_xram_rsp_next_ptr; // Next pointer to the heap 672 680 673 681 // Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache) 674 sc_signal<bool> r_xram_rsp_to_tgt_rsp_req;// Valid request675 sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid;// Transaction srcid676 sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid;// Transaction trdid677 sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid;// Transaction pktid678 sc_signal<data_t> *r_xram_rsp_to_tgt_rsp_data;// data (one cache line)679 sc_signal<size_t> r_xram_rsp_to_tgt_rsp_word;// first word index680 sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length;// length of the response681 sc_signal<bool> r_xram_rsp_to_tgt_rsp_rerror;// send error to requester682 683 // Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches) 684 sc_signal<bool> r_xram_rsp_to_init_cmd_multi_req;// Valid request685 sc_signal<bool> r_xram_rsp_to_init_cmd_brdcast_req;// Broadcast request686 sc_signal<addr_t> r_xram_rsp_to_init_cmd_nline;// cache line index;687 sc_signal<size_t> r_xram_rsp_to_init_cmd_trdid;// index of UPT entry688 GenericFifo<bool> m_xram_rsp_to_init_cmd_inst_fifo;// fifo for the L1 type689 GenericFifo<size_t> m_xram_rsp_to_init_cmd_srcid_fifo;// fifo for srcids690 GenericFifo<size_t> m_xram_rsp_to_init_cmd_cache_id_fifo;// fifo for srcids682 sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request 683 sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid 684 sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid 685 sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid 686 sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data; // data (one cache line) 687 sc_signal<size_t> r_xram_rsp_to_tgt_rsp_word; // first word index 688 sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length; // length of the response 689 sc_signal<bool> r_xram_rsp_to_tgt_rsp_rerror; // send error to requester 690 691 // Buffer between XRAM_RSP fsm and INIT_CMD fsm (Inval L1 Caches) 692 sc_signal<bool> r_xram_rsp_to_init_cmd_multi_req; // Valid request 693 sc_signal<bool> r_xram_rsp_to_init_cmd_brdcast_req; // Broadcast request 694 sc_signal<addr_t> r_xram_rsp_to_init_cmd_nline; // cache line index; 695 sc_signal<size_t> r_xram_rsp_to_init_cmd_trdid; // index of UPT entry 696 GenericFifo<bool> m_xram_rsp_to_init_cmd_inst_fifo; // fifo for the L1 type 697 GenericFifo<size_t> m_xram_rsp_to_init_cmd_srcid_fifo; // fifo for srcids 698 GenericFifo<size_t> m_xram_rsp_to_init_cmd_cache_id_fifo; // fifo for srcids 691 699 692 700 // Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write) 693 sc_signal<bool> r_xram_rsp_to_ixr_cmd_req;// Valid request694 sc_signal<addr_t> r_xram_rsp_to_ixr_cmd_nline;// cache line index695 sc_signal<data_t> *r_xram_rsp_to_ixr_cmd_data;// cache line data696 sc_signal<size_t> r_xram_rsp_to_ixr_cmd_trdid;// index in transaction table701 sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request 702 sc_signal<addr_t> r_xram_rsp_to_ixr_cmd_nline; // cache line index 703 sc_signal<data_t> * r_xram_rsp_to_ixr_cmd_data; // cache line data 704 sc_signal<size_t> r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table 697 705 698 706 //////////////////////////////////////////////////// … … 700 708 //////////////////////////////////////////////////// 701 709 702 sc_signal<int> 703 sc_signal<size_t> 710 sc_signal<int> r_ixr_cmd_fsm; 711 sc_signal<size_t> r_ixr_cmd_cpt; 704 712 705 713 //////////////////////////////////////////////////// … … 707 715 //////////////////////////////////////////////////// 708 716 709 sc_signal<int> 710 sc_signal<size_t> 717 sc_signal<int> r_tgt_rsp_fsm; 718 sc_signal<size_t> r_tgt_rsp_cpt; 711 719 712 720 //////////////////////////////////////////////////// … … 714 722 //////////////////////////////////////////////////// 715 723 716 sc_signal<int> 724 sc_signal<int> r_init_cmd_fsm; 717 725 sc_signal<size_t> r_init_cmd_cpt; 718 726 sc_signal<bool> r_init_cmd_inst; … … 722 730 //////////////////////////////////////////////////// 723 731 724 sc_signal<int> r_alloc_dir_fsm; 732 sc_signal<int> r_alloc_dir_fsm; 733 sc_signal<unsigned> r_alloc_dir_reset_cpt; 725 734 726 735 //////////////////////////////////////////////////// … … 728 737 //////////////////////////////////////////////////// 729 738 730 sc_signal<int> 739 sc_signal<int> r_alloc_trt_fsm; 731 740 732 741 //////////////////////////////////////////////////// … … 734 743 //////////////////////////////////////////////////// 735 744 736 sc_signal<int> 745 sc_signal<int> r_alloc_upt_fsm; 737 746 738 747 //////////////////////////////////////////////////// … … 740 749 //////////////////////////////////////////////////// 741 750 742 sc_signal<int> 743 751 sc_signal<int> r_alloc_heap_fsm; 752 sc_signal<unsigned> r_alloc_heap_reset_cpt; 744 753 }; // end class VciMemCacheV4 745 754 … … 755 764 // End: 756 765 757 // vim: filetype=cpp:expandtab:shiftwidth= 4:tabstop=4:softtabstop=4758 766 // vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2 767
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