Index: trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h
===================================================================
--- trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h	(revision 283)
+++ trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h	(revision 284)
@@ -27,4 +27,5 @@
  * Maintainers: alain eric.guthmuller@polytechnique.edu
  *              cesar.fuguet-tortolero@lip6.fr
+ *              alexandre.joannou@lip6.fr
  *
  * Modifications done by Christophe Choichillon on the 7/04/2009:
@@ -80,5 +81,5 @@
         TGT_CMD_READ,
         TGT_CMD_WRITE,
-        TGT_CMD_ATOMIC
+        TGT_CMD_CAS
       };
 
@@ -87,5 +88,5 @@
         TGT_RSP_READ_IDLE,
         TGT_RSP_WRITE_IDLE,
-        TGT_RSP_SC_IDLE,
+        TGT_RSP_CAS_IDLE,
         TGT_RSP_XRAM_IDLE,
         TGT_RSP_INIT_IDLE,
@@ -93,5 +94,5 @@
         TGT_RSP_READ,
         TGT_RSP_WRITE,
-        TGT_RSP_SC,
+        TGT_RSP_CAS,
         TGT_RSP_XRAM,
         TGT_RSP_INIT,
@@ -109,10 +110,10 @@
         INIT_CMD_UPDT_INDEX,
         INIT_CMD_UPDT_DATA,
-        INIT_CMD_SC_UPDT_IDLE,
-        INIT_CMD_SC_BRDCAST,
-        INIT_CMD_SC_UPDT_NLINE,
-        INIT_CMD_SC_UPDT_INDEX,
-        INIT_CMD_SC_UPDT_DATA,
-        INIT_CMD_SC_UPDT_DATA_HIGH
+        INIT_CMD_CAS_UPDT_IDLE,
+        INIT_CMD_CAS_BRDCAST,
+        INIT_CMD_CAS_UPDT_NLINE,
+        INIT_CMD_CAS_UPDT_INDEX,
+        INIT_CMD_CAS_UPDT_DATA,
+        INIT_CMD_CAS_UPDT_DATA_HIGH
       };
 
@@ -199,34 +200,34 @@
         IXR_CMD_READ_IDLE,
         IXR_CMD_WRITE_IDLE,
-        IXR_CMD_SC_IDLE,
+        IXR_CMD_CAS_IDLE,
         IXR_CMD_XRAM_IDLE,
         IXR_CMD_READ_NLINE,
         IXR_CMD_WRITE_NLINE,
-        IXR_CMD_SC_NLINE,
+        IXR_CMD_CAS_NLINE,
         IXR_CMD_XRAM_DATA
       };
 
-      /* States of the SC fsm */
-      enum sc_fsm_state_e{
-        SC_IDLE,
-        SC_DIR_REQ,
-        SC_DIR_LOCK,
-        SC_DIR_HIT_READ,
-        SC_DIR_HIT_WRITE,
-        SC_UPT_LOCK,
-        SC_UPT_HEAP_LOCK,
-        SC_UPT_REQ,
-        SC_UPT_NEXT,
-        SC_BC_TRT_LOCK,
-        SC_BC_UPT_LOCK,
-        SC_BC_DIR_INVAL,
-        SC_BC_CC_SEND,
-        SC_BC_XRAM_REQ,
-        SC_RSP_FAIL,
-        SC_RSP_SUCCESS,
-        SC_MISS_TRT_LOCK,
-        SC_MISS_TRT_SET,
-        SC_MISS_XRAM_REQ,
-        SC_WAIT
+      /* States of the CAS fsm */
+      enum cas_fsm_state_e{
+        CAS_IDLE,
+        CAS_DIR_REQ,
+        CAS_DIR_LOCK,
+        CAS_DIR_HIT_READ,
+        CAS_DIR_HIT_WRITE,
+        CAS_UPT_LOCK,
+        CAS_UPT_HEAP_LOCK,
+        CAS_UPT_REQ,
+        CAS_UPT_NEXT,
+        CAS_BC_TRT_LOCK,
+        CAS_BC_UPT_LOCK,
+        CAS_BC_DIR_INVAL,
+        CAS_BC_CC_SEND,
+        CAS_BC_XRAM_REQ,
+        CAS_RSP_FAIL,
+        CAS_RSP_SUCCESS,
+        CAS_MISS_TRT_LOCK,
+        CAS_MISS_TRT_SET,
+        CAS_MISS_XRAM_REQ,
+        CAS_WAIT
       };
 
@@ -253,5 +254,5 @@
         ALLOC_DIR_READ,
         ALLOC_DIR_WRITE,
-        ALLOC_DIR_SC,
+        ALLOC_DIR_CAS,
         ALLOC_DIR_CLEANUP,
         ALLOC_DIR_XRAM_RSP
@@ -262,5 +263,5 @@
         ALLOC_TRT_READ,
         ALLOC_TRT_WRITE,
-        ALLOC_TRT_SC,
+        ALLOC_TRT_CAS,
         ALLOC_TRT_XRAM_RSP,
         ALLOC_TRT_IXR_RSP
@@ -273,5 +274,5 @@
         ALLOC_UPT_INIT_RSP,
         ALLOC_UPT_CLEANUP,
-        ALLOC_UPT_SC
+        ALLOC_UPT_CAS
       };
 
@@ -281,7 +282,35 @@
         ALLOC_HEAP_READ,
         ALLOC_HEAP_WRITE,
-        ALLOC_HEAP_SC,
+        ALLOC_HEAP_CAS,
         ALLOC_HEAP_CLEANUP,
         ALLOC_HEAP_XRAM_RSP
+      };
+
+      /* transaction type, pktid field */
+      enum transaction_type_e
+      {
+          // b3 unused
+          // b2 READ / NOT READ
+          // Si READ
+          //  b1 DATA / INS
+          //  b0 UNC / MISS
+          // Si NOT READ
+          //  b1 accÃšs table llsc type SW / other
+          //  b2 WRITE/CAS/LL/SC
+          TYPE_READ_DATA_UNC          = 0x0,
+          TYPE_READ_DATA_MISS         = 0x1,
+          TYPE_READ_INS_UNC           = 0x2,
+          TYPE_READ_INS_MISS          = 0x3,
+          TYPE_WRITE                  = 0x4,
+          TYPE_CAS                    = 0x5,
+          TYPE_LL                     = 0x6,
+          TYPE_SC                     = 0x7
+      };
+
+      /* SC return values */
+      enum sc_status_type_e
+      {
+          SC_SUCCESS  =   0x00000000,
+          SC_FAIL     =   0x00000001
       };
 
@@ -296,5 +325,5 @@
       bool         m_debug_read_fsm;
       bool         m_debug_write_fsm;
-      bool         m_debug_sc_fsm;
+      bool         m_debug_cas_fsm;
       bool         m_debug_cleanup_fsm;
       bool         m_debug_ixr_cmd_fsm;
@@ -326,4 +355,5 @@
       uint32_t     m_cpt_ll;            // Number of LL transactions
       uint32_t     m_cpt_sc;            // Number of SC transactions
+      uint32_t     m_cpt_cas;           // Number of CAS transactions
 
       size_t       m_prev_count;
@@ -429,11 +459,11 @@
       GenericFifo<be_t>      m_cmd_write_be_fifo;
 
-      // Fifo between TGT_CMD fsm and SC fsm
-      GenericFifo<uint64_t>  m_cmd_sc_addr_fifo;
-      GenericFifo<bool>      m_cmd_sc_eop_fifo;
-      GenericFifo<size_t>    m_cmd_sc_srcid_fifo;
-      GenericFifo<size_t>    m_cmd_sc_trdid_fifo;
-      GenericFifo<size_t>    m_cmd_sc_pktid_fifo;
-      GenericFifo<data_t>    m_cmd_sc_wdata_fifo;
+      // Fifo between TGT_CMD fsm and CAS fsm
+      GenericFifo<uint64_t>  m_cmd_cas_addr_fifo;
+      GenericFifo<bool>      m_cmd_cas_eop_fifo;
+      GenericFifo<size_t>    m_cmd_cas_srcid_fifo;
+      GenericFifo<size_t>    m_cmd_cas_trdid_fifo;
+      GenericFifo<size_t>    m_cmd_cas_pktid_fifo;
+      GenericFifo<data_t>    m_cmd_cas_wdata_fifo;
 
       sc_signal<int>         r_tgt_cmd_fsm;
@@ -594,59 +624,59 @@
 
       ///////////////////////////////////////////////////////
-      // Registers controlled by SC fsm
+      // Registers controlled by CAS fsm
       ///////////////////////////////////////////////////////
 
-      sc_signal<int>      r_sc_fsm;        // FSM state
-      sc_signal<data_t>   r_sc_wdata;      // write data word
-      sc_signal<data_t> * r_sc_rdata;      // read data word
-      sc_signal<uint32_t> r_sc_lfsr;       // lfsr for random introducing
-      sc_signal<size_t>   r_sc_cpt;        // size of command
-      sc_signal<copy_t>   r_sc_copy;       // Srcid of the first copy
-      sc_signal<copy_t>   r_sc_copy_cache; // Srcid of the first copy
-      sc_signal<bool>     r_sc_copy_inst;  // Type of the first copy
-      sc_signal<size_t>   r_sc_count;      // number of copies
-      sc_signal<size_t>   r_sc_ptr;        // pointer to the heap
-      sc_signal<size_t>   r_sc_next_ptr;   // next pointer to the heap
-      sc_signal<bool>     r_sc_is_cnt;     // is_cnt bit (in directory)
-      sc_signal<bool>     r_sc_dirty;      // dirty bit (in directory)
-      sc_signal<size_t>   r_sc_way;        // way in directory
-      sc_signal<size_t>   r_sc_set;        // set in directory
-      sc_signal<data_t>   r_sc_tag;        // cache line tag (in directory)
-      sc_signal<size_t>   r_sc_trt_index;  // Transaction Table index
-      sc_signal<size_t>   r_sc_upt_index;  // Update Table index
-
-      // Buffer between SC fsm and INIT_CMD fsm (XRAM read)
-      sc_signal<bool>     r_sc_to_ixr_cmd_req;   // valid request
-      sc_signal<addr_t>   r_sc_to_ixr_cmd_nline; // cache line index
-      sc_signal<size_t>   r_sc_to_ixr_cmd_trdid; // index in Transaction Table
-      sc_signal<bool>     r_sc_to_ixr_cmd_write; // write request
-      sc_signal<data_t> * r_sc_to_ixr_cmd_data;  // cache line data
-
-
-      // Buffer between SC fsm and TGT_RSP fsm
-      sc_signal<bool>     r_sc_to_tgt_rsp_req;   // valid request
-      sc_signal<data_t>   r_sc_to_tgt_rsp_data;  // read data word
-      sc_signal<size_t>   r_sc_to_tgt_rsp_srcid; // Transaction srcid
-      sc_signal<size_t>   r_sc_to_tgt_rsp_trdid; // Transaction trdid
-      sc_signal<size_t>   r_sc_to_tgt_rsp_pktid; // Transaction pktid
-
-      // Buffer between SC fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
-      sc_signal<bool>     r_sc_to_init_cmd_multi_req;     // valid request
-      sc_signal<bool>     r_sc_to_init_cmd_brdcast_req;   // brdcast request
-      sc_signal<addr_t>   r_sc_to_init_cmd_nline;         // cache line index
-      sc_signal<size_t>   r_sc_to_init_cmd_trdid;         // index in Update Table
-      sc_signal<data_t>   r_sc_to_init_cmd_wdata;         // data (one word)
-      sc_signal<bool>     r_sc_to_init_cmd_is_long;       // it is a 64 bits SC
-      sc_signal<data_t>   r_sc_to_init_cmd_wdata_high;    // data high (one word)
-      sc_signal<size_t>   r_sc_to_init_cmd_index;         // index of the word in line
-      GenericFifo<bool>   m_sc_to_init_cmd_inst_fifo;     // fifo for the L1 type
-      GenericFifo<size_t> m_sc_to_init_cmd_srcid_fifo;    // fifo for srcids
+      sc_signal<int>      r_cas_fsm;        // FSM state
+      sc_signal<data_t>   r_cas_wdata;      // write data word
+      sc_signal<data_t> * r_cas_rdata;      // read data word
+      sc_signal<uint32_t> r_cas_lfsr;       // lfsr for random introducing
+      sc_signal<size_t>   r_cas_cpt;        // size of command
+      sc_signal<copy_t>   r_cas_copy;       // Srcid of the first copy
+      sc_signal<copy_t>   r_cas_copy_cache; // Srcid of the first copy
+      sc_signal<bool>     r_cas_copy_inst;  // Type of the first copy
+      sc_signal<size_t>   r_cas_count;      // number of copies
+      sc_signal<size_t>   r_cas_ptr;        // pointer to the heap
+      sc_signal<size_t>   r_cas_next_ptr;   // next pointer to the heap
+      sc_signal<bool>     r_cas_is_cnt;     // is_cnt bit (in directory)
+      sc_signal<bool>     r_cas_dirty;      // dirty bit (in directory)
+      sc_signal<size_t>   r_cas_way;        // way in directory
+      sc_signal<size_t>   r_cas_set;        // set in directory
+      sc_signal<data_t>   r_cas_tag;        // cache line tag (in directory)
+      sc_signal<size_t>   r_cas_trt_index;  // Transaction Table index
+      sc_signal<size_t>   r_cas_upt_index;  // Update Table index
+
+      // Buffer between CAS fsm and INIT_CMD fsm (XRAM read)
+      sc_signal<bool>     r_cas_to_ixr_cmd_req;   // valid request
+      sc_signal<addr_t>   r_cas_to_ixr_cmd_nline; // cache line index
+      sc_signal<size_t>   r_cas_to_ixr_cmd_trdid; // index in Transaction Table
+      sc_signal<bool>     r_cas_to_ixr_cmd_write; // write request
+      sc_signal<data_t> * r_cas_to_ixr_cmd_data;  // cache line data
+
+
+      // Buffer between CAS fsm and TGT_RSP fsm
+      sc_signal<bool>     r_cas_to_tgt_rsp_req;   // valid request
+      sc_signal<data_t>   r_cas_to_tgt_rsp_data;  // read data word
+      sc_signal<size_t>   r_cas_to_tgt_rsp_srcid; // Transaction srcid
+      sc_signal<size_t>   r_cas_to_tgt_rsp_trdid; // Transaction trdid
+      sc_signal<size_t>   r_cas_to_tgt_rsp_pktid; // Transaction pktid
+
+      // Buffer between CAS fsm and INIT_CMD fsm (Update/Invalidate L1 caches)
+      sc_signal<bool>     r_cas_to_init_cmd_multi_req;     // valid request
+      sc_signal<bool>     r_cas_to_init_cmd_brdcast_req;   // brdcast request
+      sc_signal<addr_t>   r_cas_to_init_cmd_nline;         // cache line index
+      sc_signal<size_t>   r_cas_to_init_cmd_trdid;         // index in Update Table
+      sc_signal<data_t>   r_cas_to_init_cmd_wdata;         // data (one word)
+      sc_signal<bool>     r_cas_to_init_cmd_is_long;       // it is a 64 bits CAS
+      sc_signal<data_t>   r_cas_to_init_cmd_wdata_high;    // data high (one word)
+      sc_signal<size_t>   r_cas_to_init_cmd_index;         // index of the word in line
+      GenericFifo<bool>   m_cas_to_init_cmd_inst_fifo;     // fifo for the L1 type
+      GenericFifo<size_t> m_cas_to_init_cmd_srcid_fifo;    // fifo for srcids
 #if L1_MULTI_CACHE
-      GenericFifo<size_t> m_sc_to_init_cmd_cache_id_fifo; // fifo for srcids
+      GenericFifo<size_t> m_cas_to_init_cmd_cache_id_fifo; // fifo for srcids
 #endif
 
-      // Buffer between SC fsm and INIT_RSP fsm (Decrement UPT entry)
-      sc_signal<bool>     r_sc_to_init_rsp_req;       // valid request
-      sc_signal<size_t>   r_sc_to_init_rsp_upt_index; // index in update table
+      // Buffer between CAS fsm and INIT_RSP fsm (Decrement UPT entry)
+      sc_signal<bool>     r_cas_to_init_rsp_req;       // valid request
+      sc_signal<size_t>   r_cas_to_init_rsp_upt_index; // index in update table
 
       ////////////////////////////////////////////////////
