Changeset 289 for trunk/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h

Timestamp:

Jan 20, 2013, 7:09:37 PM (11 years ago)

Author:

cfuguet

Message:

Introducing cache data ram with bit masking in the Memory Cache.
The goal of this modifications is the alignment of the SOCLIB model
against the VHDL one.

Due to this new property in the Cache Data of the Memory Cache,
the FSM's of this component do not need to read and then write when
doing a not full word write operation.

File:

• trunk/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h (modified) (1 diff)

trunk/modules/vci_mem_cache_v4/caba/source/include/mem_cache_directory_v4.h

@@ -620 +620 @@
   }; // end class HeapDirectory
 
+  ////////////////////////////////////////////////////////////////////////
+  //                        Cache Data 
+  ////////////////////////////////////////////////////////////////////////
+  class CacheData {
+    private:
+      const uint32_t m_sets;
+      const uint32_t m_ways;
+      const uint32_t m_words;
+
+      uint32_t *** m_cache_data;
+
+    public:
+
+      CacheData(uint32_t ways, uint32_t sets, uint32_t words)
+        : m_sets(sets), m_ways(ways), m_words(words) {
+
+          m_cache_data = new uint32_t ** [ways];
+          for ( size_t i=0 ; i < ways ; i++ ) {
+            m_cache_data[i] = new uint32_t * [sets];
+          }
+          for ( size_t i=0; i<ways; i++ ) {
+            for ( size_t j=0; j<sets; j++ ) {
+              m_cache_data[i][j] = new uint32_t [words];
+            }
+          }
+        }
+
+      ~CacheData() {
+          for(size_t i=0; i<m_ways ; i++){
+              for(size_t j=0; j<m_sets ; j++){
+                  delete [] m_cache_data[i][j];
+              }
+          }
+          for(size_t i=0; i<m_ways ; i++){
+              delete [] m_cache_data[i];
+          }
+          delete [] m_cache_data;
+      }
+
+      uint32_t read (
+          const uint32_t &way,
+          const uint32_t &set,
+          const uint32_t &word) const {
+
+        assert((set  < m_sets ) && "Cache data error: Trying to read a wrong set" );
+        assert((way  < m_ways ) && "Cache data error: Trying to read a wrong way" );
+        assert((word < m_words) && "Cache data error: Trying to read a wrong word");
+
+        return m_cache_data[way][set][word];
+      }
+
+      void read_line(
+          const uint32_t &way,
+          const uint32_t &set,
+          sc_core::sc_signal<uint32_t> * cache_line)
+      {
+        assert((set < m_sets ) && "Cache data error: Trying to read a wrong set" );
+        assert((way < m_ways ) && "Cache data error: Trying to read a wrong way" );
+      
+        for (uint32_t word=0; word<m_words; word++)
+          cache_line[word].write(m_cache_data[way][set][word]);
+      }
+
+      void write (
+          const uint32_t &way,
+          const uint32_t &set,
+          const uint32_t &word,
+          const uint32_t &data,
+          const uint32_t &be = 0xF) {
+
+        assert((set  < m_sets ) && "Cache data error: Trying to write a wrong set" );
+        assert((way  < m_ways ) && "Cache data error: Trying to write a wrong way" );
+        assert((word < m_words) && "Cache data error: Trying to write a wrong word");
+        assert((be  <= 0xF    ) && "Cache data error: Trying to write a wrong word cell");
+
+        if (be == 0x0) return;
+
+        if (be == 0xF) {
+            m_cache_data[way][set][word] = data; 
+            return;
+        }
+
+        uint32_t mask = 0;
+        if  (be & 0x1) mask = mask | 0x000000FF;
+        if  (be & 0x2) mask = mask | 0x0000FF00;
+        if  (be & 0x4) mask = mask | 0x00FF0000;
+        if  (be & 0x8) mask = mask | 0xFF000000;
+
+        m_cache_data[way][set][word] = 
+          (data & mask) | (m_cache_data[way][set][word] & ~mask);
+      }
+  }; // end class CacheData
 
 }} // end namespaces