Changeset 289 for trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h

Timestamp:

Jan 20, 2013, 7:09:37 PM (11 years ago)

Author:

cfuguet

Message:

Introducing cache data ram with bit masking in the Memory Cache.
The goal of this modifications is the alignment of the SOCLIB model
against the VHDL one.

Due to this new property in the Cache Data of the Memory Cache,
the FSM's of this component do not need to read and then write when
doing a not full word write operation.

File:

• trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h (modified) (1 diff)

trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h

@@ -420 +420 @@
       UpdateTab       m_update_tab;       // pending update & invalidate
       CacheDirectory  m_cache_directory;  // data cache directory
+      CacheData       m_cache_data;       // data array[set][way][word]
       HeapDirectory   m_heap;             // heap for copies
-
-      data_t      *** m_cache_data;       // data array[set][way][word]
 
       // adress masks