Changeset 291 for trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp

Timestamp:

Jan 28, 2013, 1:59:32 PM (11 years ago)

Author:

joannou

Message:

Introducing new generic_llsc_local_table and generic_llsc_global_table components :
These two tables implement the new scalable LL/SC mechanism for TSAR.

• generic_llsc_local_table, integrated in the vci_cc_vache_wrapper_v4 component. The table is accessed by the DCACHE_FSM. A two step registration (LL cmd/ LL rsp) sets a signature allocated by the global table for the pending LL/SC operation. An SC operation consumes the registration.
• generic_llsc_global_table, integrated in the vci_mem_cache_v4 component. The table is accessed by the READ_FSM, WRITE_FSM, CAS_FSM, when accessing the directory. It generates a signature for LL registrations and performs SC operation by checking registration's valididty with that signature. SW operations simply invalidate a registrations.

N.B. :

• The sizes of the tables are parameters, and are NOT a function of the architecture's size (scalable mechanism).
• The LL are handled by the MEMCACHE in the READ_FSM.
• The SC are handled by the MEMCACHE in the WRITE_FSM, and are no longer CAS emulated. CAS operation is now only performed by hardware mechanisms.
• An extra field is added to the xram transaction table to save a pending LL's signature.

File:

• trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp (modified) (36 diffs)

trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp

@@ -293 +293 @@
     m_cache_data( nways, nsets, nwords ),
     m_heap( m_heap_size ),
+    m_llsc_table(),
 
 #define L2 soclib::common::uint32_log2
@@ -511 +512 @@
               << " | " << ixr_rsp_fsm_str[r_ixr_rsp_fsm]
               << " | " << xram_rsp_fsm_str[r_xram_rsp_fsm] << std::endl;
+
+              //m_llsc_table.print_trace();
+
 }
 
@@ -860 +864 @@
           assert(((p_vci_tgt.pktid.read() & 0x7) == 0x6) &&
             "The type specified in the pktid field is incompatible with the LL CMD");
-          assert(false && "TODO : LL not implemented"); //TODO
-          //r_tgt_cmd_fsm = TGT_CMD_READ;
+          r_tgt_cmd_fsm = TGT_CMD_READ;
         }
         else if ( p_vci_tgt.cmd.read() == vci_param::CMD_NOP )
@@ -874 +877 @@
             "The type specified in the pktid field is incompatible with the NOP CMD");
 
-          if(p_vci_tgt.pktid.read() == TYPE_CAS)
+          if((p_vci_tgt.pktid.read() & 0x7) == TYPE_CAS)
             r_tgt_cmd_fsm = TGT_CMD_CAS;
           else // TYPE_SC
-            assert(false && "TODO : SC not implemented"); //TODO
-            //r_tgt_cmd_fsm = TGT_CMD_WRITE;
+            r_tgt_cmd_fsm = TGT_CMD_WRITE;
         }
         else
@@ -892 +894 @@
     //////////////////
     case TGT_CMD_READ:
-      if ((m_x[(vci_addr_t)p_vci_tgt.address.read()]+(p_vci_tgt.plen.read()>>2)) > 16)
+      // This test checks that the read does not cross a cache line limit.
+      // It must not be taken into account when dealing with an LL CMD.
+      if (((m_x[(vci_addr_t)p_vci_tgt.address.read()]+(p_vci_tgt.plen.read()>>2)) > 16) && ( p_vci_tgt.cmd.read() != vci_param::CMD_LOCKED_READ ))
       {
         std::cout
@@ -907 +911 @@
           << std::endl;
         std::cout
-          << " read command packets must contain one single flit"
+          << " read or ll command packets must contain one single flit"
           << std::endl;
         exit(0);
@@ -927 +931 @@
 #endif
         cmd_read_fifo_put = true;
-        m_cpt_read++;
+        if ( p_vci_tgt.cmd.read() == vci_param::CMD_LOCKED_READ )
+          m_cpt_ll++;
+        else
+          m_cpt_read++;
         r_tgt_cmd_fsm = TGT_CMD_IDLE;
       }
@@ -1139 +1146 @@
   //    READ FSM
   ////////////////////////////////////////////////////////////////////////////////////
-  // The READ FSM controls the VCI read requests.
+  // The READ FSM controls the VCI read  and ll requests.
   // It takes the lock protecting the cache directory to check the cache line status:
   // - In case of HIT
@@ -1174 +1181 @@
             << " srcid = " << std::dec << m_cmd_read_srcid_fifo.read()
             << " / address = " << std::hex << m_cmd_read_addr_fifo.read()
+            << " / pktid = " << std::hex << m_cmd_read_pktid_fifo.read()
             << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl;
         }
@@ -1211 +1219 @@
         DirectoryEntry entry =
           m_cache_directory.read(m_cmd_read_addr_fifo.read(), way);
-
+        if((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) // access the global table ONLY when we have an LL cmd
+        {
+          r_read_ll_key   = m_llsc_table.ll(m_cmd_read_addr_fifo.read());
+        }
         r_read_is_cnt     = entry.is_cnt;
         r_read_dirty      = entry.dirty;
@@ -1256 +1267 @@
             << " / count = " <<std::dec << entry.count
             << " / is_cnt = " << entry.is_cnt << std::endl;
+            if((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL)
+            {
+              std::cout
+                << "  <MEMC " << name() << ".READ_DIR_LOCK> global_llsc_table LL access" << std::endl;
+            }
         }
 #endif
@@ -1604 +1620 @@
         r_read_to_tgt_rsp_trdid  = m_cmd_read_trdid_fifo.read();
         r_read_to_tgt_rsp_pktid  = m_cmd_read_pktid_fifo.read();
-        cmd_read_fifo_get    = true;
-        r_read_to_tgt_rsp_req  = true;
-        r_read_fsm     = READ_IDLE;
+        r_read_to_tgt_rsp_ll_key = r_read_ll_key.read();
+        cmd_read_fifo_get        = true;
+        r_read_to_tgt_rsp_req    = true;
+        r_read_fsm               = READ_IDLE;
 
 #if DEBUG_MEMC_READ
@@ -1673 +1690 @@
             m_x[(vci_addr_t)(m_cmd_read_addr_fifo.read())],
             std::vector<be_t>(m_words,0),
-            std::vector<data_t>(m_words,0));
+            std::vector<data_t>(m_words,0),
+            r_read_ll_key.read());
 #if DEBUG_MEMC_READ
         if( m_debug_read_fsm )
@@ -1718 +1736 @@
   //    WRITE FSM
   ///////////////////////////////////////////////////////////////////////////////////
-  // The WRITE FSM handles the write bursts sent by the processors.
+  // The WRITE FSM handles the write bursts and sc requests sent by the processors.
   // All addresses in a burst must be in the same cache line.
   // A complete write burst is consumed in the FIFO & copied to a local buffer.
@@ -1728 +1746 @@
   //   returned to the writing processor.
   //   If the data is cached by other processors, a coherence transaction must
-  //   be launched:
+  //   be launched (sc requests always require a coherence transaction):
   //   It is a multicast update if the line is not in counter mode, and the processor
   //   takes the lock protecting the Update Table (UPT) to register this transaction.
@@ -1753 +1771 @@
       if ( m_cmd_write_addr_fifo.rok() )
       {
-        m_cpt_write++;
-        m_cpt_write_cells++;
+        if((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC)
+          m_cpt_sc++;
+        else
+        {
+          m_cpt_write++;
+          m_cpt_write_cells++;
+        }
 
         // consume a word in the FIFO & write it in the local buffer
         cmd_write_fifo_get  = true;
+        r_write_pending_sc  = false;
         size_t index        = m_x[(vci_addr_t)(m_cmd_write_addr_fifo.read())];
 
@@ -1775 +1799 @@
         }
 
-        if( m_cmd_write_eop_fifo.read() )
+        if( m_cmd_write_eop_fifo.read() || ((m_cmd_write_pktid_fifo.read() & 0x7)  == TYPE_SC) )
         {
           r_write_fsm = WRITE_DIR_REQ;
@@ -1824 +1848 @@
         // consume a word in the FIFO & write it in the local buffer
         cmd_write_fifo_get  = true;
+        r_write_pending_sc  = false;
         size_t index        = r_write_word_index.read() + r_write_word_count.read();
 
@@ -1844 +1869 @@
       if ( r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE )
       {
+        if(((r_write_pktid.read() & 0x7) == TYPE_SC) && not r_write_pending_sc.read()) // check for an SC command (and check that its second flit is not already consumed)
+        {
+          if ( m_cmd_write_addr_fifo.rok() )
+          {
+            size_t index    = m_x[(vci_addr_t)(r_write_address.read())];
+            bool sc_success = m_llsc_table.sc(r_write_address.read(),r_write_data[index].read());
+            r_write_sc_fail = !sc_success;
+
+            assert(m_cmd_write_eop_fifo.read() && "Error in VCI_MEM_CACHE : invalid packet format for SC command");
+            // consume a word in the FIFO & write it in the local buffer
+            cmd_write_fifo_get  = true;
+            r_write_pending_sc  = true;
+            index               = m_x[(vci_addr_t)(m_cmd_write_addr_fifo.read())];
+
+            r_write_address     = (addr_t)(m_cmd_write_addr_fifo.read());
+            r_write_word_index  = index;
+            r_write_word_count  = 1;
+            r_write_data[index] = m_cmd_write_data_fifo.read();
+            if (!sc_success)
+            {
+              r_write_fsm = WRITE_RSP;
+              break;
+            }
+          }
+          else break;
+        }
+        //else it is a TYPE_WRITE, need a simple sw access to the
+        // llsc_global_table
+        else
+        {
+          m_llsc_table.sw(r_write_address.read());
+        }
         r_write_fsm = WRITE_DIR_LOCK;
       }
@@ -1905 +1962 @@
             << " count = " << entry.count
             << " is_cnt = " << entry.is_cnt << std::endl;
+          if((r_write_pktid.read() & 0x7) == TYPE_SC)
+            std::cout << "  <MEMC " << name() << ".WRITE_DIR_LOCK> global_llsc_table SC access" << std::endl;
+          else
+            std::cout << "  <MEMC " << name() << ".WRITE_DIR_LOCK> global_llsc_table SW access" << std::endl;
         }
 #endif
@@ -1985 +2046 @@
 
       // no_update is true when there is no need for coherence transaction
-      bool no_update = (r_write_count.read()==0) || ( owner && (r_write_count.read()==1));
+      // (tests for sc requests)
+      bool no_update = ((r_write_count.read()==0) || ( owner && (r_write_count.read()==1) && (r_write_pktid.read() != TYPE_SC)));
 
       // write data in the cache if no coherence transaction
@@ -2004 +2066 @@
       }
 
-      if ( owner and not no_update )
+      if ( owner and not no_update and (r_write_pktid.read() != TYPE_SC))
       {
         r_write_count = r_write_count.read() - 1;
@@ -2127 +2189 @@
     case WRITE_UPT_REQ:
     {
-      // prepare the coherence ransaction for the INIT_CMD FSM
+      // prepare the coherence transaction for the INIT_CMD FSM
       // and write the first copy in the FIFO
       // send the request if only one copy
@@ -2146 +2208 @@
         for (size_t i=min ; i<max ; i++) r_write_to_init_cmd_data[i] = r_write_data[i];
 
-        if( (r_write_copy.read() != r_write_srcid.read()) or
+        if( (r_write_copy.read() != r_write_srcid.read()) or (r_write_pktid.read() == TYPE_SC) or
 #if L1_MULTI_CACHE
             (r_write_copy_cache.read() != r_write_pktid.read()) or
@@ -2159 +2221 @@
           write_to_init_cmd_fifo_cache_id= r_write_copy_cache.read();
 #endif
-          if(r_write_count.read() == 1)
+          if(r_write_count.read() == 1 || ((r_write_count.read() == 0) && (r_write_pktid.read() == TYPE_SC)) )
           {
             r_write_fsm = WRITE_IDLE;
@@ -2207 +2269 @@
       bool dec_upt_counter;
 
-      if( (entry.owner.srcid != r_write_srcid.read()) or
+      if(((entry.owner.srcid != r_write_srcid.read()) || (r_write_pktid.read() == TYPE_SC)) or
 #if L1_MULTI_CACHE
           (entry.owner.cache_id != r_write_pktid.read()) or
 #endif
-          entry.owner.inst)               // put te next srcid in the fifo
+          entry.owner.inst)             // put the next srcid in the fifo
       {
         dec_upt_counter                 = false;
@@ -2299 +2361 @@
       {
         // post the request to TGT_RSP_FSM
-        r_write_to_tgt_rsp_req   = true;
-        r_write_to_tgt_rsp_srcid = r_write_srcid.read();
-        r_write_to_tgt_rsp_trdid = r_write_trdid.read();
-        r_write_to_tgt_rsp_pktid = r_write_pktid.read();
+        r_write_to_tgt_rsp_req     = true;
+        r_write_to_tgt_rsp_srcid   = r_write_srcid.read();
+        r_write_to_tgt_rsp_trdid   = r_write_trdid.read();
+        r_write_to_tgt_rsp_pktid   = r_write_pktid.read();
+        r_write_to_tgt_rsp_sc_fail = r_write_sc_fail.read();
 
         // try to get a new write request from the FIFO
         if ( m_cmd_write_addr_fifo.rok() )
         {
-          m_cpt_write++;
-          m_cpt_write_cells++;
+          if((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC)
+            m_cpt_sc++;
+          else
+          {
+            m_cpt_write++;
+            m_cpt_write_cells++;
+          }
 
           // consume a word in the FIFO & write it in the local buffer
           cmd_write_fifo_get  = true;
+          r_write_pending_sc  = false;
           size_t index        = m_x[(vci_addr_t)(m_cmd_write_addr_fifo.read())];
 
@@ -2329 +2398 @@
           }
 
-          if( m_cmd_write_eop_fifo.read() )
+          if( m_cmd_write_eop_fifo.read() || ((m_cmd_write_pktid_fifo.read() & 0x7)  == TYPE_SC) )
           {
             r_write_fsm = WRITE_DIR_REQ;
@@ -3191 +3260 @@
             entry.lock    = false;
             entry.dirty   = dirty;
-            entry.tag   = r_xram_rsp_trt_buf.nline / m_sets;
+            entry.tag     = r_xram_rsp_trt_buf.nline / m_sets;
             entry.ptr     = 0;
             if(cached_read)
@@ -3305 +3374 @@
                 r_xram_rsp_to_tgt_rsp_word   = r_xram_rsp_trt_buf.word_index;
                 r_xram_rsp_to_tgt_rsp_length = r_xram_rsp_trt_buf.read_length;
+                r_xram_rsp_to_tgt_rsp_ll_key = r_xram_rsp_trt_buf.ll_key;
                 r_xram_rsp_to_tgt_rsp_rerror = false;
                 r_xram_rsp_to_tgt_rsp_req    = true;
@@ -4371 +4441 @@
         //////////////////////
         case CAS_DIR_HIT_WRITE:    // test if a CC transaction is required
-                                    // write data in cache if no CC request
-        {
+                                   // write data in cache if no CC request
+        {
+            // The CAS is a success => sw access to the llsc_global_table
+            m_llsc_table.sw(m_cmd_cas_addr_fifo.read());
+
             // test coherence request
             if(r_cas_count.read())   // replicated line
@@ -4422 +4495 @@
               << " / value = " << r_cas_wdata.read()
               << " / count = " << r_cas_count.read() << std::endl;
+    std::cout << "  <MEMC " << name() << ".CAS_DIR_HIT_WRITE> global_llsc_table SW access" << std::endl;
 }
 #endif
@@ -6383 +6457 @@
       case TGT_RSP_READ:
         p_vci_tgt.rspval   = true;
-        p_vci_tgt.rdata    = r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read();
+        if( ((r_read_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL)
+            && (r_tgt_rsp_cpt.read() == (r_read_to_tgt_rsp_word.read()+r_read_to_tgt_rsp_length-1)) )
+          p_vci_tgt.rdata  = r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()-1].read();
+        else if ((r_read_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL)
+          p_vci_tgt.rdata  = r_read_to_tgt_rsp_ll_key.read();
+        else
+          p_vci_tgt.rdata  = r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read();
         p_vci_tgt.rsrcid   = r_read_to_tgt_rsp_srcid.read();
         p_vci_tgt.rtrdid   = r_read_to_tgt_rsp_trdid.read();
@@ -6391 +6471 @@
         break;
       case TGT_RSP_WRITE:
+        /*if( ((r_write_to_tgt_rsp_pktid.read() & 0x7) == TYPE_SC) )
+            {
+              std::cout << "SC RSP / rsrcid = " << r_write_to_tgt_rsp_srcid.read() << " / rdata = " << r_write_to_tgt_rsp_sc_fail.read() << std::endl;
+            }*/
         p_vci_tgt.rspval   = true;
-        p_vci_tgt.rdata    = 0;
+        if( ((r_write_to_tgt_rsp_pktid.read() & 0x7) == TYPE_SC) && r_write_to_tgt_rsp_sc_fail.read() )
+          p_vci_tgt.rdata  = 1;
+        else
+          p_vci_tgt.rdata  = 0;
         p_vci_tgt.rsrcid   = r_write_to_tgt_rsp_srcid.read();
         p_vci_tgt.rtrdid   = r_write_to_tgt_rsp_trdid.read();
         p_vci_tgt.rpktid   = r_write_to_tgt_rsp_pktid.read();
-        p_vci_tgt.rerror   = 0x2 & ( (1 << vci_param::E) - 1);
+        //p_vci_tgt.rerror   = 0x2 & ( (1 << vci_param::E) - 1);
+        p_vci_tgt.rerror   = 0;
         p_vci_tgt.reop     = true;
         break;
@@ -6419 +6507 @@
       case TGT_RSP_XRAM:
         p_vci_tgt.rspval   = true;
-        p_vci_tgt.rdata    = r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read();
+        if( ((r_xram_rsp_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL)
+            && (r_tgt_rsp_cpt.read() == (r_xram_rsp_to_tgt_rsp_word.read()+r_xram_rsp_to_tgt_rsp_length-1)) )
+          p_vci_tgt.rdata  = r_xram_rsp_to_tgt_rsp_ll_key.read();
+        else
+          p_vci_tgt.rdata  = r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read();
         p_vci_tgt.rsrcid   = r_xram_rsp_to_tgt_rsp_srcid.read();
         p_vci_tgt.rtrdid   = r_xram_rsp_to_tgt_rsp_trdid.read();
@@ -6430 +6522 @@
       case TGT_RSP_INIT:
         p_vci_tgt.rspval   = true;
-        p_vci_tgt.rdata    = 0;
+        p_vci_tgt.rdata    = 0; // Can be a CAS or SC rsp
         p_vci_tgt.rsrcid   = r_init_rsp_to_tgt_rsp_srcid.read();
         p_vci_tgt.rtrdid   = r_init_rsp_to_tgt_rsp_trdid.read();
         p_vci_tgt.rpktid   = r_init_rsp_to_tgt_rsp_pktid.read();
-        p_vci_tgt.rerror   = 0; // Can be a CAS rsp
+        p_vci_tgt.rerror   = 0;
         p_vci_tgt.reop     = true;
         break;