Changeset 347 for trunk/softs/tsar_boot/README.txt

Timestamp:

Apr 1, 2013, 8:57:02 PM (11 years ago)

Author:

cfuguet

Message:

Introducing dcache line invalidation mechanism in the boot_ioc_read
function, when using platform without cache coherency.

Introducing two parameters in the defs_platform.h file:

CACHE_COHERENCE

Equals to 0 when no cache coherency

CACHE_LINE_SIZE

Number of bytes in a cache line

• TODO: Use the config register of the cache models to get

this size

Adding new platform configuration file for the

caba_vgsb_xicu_mmu SOCLIB platform.

File:

• trunk/softs/tsar_boot/README.txt (modified) (2 diffs)

trunk/softs/tsar_boot/README.txt

@@ -9 +9 @@
 
 conf/       Platform specific files and ldscript.
-             For each platform, we must define a new directory.
+            For each platform, we must define a new directory.
 
       --->  defs_platform.h:
@@ -16 +16 @@
              NB_PROCS per cluster, the NB_CLUSTERS and the base address of
              the TTY, IOC and XICU devices.
-             It also defines the IRQ_PER_PROC constant. This constant is used
-             to know how many XICU irq outputs are connected to each processor.
+             It defines also:
+              -> CACHE_COHERENCE
+                 This constant is used by the boot_ioc_read function to know
+                 if the buffer used to store the blocks from the block_device
+                 must be invalidated in the dcache after the transfert has
+                 finished.
+                                 0 means invalidation must be made.
+
+              -> CACHE_LINE_SIZE
+                 This constant defines the size in bytes of a cache line.
+
+              -> IRQ_PER_PROC
+                 This constant is used to know how many XICU irq outputs are
+                 connected to each processor.
 
       --->  platform_soclib.dts: