Index: trunk/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h
===================================================================
--- trunk/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h	(revision 377)
+++ trunk/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h	(revision 385)
@@ -40,5 +40,4 @@
   ////////////////////////////////////////////////////////////////////////
   class Owner{
-    typedef uint32_t size_t;
     
     public:
@@ -92,5 +91,4 @@
 
     typedef uint32_t tag_t;
-    typedef uint32_t size_t;
 
     public:
@@ -165,6 +163,8 @@
     void print()
     {
-      std::cout << "Valid = " << valid << " ; IS COUNT = " << is_cnt << " ; Dirty = " << dirty << " ; Lock = " 
-                << lock 
+      std::cout << "Valid = " << valid 
+                << " ; IS COUNT = " << is_cnt 
+                << " ; Dirty = " << dirty 
+                << " ; Lock = " << lock 
                 << " ; Tag = " << std::hex << tag << std::dec 
                 << " ; Count = " << count 
@@ -187,5 +187,4 @@
     typedef uint32_t data_t;
     typedef uint32_t tag_t;
-    typedef uint32_t size_t;
 
     private:
@@ -408,5 +407,4 @@
   ///////////////////////////////////////////////////////////////////////
   class HeapEntry{
-    typedef uint32_t size_t;
 
     public:
@@ -472,5 +470,4 @@
   ////////////////////////////////////////////////////////////////////////
   class HeapDirectory{
-    typedef uint32_t size_t;
     
     private:
Index: trunk/modules/vci_mem_cache/caba/source/include/update_tab.h
===================================================================
--- trunk/modules/vci_mem_cache/caba/source/include/update_tab.h	(revision 377)
+++ trunk/modules/vci_mem_cache/caba/source/include/update_tab.h	(revision 385)
@@ -126,5 +126,4 @@
 class UpdateTab{
 
-  typedef uint32_t size_t;
   typedef sc_dt::sc_uint<40> addr_t;
 
Index: trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
===================================================================
--- trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h	(revision 377)
+++ trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h	(revision 385)
@@ -58,13 +58,17 @@
   using namespace sc_core;
 
-  template<typename vci_param>
+  template<typename vci_param_int, 
+           typename vci_param_ext,
+           size_t   dspin_in_width,
+           size_t   dspin_out_width>
     class VciMemCache
     : public soclib::caba::BaseModule
     {
-      typedef sc_dt::sc_uint<40> addr_t;
-      typedef typename vci_param::fast_addr_t vci_addr_t;
+      typedef typename vci_param_int::fast_addr_t  addr_t;
+
+      typedef typename sc_dt::sc_uint<64>          wide_data_t;
+
       typedef uint32_t data_t;
       typedef uint32_t tag_t;
-      typedef uint32_t size_t;
       typedef uint32_t be_t;
       typedef uint32_t copy_t;
@@ -343,6 +347,6 @@
 
       bool         m_monitor_ok;
-      vci_addr_t   m_monitor_base;
-      vci_addr_t   m_monitor_length;
+      addr_t       m_monitor_base;
+      addr_t       m_monitor_length;
 
       // instrumentation counters
@@ -373,10 +377,10 @@
 
       public:
-      sc_in<bool>                           p_clk;
-      sc_in<bool>                           p_resetn;
-      soclib::caba::VciTarget<vci_param>    p_vci_tgt;
-      soclib::caba::VciInitiator<vci_param> p_vci_ixr;
-      soclib::caba::DspinInput<33>          p_dspin_in;
-      soclib::caba::DspinOutput<40>         p_dspin_out;
+      sc_in<bool>                                 p_clk;
+      sc_in<bool>                                 p_resetn;
+      soclib::caba::VciTarget<vci_param_int>      p_vci_tgt;
+      soclib::caba::VciInitiator<vci_param_ext>   p_vci_ixr;
+      soclib::caba::DspinInput<dspin_in_width>    p_dspin_in;
+      soclib::caba::DspinOutput<dspin_out_width>  p_dspin_out;
 
       VciMemCache(
@@ -401,6 +405,6 @@
       void print_stats();
       void print_trace();
-      void copies_monitor(vci_addr_t addr);
-      void start_monitor(vci_addr_t addr, vci_addr_t length);
+      void copies_monitor(addr_t addr);
+      void start_monitor(addr_t addr, addr_t length);
       void stop_monitor();
 
@@ -409,6 +413,5 @@
       void transition();
       void genMoore();
-      void check_monitor( const char *buf, vci_addr_t addr, data_t data);
-      void check_monitor_read( const char *buf, vci_addr_t addr);
+      void check_monitor( const char *buf, addr_t addr, data_t data, bool read);
 
       // Component attributes
@@ -436,13 +439,12 @@
       < 32  ,                              // number of slots
         4096,                              // number of processors in the system
-        8000,                              // registratioÃ§n life span (in # of LL operations)
-        typename vci_param::fast_addr_t >  // address type
-                                         m_llsc_table;       // ll/sc global registration table
+        8000,                              // registration life (# of LL operations)
+        addr_t >  m_llsc_table;            // ll/sc global registration table
 
       // adress masks
-      const soclib::common::AddressMaskingTable<vci_addr_t>   m_x;
-      const soclib::common::AddressMaskingTable<vci_addr_t>   m_y;
-      const soclib::common::AddressMaskingTable<vci_addr_t>   m_z;
-      const soclib::common::AddressMaskingTable<vci_addr_t>   m_nline;
+      const soclib::common::AddressMaskingTable<addr_t>   m_x;
+      const soclib::common::AddressMaskingTable<addr_t>   m_y;
+      const soclib::common::AddressMaskingTable<addr_t>   m_z;
+      const soclib::common::AddressMaskingTable<addr_t>   m_nline;
 
       // broadcast address
@@ -454,5 +456,5 @@
 
       // Fifo between TGT_CMD fsm and READ fsm
-      GenericFifo<uint64_t>  m_cmd_read_addr_fifo;
+      GenericFifo<addr_t>    m_cmd_read_addr_fifo;
       GenericFifo<size_t>    m_cmd_read_length_fifo;
       GenericFifo<size_t>    m_cmd_read_srcid_fifo;
@@ -461,5 +463,5 @@
 
       // Fifo between TGT_CMD fsm and WRITE fsm
-      GenericFifo<uint64_t>  m_cmd_write_addr_fifo;
+      GenericFifo<addr_t>    m_cmd_write_addr_fifo;
       GenericFifo<bool>      m_cmd_write_eop_fifo;
       GenericFifo<size_t>    m_cmd_write_srcid_fifo;
@@ -470,5 +472,5 @@
 
       // Fifo between TGT_CMD fsm and CAS fsm
-      GenericFifo<uint64_t>  m_cmd_cas_addr_fifo;
+      GenericFifo<addr_t>    m_cmd_cas_addr_fifo;
       GenericFifo<bool>      m_cmd_cas_eop_fifo;
       GenericFifo<size_t>    m_cmd_cas_srcid_fifo;
@@ -504,6 +506,5 @@
       sc_signal<size_t>   r_read_next_ptr;   // Next entry to point to
       sc_signal<bool>     r_read_last_free;  // Last free entry
-      sc_signal<typename vci_param::fast_addr_t>
-                          r_read_ll_key;     // LL key returned by the llsc_global_table
+      sc_signal<addr_t>   r_read_ll_key;     // LL key from the llsc_global_table
 
       // Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
@@ -520,6 +521,5 @@
       sc_signal<size_t>   r_read_to_tgt_rsp_word;   // first word of the response
       sc_signal<size_t>   r_read_to_tgt_rsp_length; // length of the response
-      sc_signal<typename vci_param::fast_addr_t>
-                          r_read_to_tgt_rsp_ll_key; // LL key returned by the llsc_global_table
+      sc_signal<addr_t>   r_read_to_tgt_rsp_ll_key; // LL key from the llsc_global_table
 
       ///////////////////////////////////////////////////////////////
@@ -578,4 +578,5 @@
       GenericFifo<bool>   m_write_to_cc_send_inst_fifo;     // fifo for the L1 type
       GenericFifo<size_t> m_write_to_cc_send_srcid_fifo;    // fifo for srcids
+
 #if L1_MULTI_CACHE
       GenericFifo<size_t> m_write_to_cc_send_cache_id_fifo; // fifo for srcids
@@ -703,4 +704,5 @@
       GenericFifo<bool>   m_cas_to_cc_send_inst_fifo;     // fifo for the L1 type
       GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo;    // fifo for srcids
+
 #if L1_MULTI_CACHE
       GenericFifo<size_t> m_cas_to_cc_send_cache_id_fifo; // fifo for srcids
@@ -749,6 +751,5 @@
       sc_signal<size_t>   r_xram_rsp_to_tgt_rsp_length; // length of the response
       sc_signal<bool>     r_xram_rsp_to_tgt_rsp_rerror; // send error to requester
-      sc_signal<typename vci_param::fast_addr_t>
-                          r_xram_rsp_to_tgt_rsp_ll_key; // LL key returned by the llsc_global_table
+      sc_signal<addr_t>   r_xram_rsp_to_tgt_rsp_ll_key; // LL key from llsc_global_table
 
       // Buffer between XRAM_RSP fsm and CC_SEND fsm (Inval L1 Caches)
@@ -759,4 +760,5 @@
       GenericFifo<bool>   m_xram_rsp_to_cc_send_inst_fifo;     // fifo for the L1 type
       GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo;    // fifo for srcids
+
 #if L1_MULTI_CACHE
       GenericFifo<size_t> m_xram_rsp_to_cc_send_cache_id_fifo; // fifo for srcids
Index: trunk/modules/vci_mem_cache/caba/source/include/xram_transaction.h
===================================================================
--- trunk/modules/vci_mem_cache/caba/source/include/xram_transaction.h	(revision 377)
+++ trunk/modules/vci_mem_cache/caba/source/include/xram_transaction.h	(revision 385)
@@ -14,7 +14,7 @@
 
 class TransactionTabEntry {
-    typedef uint32_t              size_t;
+    typedef sc_dt::sc_uint<64>    wide_data_t;
+    typedef sc_dt::sc_uint<40>    addr_t;
     typedef uint32_t              data_t;
-    typedef sc_dt::sc_uint<40>    addr_t;
     typedef uint32_t              be_t;
 
@@ -138,8 +138,8 @@
 ////////////////////////////////////////////////////////////////////////
 class TransactionTab{
-    typedef uint32_t size_t;
-    typedef uint32_t data_t;
-    typedef sc_dt::sc_uint<40> addr_t;
-    typedef uint32_t be_t;
+    typedef sc_dt::sc_uint<64>    wide_data_t;
+    typedef sc_dt::sc_uint<40>    addr_t;
+    typedef uint32_t              data_t;
+    typedef uint32_t              be_t;
 
     private:
@@ -368,18 +368,21 @@
 
     /////////////////////////////////////////////////////////////////////
-    // The write_rsp() function writes a word of the response to an 
-    // XRAM read transaction.
+    // The write_rsp() function writes two 32 bits words of the response 
+    // to a XRAM read transaction.
     // The BE field in TRT is taken into account.
     // Arguments :
     // - index : the index of the transaction in the transaction tab
     // - word_index : the index of the data in the line
-    // - data : the data to write
+    // - data : a 64 bits value
     // - error : invalid data
     /////////////////////////////////////////////////////////////////////
-    void write_rsp(const size_t index,
-            const size_t word,
-            const data_t data,
-            const bool   rerror)
-    {
+    void write_rsp(const size_t      index,
+                   const size_t      word,
+                   const wide_data_t data,
+                   const bool        rerror)
+    {
+        data_t  value;
+        data_t  mask;
+
         assert( (index < size_tab) 
                 && "Selected entry  out of range in write_rsp() Transaction Tab");
@@ -391,6 +394,15 @@
                 && "Selected entry is not an XRAM read transaction in write_rsp()");
 
-        data_t mask = be_to_mask(tab[index].wdata_be[word]);
-        tab[index].wdata[word] = (tab[index].wdata[word] & mask) | (data & ~mask);
+        // first 32 bits word
+        value = (data_t)data;
+        mask  = be_to_mask(tab[index].wdata_be[word]);
+        tab[index].wdata[word] = (tab[index].wdata[word] & mask) | (value & ~mask);
+
+        // second 32 bits word
+        value = (data_t)(data>>32);
+        mask  = be_to_mask(tab[index].wdata_be[word+1]);
+        tab[index].wdata[word+1] = (tab[index].wdata[word+1] & mask) | (value & ~mask);
+
+        // error update
         tab[index].rerror |= rerror;
     }
