Ignore:
Timestamp:
May 1, 2013, 4:21:29 PM (11 years ago)
Author:
alain
Message:

New release supporting the tsar_generic_xbar platform
with 64 bits interface between MEMC & XCACHE, and preparing
support for the tsar_generic_iob platform.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp

    r384 r386  
    160160}
    161161
    162 #define tmpl(...)  template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapper<vci_param, iss_t>
     162#define tmpl(...) \
     163   template<typename vci_param, \
     164            size_t   dspin_in_width, \
     165            size_t   dspin_out_width, \
     166            typename iss_t> __VA_ARGS__ \
     167   VciCcVCacheWrapper<vci_param, dspin_in_width, dspin_out_width, iss_t>
    163168
    164169using namespace soclib::common;
     
    494499//////////////////////////////////////////
    495500{
    496     size_t      cache_way;
    497     size_t      cache_set;
    498     size_t      cache_word;
     501    size_t          cache_way;
     502    size_t          cache_set;
     503    size_t          cache_word;
    499504    uint32_t    cache_rdata;
    500     bool        cache_hit = r_dcache.read_neutral( addr,
    501                                            &cache_rdata,
    502                                            &cache_way,
    503                                            &cache_set,
    504                                            &cache_word );
     505    bool            cache_hit = r_dcache.read_neutral( addr,
     506                                                   &cache_rdata,
     507                                                   &cache_way,
     508                                                   &cache_set,
     509                                                   &cache_word );
    505510    bool        icache_hit = r_icache.read_neutral( addr,
    506511                                           &cache_rdata,
     
    11511156                    // we request a VCI transaction
    11521157                    r_icache_fsm      = ICACHE_MISS_SELECT;
    1153                     r_icache_miss_req = true;
     1158#if DEBUG_ICACHE
     1159if ( m_debug_icache_fsm )
     1160{
     1161    std::cout << "  <PROC " << name()
     1162              << " ICACHE_IDLE> READ MISS in icache"
     1163              << " : PADDR = " << std::hex << paddr << std::endl;
     1164}
     1165#endif
     1166                   r_icache_miss_req = true;
    11541167                }
    11551168                else if (cache_state == CACHE_SLOT_STATE_ZOMBI )        // pending cleanup
     
    11681181                    m_irsp.instruction = cache_inst;
    11691182                    r_icache_fsm       = ICACHE_IDLE;
     1183#if DEBUG_ICACHE
     1184if ( m_debug_icache_fsm )
     1185{
     1186    std::cout << "  <PROC " << name()
     1187              << " ICACHE_IDLE> READ HIT in icache"
     1188              << " : PADDR = " << std::hex << paddr << std::endl;
     1189}
     1190#endif
    11701191                }
    11711192            }
     
    11741195                r_icache_unc_req  = true;
    11751196                r_icache_fsm      = ICACHE_UNC_WAIT;
     1197
     1198#if DEBUG_ICACHE
     1199if ( m_debug_icache_fsm )
     1200{
     1201    std::cout << "  <PROC " << name()
     1202              << " ICACHE_IDLE> READ UNCACHEABLE in icache"
     1203              << " : PADDR = " << std::hex << paddr << std::endl;
     1204}
     1205#endif
    11761206            }
    11771207        }    // end if m_ireq.valid
     
    26042634{
    26052635    std::cout << "  <PROC " << name()
    2606               << ".DCACHE_IDLE> READ MISS in dcache" << std::endl;
     2636              << " DCACHE_IDLE> READ MISS in dcache"
     2637              << " : PADDR = " << std::hex << paddr << std::endl;
    26072638}
    26082639#endif
     
    26262657{
    26272658    std::cout << "  <PROC " << name()
    2628               << ".DCACHE_IDLE> READ HIT in dcache" << std::endl;
     2659              << " DCACHE_IDLE> READ HIT in dcache"
     2660              << " : PADDR = " << std::hex << paddr << std::endl;
    26292661}
    26302662#endif
     
    26412673{
    26422674    std::cout << "  <PROC " << name()
    2643               << ".DCACHE_IDLE> READ UNCACHEABLE in dcache" << std::endl;
     2675              << " DCACHE_IDLE> READ UNCACHEABLE in dcache"
     2676              << " : PADDR = " << std::hex << paddr << std::endl;
    26442677}
    26452678#endif
     
    31853218{
    31863219    std::cout << "  <PROC " << name()
    3187               << " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped"
     3220              << " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE unmapped"
    31883221              << " PTE_FLAGS = " << std::hex << pte_flags
    31893222              << " PTE_PPN = " << std::hex << pte_ppn << std::endl;
     
    32043237if ( m_debug_dcache_fsm )
    32053238{
    3206     std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE2_GET> HIT in dcache:"
     3239    std::cout << "  <PROC " << name()
     3240              << " DCACHE_TLB_PTE2_GET> HIT in dcache:"
    32073241              << " PTE_FLAGS = " << std::hex << pte_flags
    32083242              << " PTE_PPN = " << std::hex << pte_ppn << std::endl;
     
    32153249            // stalled until cleanup is acknowledged
    32163250            r_dcache_fsm   = DCACHE_TLB_PTE2_GET;
     3251
     3252#if DEBUG_DCACHE
     3253if ( m_debug_dcache_fsm )
     3254{
     3255    std::cout << "  <PROC " << name()
     3256              << " DCACHE_TLB_PTE2_GET> ZOMBI in dcache: waiting cleanup ack"
     3257              << std::endl;
     3258}
     3259#endif
    32173260        }
    32183261        else            // we must load the missing cache line in dcache
     
    40154058    std::cout << "  <PROC " << name()
    40164059              << " DCACHE_MISS_DATA_UPDT> Write one word:"
    4017               << " / DATA = "  << r_vci_rsp_fifo_dcache.read()
     4060              << " / DATA = "  << std::hex << r_vci_rsp_fifo_dcache.read()
    40184061              << " / WAY = "   << std::dec << r_dcache_miss_way.read()
    40194062              << " / SET = "   << r_dcache_miss_set.read()
     
    41044147              << " / SET = "   << r_dcache_miss_set.read() << std::endl;
    41054148
    4106     r_dcache.printTrace();
     4149//    r_dcache.printTrace();
    41074150
    41084151
     
    52595302            // we first check for the last client and listen for //
    52605303            // a request of the other, then update the client    //
     5304            // r_cc_send_last_client : 0 dcache / 1 icache
    52615305            ///////////////////////////////////////////////////////
    5262             // r_cc_send_last_client : 0 dcache / 1 icache
    52635306            bool update_last_client = r_cc_send_last_client.read();
    52645307            if ( r_cc_send_last_client.read() == 0 ) // last client was dcache
     
    52775320            if (r_dcache_cc_send_req.read() or r_icache_cc_send_req.read())
    52785321            {
    5279                 // test if the new client is dcache and has a cleanup request
    5280                 if ( (update_last_client == 0) and (r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP))
     5322                // the new client is dcache and has a cleanup request
     5323                if      ( (update_last_client == 0) and
     5324                          (r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP))
    52815325                    r_cc_send_fsm = CC_SEND_CLEANUP_1;
    5282                 // test if the new client is dcache and has a multi acknowledgement request
    5283                 else if ( (update_last_client == 0) and (r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
     5326                // the new client is dcache and has a multi acknowledgement request
     5327                else if ( (update_last_client == 0) and
     5328                          (r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
    52845329                    r_cc_send_fsm = CC_SEND_MULTI_ACK;
    5285                 // test if the new client is icache and has a cleanup request
    5286                 else if ( (update_last_client == 1) and (r_icache_cc_send_type.read() == CC_TYPE_CLEANUP))
     5330                // the new client is icache and has a cleanup request
     5331                else if ( (update_last_client == 1) and
     5332                          (r_icache_cc_send_type.read() == CC_TYPE_CLEANUP))
    52875333                    r_cc_send_fsm = CC_SEND_CLEANUP_1;
    5288                 // test if the new client is icache and has a multi acknowledgement request
    5289                 else if ( (update_last_client == 1) and (r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
     5334                // the new client is icache and has a multi acknowledgement request
     5335                else if ( (update_last_client == 1) and
     5336                        (r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
    52905337                    r_cc_send_fsm = CC_SEND_MULTI_ACK;
    52915338            }
     
    53575404                uint64_t receive_data = p_dspin_in.data.read();
    53585405                // initialize coherence packet type
    5359                 uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_TYPE);
     5406                uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data,
     5407                                            DspinDhccpParam::FROM_MC_TYPE);
    53605408                // initialize data/ins flip_flop (0 data / 1 ins)
    53615409                r_cc_receive_data_ins = (bool)(receive_type & 0x1);
     
    53925440
    53935441            // for data CLACK, wait for dcache to take the request
    5394             if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
     5442            if ((r_cc_receive_data_ins.read() == 0) and
     5443                   not (r_cc_receive_dcache_req.read()))
    53955444            {
    53965445                // request dcache to handle the CLACK
    53975446                r_cc_receive_dcache_req  = true;
    5398                 r_cc_receive_dcache_set  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_SET) & ((1ULL<<(uint32_log2(m_dcache_sets)))-1);
    5399                 r_cc_receive_dcache_way  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_WAY) & ((1ULL<<(uint32_log2(m_dcache_ways)))-1);
     5447                r_cc_receive_dcache_set  = DspinDhccpParam::dspin_get(receive_data,
     5448                                           DspinDhccpParam::CLEANUP_ACK_SET) &
     5449                                           ((1ULL<<(uint32_log2(m_dcache_sets)))-1);
     5450                r_cc_receive_dcache_way  = DspinDhccpParam::dspin_get(receive_data,
     5451                                           DspinDhccpParam::CLEANUP_ACK_WAY) &
     5452                                           ((1ULL<<(uint32_log2(m_dcache_ways)))-1);
    54005453                r_cc_receive_dcache_type = CC_TYPE_CLACK;
    54015454                // get back to idle state
     
    54045457            }
    54055458            // for ins CLACK, wait for icache to take the request
    5406             if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
     5459            if ((r_cc_receive_data_ins.read() == 1) and
     5460                   not (r_cc_receive_icache_req.read()))
    54075461            {
    54085462                // request icache to handle the CLACK
    54095463                r_cc_receive_icache_req  = true;
    5410                 r_cc_receive_icache_set  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_SET) & ((1ULL<<(uint32_log2(m_icache_sets)))-1);
    5411                 r_cc_receive_icache_way  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_WAY) & ((1ULL<<(uint32_log2(m_icache_ways)))-1);
     5464                r_cc_receive_icache_set  = DspinDhccpParam::dspin_get(receive_data,
     5465                                           DspinDhccpParam::CLEANUP_ACK_SET) &
     5466                                           ((1ULL<<(uint32_log2(m_icache_sets)))-1);
     5467                r_cc_receive_icache_way  = DspinDhccpParam::dspin_get(receive_data,
     5468                                           DspinDhccpParam::CLEANUP_ACK_WAY) &
     5469                                           ((1ULL<<(uint32_log2(m_icache_ways)))-1);
    54125470                r_cc_receive_icache_type = CC_TYPE_CLACK;
    54135471                // get back to idle state
     
    54345492            // not to actually post a request to an available cache => need a
    54355493            // flip_flop to check that ?
    5436             if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()) and (p_dspin_in.write.read()))
     5494            if (not (r_cc_receive_icache_req.read()) and
     5495                not (r_cc_receive_dcache_req.read()) and
     5496                (p_dspin_in.write.read()))
    54375497            {
    54385498                // request dcache to handle the BROADCAST
    54395499                r_cc_receive_dcache_req  = true;
    5440                 r_cc_receive_dcache_nline  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::BROADCAST_NLINE);
     5500                r_cc_receive_dcache_nline  = DspinDhccpParam::dspin_get(receive_data,
     5501                                             DspinDhccpParam::BROADCAST_NLINE);
    54415502                r_cc_receive_dcache_type = CC_TYPE_BRDCAST;
    54425503                // request icache to handle the BROADCAST
    54435504                r_cc_receive_icache_req  = true;
    5444                 r_cc_receive_icache_nline  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::BROADCAST_NLINE);
     5505                r_cc_receive_icache_nline  = DspinDhccpParam::dspin_get(receive_data,
     5506                                             DspinDhccpParam::BROADCAST_NLINE);
    54455507                r_cc_receive_icache_type = CC_TYPE_BRDCAST;
    54465508                // get back to idle state
     
    54575519            uint64_t receive_data = p_dspin_in.data.read();
    54585520            // for data INVAL, wait for dcache to take the request
    5459             if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
    5460             {
    5461                 r_cc_receive_dcache_updt_tab_idx  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
     5521            if ((r_cc_receive_data_ins.read() == 0) and
     5522                 not (r_cc_receive_dcache_req.read()))
     5523            {
     5524                r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,
     5525                                                   DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
    54625526                r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE;
    54635527                break;
    54645528            }
    54655529            // for ins INVAL, wait for icache to take the request
    5466             if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
    5467             {
    5468                 r_cc_receive_icache_updt_tab_idx  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
     5530            if ((r_cc_receive_data_ins.read() == 1) and
     5531                 not (r_cc_receive_icache_req.read()))
     5532            {
     5533                r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,
     5534                                                   DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
    54695535                r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE;
    54705536                break;
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