Index: trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
===================================================================
--- trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 384)
+++ trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 386)
@@ -55,5 +55,8 @@
 
 ////////////////////////////////////////////
-template<typename vci_param, typename iss_t>
+template<typename vci_param, 
+         size_t   dspin_in_width,
+         size_t   dspin_out_width,
+         typename iss_t>
 class VciCcVCacheWrapper
 ////////////////////////////////////////////
@@ -283,10 +286,10 @@
 
 public:
-    sc_in<bool>                             p_clk;
-    sc_in<bool>                             p_resetn;
-    sc_in<bool>                             p_irq[iss_t::n_irq];
-    soclib::caba::VciInitiator<vci_param>   p_vci;
-    soclib::caba::DspinInput <40>           p_dspin_in;
-    soclib::caba::DspinOutput<33>           p_dspin_out;
+    sc_in<bool>                                 p_clk;
+    sc_in<bool>                                 p_resetn;
+    sc_in<bool>                                 p_irq[iss_t::n_irq];
+    soclib::caba::VciInitiator<vci_param>       p_vci;
+    soclib::caba::DspinInput <dspin_in_width>   p_dspin_in;
+    soclib::caba::DspinOutput<dspin_out_width>  p_dspin_out;
 
 private:
Index: trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
===================================================================
--- trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 384)
+++ trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 386)
@@ -160,5 +160,10 @@
 }
 
-#define tmpl(...)  template<typename vci_param, typename iss_t> __VA_ARGS__ VciCcVCacheWrapper<vci_param, iss_t>
+#define tmpl(...) \
+   template<typename vci_param, \
+            size_t   dspin_in_width, \
+            size_t   dspin_out_width, \
+            typename iss_t> __VA_ARGS__ \
+   VciCcVCacheWrapper<vci_param, dspin_in_width, dspin_out_width, iss_t>
 
 using namespace soclib::common;
@@ -494,13 +499,13 @@
 //////////////////////////////////////////
 {
-    size_t	cache_way;
-    size_t	cache_set;
-    size_t	cache_word;
+    size_t	    cache_way;
+    size_t	    cache_set;
+    size_t	    cache_word;
     uint32_t	cache_rdata;
-    bool	cache_hit = r_dcache.read_neutral( addr,
-                                           &cache_rdata,
-                                           &cache_way,
-                                           &cache_set,
-                                           &cache_word );
+    bool	    cache_hit = r_dcache.read_neutral( addr,
+                                                   &cache_rdata,
+                                                   &cache_way,
+                                                   &cache_set,
+                                                   &cache_word );
     bool	icache_hit = r_icache.read_neutral( addr,
                                            &cache_rdata,
@@ -1151,5 +1156,13 @@
                     // we request a VCI transaction
                     r_icache_fsm      = ICACHE_MISS_SELECT;
-                    r_icache_miss_req = true;
+#if DEBUG_ICACHE
+if ( m_debug_icache_fsm )
+{
+    std::cout << "  <PROC " << name()
+              << " ICACHE_IDLE> READ MISS in icache" 
+              << " : PADDR = " << std::hex << paddr << std::endl;
+}
+#endif
+                   r_icache_miss_req = true;
                 }
                 else if (cache_state == CACHE_SLOT_STATE_ZOMBI )	// pending cleanup
@@ -1168,4 +1181,12 @@
                     m_irsp.instruction = cache_inst;
                     r_icache_fsm       = ICACHE_IDLE;
+#if DEBUG_ICACHE
+if ( m_debug_icache_fsm )
+{
+    std::cout << "  <PROC " << name()
+              << " ICACHE_IDLE> READ HIT in icache" 
+              << " : PADDR = " << std::hex << paddr << std::endl;
+}
+#endif
                 }
             }
@@ -1174,4 +1195,13 @@
                 r_icache_unc_req  = true;
                 r_icache_fsm      = ICACHE_UNC_WAIT;
+
+#if DEBUG_ICACHE
+if ( m_debug_icache_fsm )
+{
+    std::cout << "  <PROC " << name()
+              << " ICACHE_IDLE> READ UNCACHEABLE in icache" 
+              << " : PADDR = " << std::hex << paddr << std::endl;
+}
+#endif
             }
         }    // end if m_ireq.valid
@@ -2604,5 +2634,6 @@
 {
     std::cout << "  <PROC " << name()
-              << ".DCACHE_IDLE> READ MISS in dcache" << std::endl;
+              << " DCACHE_IDLE> READ MISS in dcache" 
+              << " : PADDR = " << std::hex << paddr << std::endl;
 }
 #endif
@@ -2626,5 +2657,6 @@
 {
     std::cout << "  <PROC " << name()
-              << ".DCACHE_IDLE> READ HIT in dcache" << std::endl;
+              << " DCACHE_IDLE> READ HIT in dcache" 
+              << " : PADDR = " << std::hex << paddr << std::endl;
 }
 #endif
@@ -2641,5 +2673,6 @@
 {
     std::cout << "  <PROC " << name()
-              << ".DCACHE_IDLE> READ UNCACHEABLE in dcache" << std::endl;
+              << " DCACHE_IDLE> READ UNCACHEABLE in dcache" 
+              << " : PADDR = " << std::hex << paddr << std::endl;
 }
 #endif
@@ -3185,5 +3218,5 @@
 {
     std::cout << "  <PROC " << name()
-              << " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE is unmapped"
+              << " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE unmapped"
               << " PTE_FLAGS = " << std::hex << pte_flags
               << " PTE_PPN = " << std::hex << pte_ppn << std::endl;
@@ -3204,5 +3237,6 @@
 if ( m_debug_dcache_fsm )
 {
-    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE2_GET> HIT in dcache:"
+    std::cout << "  <PROC " << name() 
+              << " DCACHE_TLB_PTE2_GET> HIT in dcache:"
               << " PTE_FLAGS = " << std::hex << pte_flags
               << " PTE_PPN = " << std::hex << pte_ppn << std::endl;
@@ -3215,4 +3249,13 @@
             // stalled until cleanup is acknowledged
             r_dcache_fsm   = DCACHE_TLB_PTE2_GET;
+
+#if DEBUG_DCACHE
+if ( m_debug_dcache_fsm )
+{
+    std::cout << "  <PROC " << name() 
+              << " DCACHE_TLB_PTE2_GET> ZOMBI in dcache: waiting cleanup ack"
+              << std::endl;
+}
+#endif
         }
         else            // we must load the missing cache line in dcache
@@ -4015,5 +4058,5 @@
     std::cout << "  <PROC " << name()
               << " DCACHE_MISS_DATA_UPDT> Write one word:"
-              << " / DATA = "  << r_vci_rsp_fifo_dcache.read()
+              << " / DATA = "  << std::hex << r_vci_rsp_fifo_dcache.read()
               << " / WAY = "   << std::dec << r_dcache_miss_way.read()
               << " / SET = "   << r_dcache_miss_set.read()
@@ -4104,5 +4147,5 @@
               << " / SET = "   << r_dcache_miss_set.read() << std::endl;
 
-    r_dcache.printTrace();
+//    r_dcache.printTrace();
 
 
@@ -5259,6 +5302,6 @@
             // we first check for the last client and listen for //
             // a request of the other, then update the client    //
+            // r_cc_send_last_client : 0 dcache / 1 icache
             ///////////////////////////////////////////////////////
-            // r_cc_send_last_client : 0 dcache / 1 icache
             bool update_last_client = r_cc_send_last_client.read();
             if ( r_cc_send_last_client.read() == 0 ) // last client was dcache
@@ -5277,15 +5320,19 @@
             if (r_dcache_cc_send_req.read() or r_icache_cc_send_req.read())
             {
-                // test if the new client is dcache and has a cleanup request
-                if ( (update_last_client == 0) and (r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP))
+                // the new client is dcache and has a cleanup request
+                if      ( (update_last_client == 0) and 
+                          (r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP))
                     r_cc_send_fsm = CC_SEND_CLEANUP_1;
-                // test if the new client is dcache and has a multi acknowledgement request
-                else if ( (update_last_client == 0) and (r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
+                // the new client is dcache and has a multi acknowledgement request
+                else if ( (update_last_client == 0) and 
+                          (r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
                     r_cc_send_fsm = CC_SEND_MULTI_ACK;
-                // test if the new client is icache and has a cleanup request
-                else if ( (update_last_client == 1) and (r_icache_cc_send_type.read() == CC_TYPE_CLEANUP))
+                // the new client is icache and has a cleanup request
+                else if ( (update_last_client == 1) and 
+                          (r_icache_cc_send_type.read() == CC_TYPE_CLEANUP))
                     r_cc_send_fsm = CC_SEND_CLEANUP_1;
-                // test if the new client is icache and has a multi acknowledgement request
-                else if ( (update_last_client == 1) and (r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
+                // the new client is icache and has a multi acknowledgement request
+                else if ( (update_last_client == 1) and
+                        (r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
                     r_cc_send_fsm = CC_SEND_MULTI_ACK;
             }
@@ -5357,5 +5404,6 @@
                 uint64_t receive_data = p_dspin_in.data.read();
                 // initialize coherence packet type
-                uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::FROM_MC_TYPE);
+                uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data,
+                                            DspinDhccpParam::FROM_MC_TYPE);
                 // initialize data/ins flip_flop (0 data / 1 ins)
                 r_cc_receive_data_ins = (bool)(receive_type & 0x1);
@@ -5392,10 +5440,15 @@
 
             // for data CLACK, wait for dcache to take the request
-            if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
+            if ((r_cc_receive_data_ins.read() == 0) and 
+                   not (r_cc_receive_dcache_req.read()))
             {
                 // request dcache to handle the CLACK
                 r_cc_receive_dcache_req  = true;
-                r_cc_receive_dcache_set  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_SET) & ((1ULL<<(uint32_log2(m_dcache_sets)))-1);
-                r_cc_receive_dcache_way  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_WAY) & ((1ULL<<(uint32_log2(m_dcache_ways)))-1);
+                r_cc_receive_dcache_set  = DspinDhccpParam::dspin_get(receive_data,
+                                           DspinDhccpParam::CLEANUP_ACK_SET) & 
+                                           ((1ULL<<(uint32_log2(m_dcache_sets)))-1);
+                r_cc_receive_dcache_way  = DspinDhccpParam::dspin_get(receive_data,
+                                           DspinDhccpParam::CLEANUP_ACK_WAY) & 
+                                           ((1ULL<<(uint32_log2(m_dcache_ways)))-1);
                 r_cc_receive_dcache_type = CC_TYPE_CLACK;
                 // get back to idle state
@@ -5404,10 +5457,15 @@
             }
             // for ins CLACK, wait for icache to take the request
-            if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
+            if ((r_cc_receive_data_ins.read() == 1) and 
+                   not (r_cc_receive_icache_req.read()))
             {
                 // request icache to handle the CLACK
                 r_cc_receive_icache_req  = true;
-                r_cc_receive_icache_set  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_SET) & ((1ULL<<(uint32_log2(m_icache_sets)))-1);
-                r_cc_receive_icache_way  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::CLEANUP_ACK_WAY) & ((1ULL<<(uint32_log2(m_icache_ways)))-1);
+                r_cc_receive_icache_set  = DspinDhccpParam::dspin_get(receive_data,
+                                           DspinDhccpParam::CLEANUP_ACK_SET) & 
+                                           ((1ULL<<(uint32_log2(m_icache_sets)))-1);
+                r_cc_receive_icache_way  = DspinDhccpParam::dspin_get(receive_data,
+                                           DspinDhccpParam::CLEANUP_ACK_WAY) & 
+                                           ((1ULL<<(uint32_log2(m_icache_ways)))-1);
                 r_cc_receive_icache_type = CC_TYPE_CLACK;
                 // get back to idle state
@@ -5434,13 +5492,17 @@
             // not to actually post a request to an available cache => need a
             // flip_flop to check that ?
-            if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()) and (p_dspin_in.write.read()))
+            if (not (r_cc_receive_icache_req.read()) and 
+                not (r_cc_receive_dcache_req.read()) and 
+                (p_dspin_in.write.read()))
             {
                 // request dcache to handle the BROADCAST
                 r_cc_receive_dcache_req  = true;
-                r_cc_receive_dcache_nline  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::BROADCAST_NLINE);
+                r_cc_receive_dcache_nline  = DspinDhccpParam::dspin_get(receive_data,
+                                             DspinDhccpParam::BROADCAST_NLINE);
                 r_cc_receive_dcache_type = CC_TYPE_BRDCAST;
                 // request icache to handle the BROADCAST
                 r_cc_receive_icache_req  = true;
-                r_cc_receive_icache_nline  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::BROADCAST_NLINE);
+                r_cc_receive_icache_nline  = DspinDhccpParam::dspin_get(receive_data,
+                                             DspinDhccpParam::BROADCAST_NLINE);
                 r_cc_receive_icache_type = CC_TYPE_BRDCAST;
                 // get back to idle state
@@ -5457,14 +5519,18 @@
             uint64_t receive_data = p_dspin_in.data.read();
             // for data INVAL, wait for dcache to take the request
-            if ((r_cc_receive_data_ins.read() == 0) and not (r_cc_receive_dcache_req.read()))
-            {
-                r_cc_receive_dcache_updt_tab_idx  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
+            if ((r_cc_receive_data_ins.read() == 0) and 
+                 not (r_cc_receive_dcache_req.read()))
+            {
+                r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,
+                                                   DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
                 r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE;
                 break;
             }
             // for ins INVAL, wait for icache to take the request
-            if ((r_cc_receive_data_ins.read() == 1) and not (r_cc_receive_icache_req.read()))
-            {
-                r_cc_receive_icache_updt_tab_idx  = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
+            if ((r_cc_receive_data_ins.read() == 1) and 
+                 not (r_cc_receive_icache_req.read()))
+            {
+                r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,
+                                                   DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
                 r_cc_receive_fsm = CC_RECEIVE_INVAL_NLINE;
                 break;
