Index: trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
===================================================================
--- trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 387)
+++ trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 394)
@@ -34,5 +34,5 @@
 #define DEBUG_DCACHE		1
 #define DEBUG_ICACHE		1
-#define DEBUG_CLEANUP		1
+#define DEBUG_CMD   		0
 
 namespace soclib {
@@ -464,5 +464,6 @@
               << " | " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
               << " | " << cc_receive_fsm_state_str[r_cc_receive_fsm.read()]
-              << " | " << cc_send_fsm_state_str[r_cc_send_fsm.read()];
+              << " | " << cc_send_fsm_state_str[r_cc_send_fsm.read()]
+              << " | MMU = " << r_mmu_mode.read();
     if (r_dcache_updt_req.read() ) std::cout << " | P1_UPDT";
     if (r_dcache_wbuf_req.read() ) std::cout << " | P1_WBUF";
@@ -499,33 +500,42 @@
 //////////////////////////////////////////
 {
-    size_t	    cache_way;
-    size_t	    cache_set;
-    size_t	    cache_word;
-    uint32_t	cache_rdata;
-    bool	    cache_hit = r_dcache.read_neutral( addr,
-                                                   &cache_rdata,
-                                                   &cache_way,
-                                                   &cache_set,
-                                                   &cache_word );
-    bool	icache_hit = r_icache.read_neutral( addr,
-                                           &cache_rdata,
-                                           &cache_way,
-                                           &cache_set,
-                                           &cache_word );
-    if ( cache_hit != m_debug_previous_hit )
-    {
-        std::cout << "PROC " << name()
-                  << " dcache change at cycle " << std::dec << m_cpt_total_cycles
-                  << " for adresse " << std::hex << addr
-                  << " / HIT = " << std::dec << cache_hit << std::endl;
-	m_debug_previous_hit = cache_hit;
-    }
-    if ( icache_hit != m_idebug_previous_hit )
-    {
-        std::cout << "PROC " << name()
-                  << " icache change at cycle " << std::dec << m_cpt_total_cycles
-                  << " for adresse " << std::hex << addr
-                  << " / HIT = " << icache_hit << std::endl;
-	m_idebug_previous_hit = icache_hit;
+    bool        cache_hit;
+    size_t	    cache_way = 0;
+    size_t	    cache_set = 0;
+    size_t	    cache_word = 0;
+    uint32_t	cache_rdata = 0;
+
+    cache_hit = r_dcache.read_neutral( addr,
+                                       &cache_rdata,
+                                       &cache_way,
+                                       &cache_set,
+                                       &cache_word );
+
+    if ( cache_hit != m_debug_previous_d_hit )
+    {
+        std::cout << "Monitor PROC " << name()
+                  << " DCACHE at cycle " << std::dec << m_cpt_total_cycles
+                  << " / HIT = " << cache_hit 
+                  << " / PADDR = " << std::hex << addr
+                  << " / DATA = " << cache_rdata 
+                  << " / WAY = " << cache_way << std::endl;
+	    m_debug_previous_d_hit = cache_hit;
+    }
+
+    cache_hit = r_icache.read_neutral( addr,
+                                       &cache_rdata,
+                                       &cache_way,
+                                       &cache_set,
+                                       &cache_word );
+
+    if ( cache_hit != m_debug_previous_i_hit )
+    {
+        std::cout << "Monitor PROC " << name()
+                  << " ICACHE at cycle " << std::dec << m_cpt_total_cycles
+                  << " / HIT = " << cache_hit 
+                  << " / PADDR = " << std::hex << addr
+                  << " / DATA = " << cache_rdata 
+                  << " / WAY = " << cache_way << std::endl;
+	    m_debug_previous_i_hit = cache_hit;
     }
 }
@@ -681,5 +691,4 @@
 /////////////////////////
 {
-    #define LLSCLocalTable GenericLLSCLocalTable<8000, 1, paddr_t, vci_trdid_t, vci_data_t>
     if ( not p_resetn.read() )
     {
@@ -698,4 +707,7 @@
         r_cc_send_fsm     = CC_SEND_IDLE;
 
+        // reset data physical address extension
+        r_dcache_paddr_ext = 0;
+
         // reset dcache directory extension
         for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++)
@@ -710,4 +722,5 @@
 
         // ICACHE & DCACHE activated
+        // ITLB & DTLB desactivated
         r_mmu_mode = 0x3;
 
@@ -762,8 +775,7 @@
 
         // Debug variables
-        m_debug_previous_hit       = false;
-        m_idebug_previous_hit      = false;
-        m_debug_dcache_fsm	       = false;
-        m_debug_icache_fsm	       = false;
+        m_debug_previous_i_hit     = false;
+        m_debug_previous_d_hit     = false;
+        m_debug_activated	       = false;
 
         // activity counters
@@ -905,6 +917,5 @@
     m_cpt_total_cycles++;
 
-    m_debug_icache_fsm     = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
-    m_debug_dcache_fsm     = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
+    m_debug_activated = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok;
 
     /////////////////////////////////////////////////////////////////////
@@ -1157,10 +1168,7 @@
                     r_icache_fsm      = ICACHE_MISS_SELECT;
 #if DEBUG_ICACHE
-if ( m_debug_icache_fsm )
-{
-    std::cout << "  <PROC " << name()
-              << " ICACHE_IDLE> READ MISS in icache" 
-              << " : PADDR = " << std::hex << paddr << std::endl;
-}
+if ( m_debug_activated )
+std::cout << "  <PROC " << name() << " ICACHE_IDLE> READ MISS in icache" 
+          << " : PADDR = " << std::hex << paddr << std::endl;
 #endif
                    r_icache_miss_req = true;
@@ -1182,10 +1190,7 @@
                     r_icache_fsm       = ICACHE_IDLE;
 #if DEBUG_ICACHE
-if ( m_debug_icache_fsm )
-{
-    std::cout << "  <PROC " << name()
-              << " ICACHE_IDLE> READ HIT in icache" 
-              << " : PADDR = " << std::hex << paddr << std::endl;
-}
+if ( m_debug_activated )
+std::cout << "  <PROC " << name() << " ICACHE_IDLE> READ HIT in icache" 
+          << " : PADDR = " << std::hex << paddr << std::endl;
 #endif
                 }
@@ -1197,5 +1202,5 @@
 
 #if DEBUG_ICACHE
-if ( m_debug_icache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -1271,5 +1276,5 @@
         {
             int       state;
-            uint32_t  tag;
+            paddr_t   tag;
             size_t	  way = r_icache_flush_count.read()/m_icache_sets;
             size_t	  set = r_icache_flush_count.read()%m_icache_sets;
@@ -1505,5 +1510,5 @@
 
 #if DEBUG_ICACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -1531,5 +1536,5 @@
                             CACHE_SLOT_STATE_ZOMBI);
 #if DEBUG_ICACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -1588,5 +1593,5 @@
                             r_vci_rsp_fifo_icache.read() );
 #if DEBUG_ICACHE
-if ( m_debug_icache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -1648,5 +1653,5 @@
                                         CACHE_SLOT_STATE_ZOMBI );
 #if DEBUG_ICACHE
-if ( m_debug_icache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -1672,5 +1677,5 @@
                                     CACHE_SLOT_STATE_VALID );
 #if DEBUG_ICACHE
-if ( m_debug_icache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -1754,5 +1759,5 @@
 
 #if DEBUG_ICACHE
-if ( m_debug_icache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -1787,5 +1792,5 @@
             }
 #if DEBUG_ICACHE
-if ( m_debug_icache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -1856,5 +1861,5 @@
 
 #if DEBUG_ICACHE
-if ( m_debug_icache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -1900,5 +1905,5 @@
 
 #if DEBUG_ICACHE
-if ( m_debug_icache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -1963,5 +1968,5 @@
 
 #if DEBUG_ICACHE
-if ( m_debug_icache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -2153,5 +2158,8 @@
             else                                    // identity mapping
             {
-                paddr       = (paddr_t)m_dreq.addr;
+                paddr = (paddr_t)m_dreq.addr;
+                // we take into account the paddr extension
+                if (vci_param::N > 32) 
+                    paddr = paddr | ((paddr_t)(r_dcache_paddr_ext.read()) << 32);
             }
         } // end physical address computation
@@ -2227,14 +2235,12 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_IDLE> Cache update in P1 stage" << std::dec
-              << " / WAY = " << r_dcache_save_cache_way.read()
-              << " / SET = " << r_dcache_save_cache_set.read()
-              << " / WORD = " << r_dcache_save_cache_word.read() << std::hex
-              << " / DATA = " << r_dcache_save_wdata.read()
-              << " / BE = " << r_dcache_save_be.read() << std::endl;
-}
+if ( m_debug_activated )
+std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
+          << " Cache update in P1 stage" << std::dec
+          << " / WAY = " << r_dcache_save_cache_way.read()
+          << " / SET = " << r_dcache_save_cache_set.read()
+          << " / WORD = " << r_dcache_save_cache_word.read() << std::hex
+          << " / WDATA = " << r_dcache_save_wdata.read()
+          << " / BE = " << r_dcache_save_be.read() << std::endl;
 #endif
         } // end test TLB inval
@@ -2379,4 +2385,10 @@
                     case iss_t::XTN_MMU_WORD_HI:
                         m_drsp.rdata = r_mmu_word_hi.read();
+                        m_drsp.valid = true;
+                        m_drsp.error = false;
+                        break;
+
+                    case iss_t::XTN_DATA_PADDR_EXT:
+                        m_drsp.rdata = r_dcache_paddr_ext.read();
                         m_drsp.valid = true;
                         m_drsp.error = false;
@@ -2503,4 +2515,10 @@
                         m_drsp.valid     = true;
                         r_dcache_fsm     = DCACHE_IDLE;
+                    break;
+
+                    case iss_t::XTN_DATA_PADDR_EXT:     // no cache or tlb access
+                        r_dcache_paddr_ext = m_dreq.wdata;
+                        m_drsp.valid       = true;
+                        r_dcache_fsm       = DCACHE_IDLE;
                     break;
 
@@ -2568,9 +2586,7 @@
                             m_drsp.rdata = 0;
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
-{
-    std::cout << "  <PROC " << name()
-              << ".DCACHE_IDLE> HIT in dtlb, but privilege violation" << std::endl;
-}
+if ( m_debug_activated )
+std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
+          << " HIT in dtlb, but privilege violation" << std::endl;
 #endif
                         }
@@ -2586,9 +2602,7 @@
                             m_drsp.rdata = 0;
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
-{
-    std::cout << "  <PROC " << name()
-              << ".DCACHE_IDLE> HIT in dtlb, but writable violation" << std::endl;
-}
+if ( m_debug_activated )
+std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
+          << " HIT in dtlb, but writable violation" << std::endl;
 #endif
                         }
@@ -2607,5 +2621,5 @@
                 }    // end DTLB activated
 
-                if ( valid_req ) 	// processor request is valid after TLB check
+                if ( valid_req ) 	// processor request is valid (after MMU check)
                 {
                     r_dcache_save_cacheable  = cacheable;
@@ -2631,10 +2645,8 @@
                                 r_dcache_fsm          = DCACHE_MISS_SELECT;
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_IDLE> READ MISS in dcache" 
-              << " : PADDR = " << std::hex << paddr << std::endl;
-}
+if ( m_debug_activated )
+std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
+          << " READ MISS in dcache" 
+          << " / PADDR = " << std::hex << paddr << std::endl;
 #endif
                             }
@@ -2643,4 +2655,10 @@
                                 // stalled until cleanup is acknowledged
                                 r_dcache_fsm   = DCACHE_IDLE;
+#if DEBUG_DCACHE
+if ( m_debug_activated )
+std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
+          << " Pending cleanup, stalled until cleanup acknowledge"
+          << " / PADDR = " << std::hex << paddr << std::endl;
+#endif
                             }
                             else                                      // cache hit
@@ -2654,10 +2672,8 @@
                                 m_drsp.rdata   = cache_rdata;
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_IDLE> READ HIT in dcache" 
-              << " : PADDR = " << std::hex << paddr << std::endl;
-}
+if ( m_debug_activated )
+std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
+          << " READ HIT in dcache" 
+          << " / PADDR = " << std::hex << paddr << std::endl;
 #endif
                             }
@@ -2670,10 +2686,8 @@
                             r_dcache_fsm          = DCACHE_UNC_WAIT;
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_IDLE> READ UNCACHEABLE in dcache" 
-              << " : PADDR = " << std::hex << paddr << std::endl;
-}
+if ( m_debug_activated )
+std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
+          << " READ UNCACHEABLE in dcache" 
+          << " / PADDR = " << std::hex << paddr << std::endl;
 #endif
                         }
@@ -2845,6 +2859,6 @@
         if ( not bypass )     // Try to read PTE1/PTD1 in dcache
         {
-            pte_paddr = (paddr_t)r_mmu_ptpr.read() << (INDEX1_NBITS+2) |
-                        (paddr_t)((r_dcache_tlb_vaddr.read() >> PAGE_M_NBITS) << 2);
+            pte_paddr = (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2)) |
+                        ((((paddr_t)r_dcache_tlb_vaddr.read()) >> PAGE_M_NBITS) << 2);
             r_dcache_tlb_paddr = pte_paddr;
             r_dcache_fsm       = DCACHE_TLB_PTE1_GET;
@@ -2859,15 +2873,12 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     if ( r_dcache_tlb_ins.read() )
-    {
-        std::cout << "  <PROC " << name() << ".DCACHE_TLB_MISS> ITLB miss";
-    }
+        std::cout << "  <PROC " << name() << " DCACHE_TLB_MISS> ITLB miss";
     else
-    {
-        std::cout << "  <PROC " << name() << ".DCACHE_TLB_MISS> DTLB miss";
-    }
+        std::cout << "  <PROC " << name() << " DCACHE_TLB_MISS> DTLB miss";
     std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
+              << " / ptpr  = " << (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2))
               << " / BYPASS = " << bypass
               << " / PTE_ADR = " << pte_paddr << std::endl;
@@ -2924,7 +2935,8 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
-    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
+    std::cout << "  <PROC " << name() 
+              << " DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
               << std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
               << std::dec << " / way = " << way
@@ -2960,7 +2972,8 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
-    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache"
+    std::cout << "  <PROC " << name() 
+              << " DCACHE_TLB_PTE1_GET> HIT in dcache"
               << std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
               << std::dec << " / way = " << way
@@ -2981,7 +2994,8 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
-    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_GET> HIT in dcache"
+    std::cout << "  <PROC " << name() 
+              << " DCACHE_TLB_PTE1_GET> HIT in dcache"
               << std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
               << std::dec << " / way = " << way
@@ -3007,7 +3021,8 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
-    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_GET> MISS in dcache:"
+    std::cout << "  <PROC " << name() 
+              << " DCACHE_TLB_PTE1_GET> MISS in dcache:"
               << " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
 }
@@ -3047,10 +3062,12 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     if ( r_dcache_tlb_ins.read() )
-        std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
+        std::cout << "  <PROC " << name() 
+                  << " DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
     else
-        std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
+        std::cout << "  <PROC " << name() 
+                  << ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
         std::cout << " way = " << std::dec << way
                   << " / set = " << set << std::endl;
@@ -3117,8 +3134,9 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
-    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB";
-    std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
+    std::cout << "  <PROC " << name() 
+              << " DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB"
+              << " / set = " << std::dec << r_dcache_tlb_set.read()
               << " / way = " << r_dcache_tlb_way.read() << std::endl;
     r_itlb.printTrace();
@@ -3140,8 +3158,9 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
-    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB";
-    std::cout << " / set = " << std::dec << r_dcache_tlb_set.read()
+    std::cout << "  <PROC " << name() 
+              << " DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB"
+              << " / set = " << std::dec << r_dcache_tlb_set.read()
               << " / way = " << r_dcache_tlb_way.read() << std::endl;
     r_dtlb.printTrace();
@@ -3156,7 +3175,8 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
-    std::cout << "  <PROC " << name() << ".DCACHE_TLB_PTE1_UPDT> L/R bit update required"
+    std::cout << "  <PROC " << name() 
+              << " DCACHE_TLB_PTE1_UPDT> L/R bit update required"
               << std::endl;
 }
@@ -3215,5 +3235,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -3235,5 +3255,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name() 
@@ -3251,5 +3271,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name() 
@@ -3268,5 +3288,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -3306,5 +3326,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     if ( r_dcache_tlb_ins.read() )
@@ -3382,5 +3402,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -3406,5 +3426,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -3424,5 +3444,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -3437,5 +3457,5 @@
     {
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -3482,5 +3502,5 @@
 	{
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -3497,5 +3517,5 @@
     {
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -3603,5 +3623,5 @@
         {
             int       state;
-            uint32_t  tag;
+            paddr_t   tag;
             size_t    way = r_dcache_flush_count.read()/m_dcache_sets;
             size_t    set = r_dcache_flush_count.read()%m_dcache_sets;
@@ -3723,5 +3743,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -3766,5 +3786,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -3826,5 +3846,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -3900,5 +3920,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -3907,5 +3927,5 @@
               << " / SET = "   << set
               << " / PADDR = " << std::hex << r_dcache_save_paddr.read();
-    if(cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
+    if(cleanup) std::cout << " / VICTIM = " << (victim*m_dcache_words*4) << std::endl;
     else        std::cout << std::endl;
 }
@@ -3923,5 +3943,4 @@
         size_t  way   = r_dcache_miss_way.read();
         size_t  set   = r_dcache_miss_set.read();
-        paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words<<2);
 
 #ifdef INSTRUMENTATION
@@ -3932,5 +3951,5 @@
                             CACHE_SLOT_STATE_ZOMBI );
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -4054,5 +4073,5 @@
                                 r_vci_rsp_fifo_dcache.read() );
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -4097,5 +4116,5 @@
             if ( r_dcache_miss_inval.read() ) // switch slot to ZOMBI state, and new cleanup
             {
-                if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
+                if ( not r_dcache_cc_send_req.read() ) // blocked until previous request sent
                 {
                     r_dcache_miss_inval     = false;
@@ -4114,12 +4133,10 @@
                                         CACHE_SLOT_STATE_ZOMBI );
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_MISS_DIR_UPDT> Switch slot to ZOMBI state"
-              << " PADDR = " << std::hex << r_dcache_save_paddr.read()
-              << " / WAY = "   << std::dec << r_dcache_miss_way.read()
-              << " / SET = "   << r_dcache_miss_set.read() << std::endl;
-}
+if ( m_debug_activated )
+std::cout << "  <PROC " << name()
+          << " DCACHE_MISS_DIR_UPDT> Switch slot to ZOMBI state"
+          << " PADDR = " << std::hex << r_dcache_save_paddr.read()
+          << " / WAY = "   << std::dec << r_dcache_miss_way.read()
+          << " / SET = "   << r_dcache_miss_set.read() << std::endl;
 #endif
                 }
@@ -4139,16 +4156,10 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_MISS_DIR_UPDT> Switch slot to VALID state"
-              << " PADDR = " << std::hex << r_dcache_save_paddr.read()
-              << " / WAY = "   << std::dec << r_dcache_miss_way.read()
-              << " / SET = "   << r_dcache_miss_set.read() << std::endl;
-
-//    r_dcache.printTrace();
-
-
-}
+if ( m_debug_activated )
+std::cout << "  <PROC " << name()
+          << " DCACHE_MISS_DIR_UPDT> Switch slot to VALID state"
+          << " PADDR = " << std::hex << r_dcache_save_paddr.read()
+          << " / WAY = "   << std::dec << r_dcache_miss_way.read()
+          << " / SET = "   << r_dcache_miss_set.read() << std::endl;
 #endif
                 // reset directory extension
@@ -4322,5 +4333,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -4362,5 +4373,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -4384,5 +4395,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -4390,7 +4401,10 @@
               << " r_dcache_vci_paddr = " << r_dcache_vci_paddr.read()
               << " mask = " << mask 
-              << " (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = " << (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT)
-              << " (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = " << (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)
-              << " ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = " << ((r_dcache_vci_paddr.read() & mask) == (paddr & mask))
+              << " (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = " 
+              << (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT)
+              << " (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = " 
+              << (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)
+              << " ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = " 
+              << ((r_dcache_vci_paddr.read() & mask) == (paddr & mask))
               <<std::endl;
 }
@@ -4420,5 +4434,5 @@
             r_cc_receive_dcache_req = false;
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -4454,5 +4468,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -4518,5 +4532,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -4557,5 +4571,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -4573,5 +4587,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -4629,5 +4643,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -4649,5 +4663,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -4722,5 +4736,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -4739,5 +4753,5 @@
                 r_dcache_cc_need_write = false;
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm )
+if ( m_debug_activated )
 {
     std::cout << "  <PROC " << name()
@@ -4793,5 +4807,5 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm and ok )
+if ( m_debug_activated and ok )
 {
     std::cout << "  <PROC " << name()
@@ -4809,12 +4823,10 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_dcache_fsm and ok )
-{
-    std::cout << "  <PROC " << name()
-              << ".DCACHE_INVAL_TLB_SCAN> Invalidate DTLB entry:" << std::hex
-              << " line = " << line << std::dec
-              << " / set = " << set
-              << " / way = " << way << std::endl;
-}
+if ( m_debug_activated and ok )
+std::cout << "  <PROC " << name() << " DCACHE_INVAL_TLB_SCAN>"
+          << " Invalidate DTLB entry" << std::hex
+          << " / line = " << line << std::dec
+          << " / set = " << set
+          << " / way = " << way << std::endl;
 #endif
         }
@@ -4911,5 +4923,5 @@
         case CMD_IDLE:
         {
-            // DDACHE read requests (r_dcache_vci_miss_req or r_dcache_vci_ll_req), and
+            // DCACHE read requests (r_dcache_vci_miss_req or r_dcache_vci_ll_req), and
             // ICACHE read requests (r_icache_miss_req) require both a write_buffer access
             // to check a possible pending write on the same cache line.
@@ -4936,5 +4948,4 @@
                      or r_vci_cmd_imiss_prio.read() );
 
-
             // 1 - Data Read Miss
             if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
@@ -4970,6 +4981,6 @@
             else if ( r_icache_unc_req.read() )
             {
-                r_vci_cmd_fsm    = CMD_INS_UNC;
-                r_icache_unc_req = false;
+                r_vci_cmd_fsm       = CMD_INS_UNC;
+                r_icache_unc_req    = false;
 //                m_cpt_iunc_transaction++;
             }
@@ -5000,4 +5011,14 @@
 //              m_cpt_cas_transaction++;
             }
+
+#if DEBUG_CMD
+if ( m_debug_activated )
+{
+std::cout << "  <PROC " << name() << " CMD_IDLE>"
+          << " / dmiss_req = " << dcache_miss_req
+          << " / imiss_req = " << icache_miss_req
+          << std::endl;
+}
+#endif
             break;
         }
@@ -5820,5 +5841,5 @@
 
     
-    // Send coherence packets on DSPIN L2M 
+    // Send coherence packets on DSPIN P2M 
     // it depends on the CC_SEND FSM 
 
@@ -5857,5 +5878,5 @@
 
                 DspinDhccpParam::dspin_set(dspin_send_data,
-                                           r_dcache_cc_send_nline.read() & 0x300000000ULL,
+                                           (r_dcache_cc_send_nline.read() & 0x300000000ULL)>>32,
                                            DspinDhccpParam::CLEANUP_NLINE_MSB);
 
@@ -5879,5 +5900,5 @@
 
                 DspinDhccpParam::dspin_set(dspin_send_data,
-                                           r_icache_cc_send_nline.read() & 0x300000000ULL,
+                                           (r_icache_cc_send_nline.read() & 0x300000000ULL)>>32,
                                            DspinDhccpParam::CLEANUP_NLINE_MSB);
 
