Changeset 396 for trunk/platforms/tsar_generic_xbar/top.cpp
- Timestamp:
- May 28, 2013, 11:02:08 AM (11 years ago)
- File:
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- 1 edited
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trunk/platforms/tsar_generic_xbar/top.cpp (modified) (25 diffs)
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trunk/platforms/tsar_generic_xbar/top.cpp
r389 r396 3 3 // Author: Alain Greiner 4 4 // Copyright: UPMC/LIP6 5 // Date : august 20125 // Date : may 2013 6 6 // This program is released under the GNU public license 7 7 ///////////////////////////////////////////////////////////////////////// 8 // This file define a generic TSAR architecture with virtual memory. 9 // The physical address space is 32 bits. 8 // This file define a generic TSAR architecture. 9 // The physical address space is 40 bits. 10 // 10 11 // The number of clusters cannot be larger than 256. 11 12 // The number of processors per cluster cannot be larger than 8. … … 15 16 // - It uses the vci_cc_vcache_wrapper 16 17 // - It uses the vci_mem_cache 17 // - It contains one vci_xicu and one vci_multi_dma per cluster. 18 // - It contains one vci_simple ram per cluster to model the L3 cache. 18 // - It contains one vci_xicu per cluster. 19 // - It contains one vci_multi_dma per cluster. 20 // - It contains one vci_simple_ram per cluster to model the L3 cache. 19 21 // 20 // All clusters are identical, but the cluster containing address 21 // 0xBFC00000 (called io_cluster), contains 5 extra components: 22 // The communication between the MemCache and the Xram is 64 bits. 23 // 24 // All clusters are identical, but the cluster 0 (called io_cluster), 25 // contains 5 extra components: 22 26 // - the boot rom (BROM) 23 27 // - the disk controller (BDEV) … … 26 30 // - the frame buffer controller (FBUF) 27 31 // 28 // It is build with one single component implementing a cluster: 29 // The Tsarv4ClusterMmu component is defined in files 30 // tsar_xbar_cluster.* (with * = cpp, h, sd) 32 // It is build with one single component implementing a cluster, 33 // defined in files tsar_xbar_cluster.* (with * = cpp, h, sd) 31 34 // 32 35 // The IRQs are connected to XICUs as follow: … … 36 39 // - The BDEV IRQ is connected to IRQ_IN[31] in I/O cluster. 37 40 // 38 // The main hardware parameters must be defined in the hard_config.h file : 41 // Some hardware parameters are used when compiling the OS, and are used 42 // by this top.cpp file. They must be defined in the hard_config.h file : 39 43 // - CLUSTER_X : number of clusters in a row (power of 2) 40 44 // - CLUSTER_Y : number of clusters in a column (power of 2) 41 45 // - CLUSTER_SIZE : size of the segment allocated to a cluster 42 46 // - NB_PROCS_MAX : number of processors per cluster (power of 2) 43 // - NB_DMA S_MAX: number of DMA channels per cluster (< 9)44 // - NB_TTY S : number of TTY channels in I/O cluster (< 16)45 // - NB_NIC S : number of NIC channels in I/O cluster (< 9)47 // - NB_DMA_CHANNELS : number of DMA channels per cluster (< 9) 48 // - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (< 16) 49 // - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (< 9) 46 50 // 47 // Some secondary hardware parameters must be defined in this top.cpp file: 51 // Some other hardware parameters are not used when compiling the OS, 52 // and can be directly defined in this top.cpp file: 48 53 // - XRAM_LATENCY : external ram latency 49 54 // - MEMC_WAYS : L2 cache number of ways … … 60 65 // - NIC_TX_NAME : file pathname for NIC transmited packets 61 66 // - NIC_TIMEOUT : max number of cycles before closing a container 62 // 63 // General policy for 32bits physical address decoding:64 // All segments base addresses are multiple of 64 Kbytes65 // Therefore the 16 address MSB bits completely define the target:67 ///////////////////////////////////////////////////////////////////////// 68 // General policy for 40 bits physical address decoding: 69 // All physical segments base addresses are multiple of 1 Mbytes 70 // (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) 66 71 // The (x_width + y_width) MSB bits (left aligned) define 67 // the cluster index, and the 8 LSBbits define the local index:72 // the cluster index, and the LADR bits define the local index: 68 73 // | X_ID | Y_ID |---| LADR | OFFSET | 69 // |x_width|y_width|---| 8 | 16|70 // 71 // General policy for hardware component indexing:72 // Each component is identified by (x_id, y_id,l_id) tuple.73 // | X_ID | Y_ID | L_ID |74 // |x_width|y_width| 4|74 // |x_width|y_width|---| 8 | 24 | 75 ///////////////////////////////////////////////////////////////////////// 76 // General policy for 14 bits SRCID decoding: 77 // Each component is identified by (x_id, y_id, l_id) tuple. 78 // | X_ID | Y_ID |---| L_ID | 79 // |x_width|y_width|---| 6 | 75 80 ///////////////////////////////////////////////////////////////////////// 76 81 … … 113 118 /////////////////////////////////////////////////////////// 114 119 115 #define cmd_width 40 116 #define rsp_width 33 120 #define dspin_cmd_width 40 121 #define dspin_rsp_width 33 122 123 /////////////////////////////////////////////////////////// 124 // VCI parameters 125 /////////////////////////////////////////////////////////// 126 127 #define int_vci_cell_width 4 128 #define int_vci_plen_width 8 129 #define int_vci_address_width 40 130 #define int_vci_rerror_width 1 131 #define int_vci_clen_width 1 132 #define int_vci_rflag_width 1 133 #define int_vci_srcid_width 14 134 #define int_vci_pktid_width 4 135 #define int_vci_trdid_width 4 136 #define int_vci_wrplen_width 1 137 138 #define ext_vci_cell_width 8 139 #define ext_vci_plen_width 8 140 #define ext_vci_address_width 40 141 #define ext_vci_rerror_width 1 142 #define ext_vci_clen_width 1 143 #define ext_vci_rflag_width 1 144 #define ext_vci_srcid_width 14 145 #define ext_vci_pktid_width 4 146 #define ext_vci_trdid_width 4 147 #define ext_vci_wrplen_width 1 117 148 118 149 //////////////////////////////////////////////////////////// … … 123 154 124 155 //////////////////////////////////////////////////////////// 125 // Secondary Hardware Parameters values156 // Secondary Hardware Parameters 126 157 //////////////////////i///////////////////////////////////// 127 158 … … 151 182 //////////////////////i///////////////////////////////////// 152 183 153 #define BOOT_SOFT_NAME "giet_vm/soft.elf"184 #define SOFT_NAME "giet_vm/soft.elf" 154 185 155 186 //////////////////////////////////////////////////////////// … … 159 190 #define MAX_FROZEN_CYCLES 10000 160 191 161 #define TRACE_MEMC_ID 0162 #define TRACE_PROC_ID 0192 #define TRACE_MEMC_ID 1000000 193 #define TRACE_PROC_ID 1000000 163 194 164 195 ///////////////////////////////////////////////////////// … … 172 203 // specific segments in "IO" cluster : absolute physical address 173 204 174 #define BROM_BASE 0xBFC00000175 #define BROM_SIZE 0x00100000 // 1 Mbytes176 177 #define FBUF_BASE 0xBFD00000178 #define FBUF_SIZE 0x00200000 // 2 Mbytes179 180 #define BDEV_BASE 0xBFF10000181 #define BDEV_SIZE 0x00001000 // 4 Kbytes182 183 #define MTTY_BASE 0xBFF20000184 #define MTTY_SIZE 0x00001000 // 4 Kbytes185 186 #define MNIC_BASE 0xBFF80000187 #define MNIC_SIZE 0x00002000 * (NB_NICS + 1) // 8 Kbytes per channel + 8 Kbytes205 #define BROM_BASE 0x00BFC00000 206 #define BROM_SIZE 0x0000100000 // 1 Mbytes 207 208 #define FBUF_BASE 0x00B2000000 209 #define FBUF_SIZE FBUF_X_SIZE * FBUF_Y_SIZE 210 211 #define BDEV_BASE 0x00B3000000 212 #define BDEV_SIZE 0x0000001000 // 4 Kbytes 213 214 #define MTTY_BASE 0x00B4000000 215 #define MTTY_SIZE 0x0000001000 // 4 Kbytes 216 217 #define MNIC_BASE 0x00B5000000 218 #define MNIC_SIZE 0x0000002000 * (NB_NIC_CHANNELS + 1) // 8 Kbytes per channel + 8 Kbytes 188 219 189 220 // replicated segments : address is incremented by a cluster offset 190 221 // offset = cluster(x,y) << (address_width-x_width-y_width); 191 222 192 #define MEMC_BASE 0x00000000193 #define MEMC_SIZE 0x00C00000 // 12 Mbytes194 195 #define XICU_BASE 0x00F00000196 #define XICU_SIZE 0x00001000 // 4 Kbytes197 198 #define CDMA_BASE 0x00F30000199 #define CDMA_SIZE 0x00001000 * NB_DMAS_MAX// 4 Kbytes per channel223 #define MEMC_BASE 0x0000000000 224 #define MEMC_SIZE 0x0010000000 // 256 Mbytes per cluster 225 226 #define XICU_BASE 0x00B0000000 227 #define XICU_SIZE 0x0000001000 // 4 Kbytes 228 229 #define MDMA_BASE 0x00B1000000 230 #define MDMA_SIZE 0x0000001000 * NB_DMA_CHANNELS // 4 Kbytes per channel 200 231 201 232 //////////////////////////////////////////////////////////////////// … … 204 235 //////////////////////////////////////////////////////////////////// 205 236 206 #define MEMC_TGTID 207 #define XICU_TGTID 208 #define CDMA_TGTID2209 #define MTTY_TGTID 210 #define FBUF_TGTID 211 #define B ROM_TGTID5212 #define BDEV_TGTID6213 #define MNIC_TGTID7237 #define MEMC_TGTID 0 238 #define XICU_TGTID 1 239 #define MDMA_TGTID 2 240 #define MTTY_TGTID 3 241 #define FBUF_TGTID 4 242 #define BDEV_TGTID 5 243 #define MNIC_TGTID 6 244 #define BROM_TGTID 7 214 245 215 246 ///////////////////////////////// … … 221 252 222 253 223 char soft_name[256] = BOOT_SOFT_NAME;// pathname to binary code254 char soft_name[256] = SOFT_NAME; // pathname to binary code 224 255 size_t ncycles = 1000000000; // simulated cycles 225 256 char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image … … 229 260 bool debug_ok = false; // trace activated 230 261 size_t debug_period = 1; // trace period 231 size_t debug_memc_id = TRACE_MEMC_ID; // index of memc to be traced (cluster_id)262 size_t debug_memc_id = TRACE_MEMC_ID; // index of memc to be traced 232 263 size_t debug_proc_id = TRACE_PROC_ID; // index of proc to be traced 233 264 uint32_t debug_from = 0; // trace start cycle 234 265 uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor 266 size_t cluster_io_id = 0; // index of cluster containing IOs 235 267 236 268 ////////////// command line arguments ////////////////////// … … 300 332 } 301 333 302 // checking hardware parameters 303 assert( ( (CLUSTER_X == 1) or (CLUSTER_X == 2) or (CLUSTER_X == 4) or 304 (CLUSTER_X == 8) or (CLUSTER_X == 16) ) and 305 "The CLUSTER_X parameter must be 1, 2, 4, 8 or 16" ); 306 307 assert( ( (CLUSTER_Y == 1) or (CLUSTER_Y == 2) or (CLUSTER_Y == 4) or 308 (CLUSTER_Y == 8) or (CLUSTER_Y == 16) ) and 309 "The CLUSTER_Y parameter must be 1, 2, 4, 8 or 16" ); 310 311 assert( ( (NB_PROCS_MAX == 1) or (NB_PROCS_MAX == 2) or 312 (NB_PROCS_MAX == 4) or (NB_PROCS_MAX == 8) ) and 313 "The NB_PROCS_MAX parameter must be 1, 2, 4 or 8" ); 314 315 assert( (NB_DMAS_MAX < 9) and 316 "The NB_DMAS_MAX parameter must be smaller than 9" ); 317 318 assert( (NB_TTYS < 15) and 319 "The NB_TTYS parameter must be smaller than 15" ); 320 321 assert( (NB_NICS < 9) and 322 "The NB_NICS parameter must be smaller than 9" ); 323 324 std::cout << std::endl; 325 std::cout << " - CLUSTER_X = " << CLUSTER_X << std::endl; 326 std::cout << " - CLUSTER_Y = " << CLUSTER_Y << std::endl; 327 std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl; 328 std::cout << " - NB_DMAS_MAX = " << NB_DMAS_MAX << std::endl; 329 std::cout << " - NB_TTYS = " << NB_TTYS << std::endl; 330 std::cout << " - NB_NICS = " << NB_NICS << std::endl; 331 std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl; 332 std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl; 333 std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl; 334 std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl; 335 336 std::cout << std::endl; 334 // checking hardware parameters 335 assert( ( (CLUSTER_X == 1) or (CLUSTER_X == 2) or (CLUSTER_X == 4) or 336 (CLUSTER_X == 8) or (CLUSTER_X == 16) ) and 337 "The CLUSTER_X parameter must be 1, 2, 4, 8 or 16" ); 338 339 assert( ( (CLUSTER_Y == 1) or (CLUSTER_Y == 2) or (CLUSTER_Y == 4) or 340 (CLUSTER_Y == 8) or (CLUSTER_Y == 16) ) and 341 "The CLUSTER_Y parameter must be 1, 2, 4, 8 or 16" ); 342 343 assert( ( (NB_PROCS_MAX == 1) or (NB_PROCS_MAX == 2) or 344 (NB_PROCS_MAX == 4) or (NB_PROCS_MAX == 8) ) and 345 "The NB_PROCS_MAX parameter must be 1, 2, 4 or 8" ); 346 347 assert( (NB_DMA_CHANNELS < 9) and 348 "The NB_DMA_CHANNELS parameter must be smaller than 9" ); 349 350 assert( (NB_TTY_CHANNELS < 15) and 351 "The NB_TTY_CHANNELS parameter must be smaller than 15" ); 352 353 assert( (NB_NIC_CHANNELS < 9) and 354 "The NB_NIC_CHANNELS parameter must be smaller than 9" ); 355 356 assert( (int_vci_address_width == ext_vci_address_width) and 357 "address widths must be equal on internal & external networks" ); 358 359 assert( (int_vci_address_width == 40) and 360 "VCI address width must be 40 bits" ); 361 362 std::cout << std::endl; 363 std::cout << " - CLUSTER_X = " << CLUSTER_X << std::endl; 364 std::cout << " - CLUSTER_Y = " << CLUSTER_Y << std::endl; 365 std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl; 366 std::cout << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl; 367 std::cout << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl; 368 std::cout << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl; 369 std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl; 370 std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl; 371 std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl; 372 std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl; 373 374 std::cout << std::endl; 375 376 // Internal and External VCI parameters definition 377 typedef soclib::caba::VciParams<int_vci_cell_width, 378 int_vci_plen_width, 379 int_vci_address_width, 380 int_vci_rerror_width, 381 int_vci_clen_width, 382 int_vci_rflag_width, 383 int_vci_srcid_width, 384 int_vci_pktid_width, 385 int_vci_trdid_width, 386 int_vci_wrplen_width> vci_param_int; 387 388 typedef soclib::caba::VciParamsBis<ext_vci_cell_width, 389 ext_vci_plen_width, 390 ext_vci_address_width, 391 ext_vci_rerror_width, 392 ext_vci_clen_width, 393 ext_vci_rflag_width, 394 ext_vci_srcid_width, 395 ext_vci_pktid_width, 396 ext_vci_trdid_width, 397 ext_vci_wrplen_width> vci_param_ext; 337 398 338 399 #if USE_OPENMP … … 343 404 344 405 // Define parameters depending on mesh size 345 size_t cluster_io_id;346 406 size_t x_width; 347 407 size_t y_width; … … 359 419 else y_width = 4; 360 420 361 cluster_io_id = 0xBF >> (8 - x_width - y_width);362 363 421 ///////////////////// 364 422 // Mapping Tables 365 423 ///////////////////// 366 424 367 // directnetwork368 MappingTable maptabd( address_width,369 IntTab(x_width + y_width, 16 - x_width - y_width),370 IntTab(x_width + y_width,srcid_width - x_width - y_width),371 0x00FF0000);425 // internal network 426 MappingTable maptabd(int_vci_address_width, 427 IntTab(x_width + y_width, 16 - x_width - y_width), 428 IntTab(x_width + y_width, int_vci_srcid_width - x_width - y_width), 429 0x00FF000000); 372 430 373 431 for (size_t x = 0; x < CLUSTER_X; x++) … … 375 433 for (size_t y = 0; y < CLUSTER_Y; y++) 376 434 { 377 sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width); 435 sc_uint<int_vci_address_width> offset; 436 offset = (sc_uint<int_vci_address_width>)cluster(x,y) 437 << (int_vci_address_width-x_width-y_width); 378 438 379 439 std::ostringstream sh; 380 sh << "d_seg_memc_" << x << "_" << y; 381 maptabd.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE, IntTab(cluster(x,y),MEMC_TGTID), true)); 440 sh << "seg_memc_" << x << "_" << y; 441 maptabd.add(Segment(sh.str(), MEMC_BASE+offset, MEMC_SIZE, 442 IntTab(cluster(x,y),MEMC_TGTID), true)); 382 443 383 444 std::ostringstream si; 384 si << "d_seg_xicu_" << x << "_" << y; 385 maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE, IntTab(cluster(x,y),XICU_TGTID), false)); 445 si << "seg_xicu_" << x << "_" << y; 446 maptabd.add(Segment(si.str(), XICU_BASE+offset, XICU_SIZE, 447 IntTab(cluster(x,y),XICU_TGTID), false)); 386 448 387 449 std::ostringstream sd; 388 sd << "d_seg_mdma_" << x << "_" << y; 389 maptabd.add(Segment(sd.str(), CDMA_BASE+offset, CDMA_SIZE, IntTab(cluster(x,y),CDMA_TGTID), false)); 450 sd << "seg_mdma_" << x << "_" << y; 451 maptabd.add(Segment(sd.str(), MDMA_BASE+offset, MDMA_SIZE, 452 IntTab(cluster(x,y),MDMA_TGTID), false)); 390 453 391 454 if ( cluster(x,y) == cluster_io_id ) 392 455 { 393 maptabd.add(Segment("d_seg_mtty", MTTY_BASE, MTTY_SIZE, IntTab(cluster(x,y),MTTY_TGTID), false)); 394 maptabd.add(Segment("d_seg_fbuf", FBUF_BASE, FBUF_SIZE, IntTab(cluster(x,y),FBUF_TGTID), false)); 395 maptabd.add(Segment("d_seg_bdev", BDEV_BASE, BDEV_SIZE, IntTab(cluster(x,y),BDEV_TGTID), false)); 396 maptabd.add(Segment("d_seg_mnic", MNIC_BASE, MNIC_SIZE, IntTab(cluster(x,y),MNIC_TGTID), false)); 397 maptabd.add(Segment("d_seg_brom", BROM_BASE, BROM_SIZE, IntTab(cluster(x,y),BROM_TGTID), true)); 456 maptabd.add(Segment("seg_mtty", MTTY_BASE, MTTY_SIZE, 457 IntTab(cluster(x,y),MTTY_TGTID), false)); 458 maptabd.add(Segment("seg_fbuf", FBUF_BASE, FBUF_SIZE, 459 IntTab(cluster(x,y),FBUF_TGTID), false)); 460 maptabd.add(Segment("seg_bdev", BDEV_BASE, BDEV_SIZE, 461 IntTab(cluster(x,y),BDEV_TGTID), false)); 462 maptabd.add(Segment("seg_mnic", MNIC_BASE, MNIC_SIZE, 463 IntTab(cluster(x,y),MNIC_TGTID), false)); 464 maptabd.add(Segment("seg_brom", BROM_BASE, BROM_SIZE, 465 IntTab(cluster(x,y),BROM_TGTID), true)); 398 466 } 399 467 } … … 402 470 403 471 // external network 404 MappingTable maptabx(address_width, IntTab(1), IntTab(x_width+y_width), 0xF0000000); 472 MappingTable maptabx(ext_vci_address_width, 473 IntTab(x_width+y_width), 474 IntTab(x_width+y_width), 475 0xFFFF000000ULL); 405 476 406 477 for (size_t x = 0; x < CLUSTER_X; x++) … … 408 479 for (size_t y = 0; y < CLUSTER_Y ; y++) 409 480 { 410 sc_uint<address_width> offset = cluster(x,y) << (address_width-x_width-y_width); 481 482 sc_uint<ext_vci_address_width> offset; 483 offset = (sc_uint<ext_vci_address_width>)cluster(x,y) 484 << (ext_vci_address_width-x_width-y_width); 485 411 486 std::ostringstream sh; 412 487 sh << "x_seg_memc_" << x << "_" << y; 488 413 489 maptabx.add(Segment(sh.str(), MEMC_BASE+offset, 414 490 MEMC_SIZE, IntTab(cluster(x,y)), false)); … … 425 501 426 502 // Horizontal inter-clusters DSPIN signals 427 DspinSignals< cmd_width>*** signal_dspin_h_cmd_inc =428 alloc_elems<DspinSignals< cmd_width> >("signal_dspin_h_cmd_inc", CLUSTER_X-1, CLUSTER_Y, 2);429 DspinSignals< cmd_width>*** signal_dspin_h_cmd_dec =430 alloc_elems<DspinSignals< cmd_width> >("signal_dspin_h_cmd_dec", CLUSTER_X-1, CLUSTER_Y, 2);431 DspinSignals< rsp_width>*** signal_dspin_h_rsp_inc =432 alloc_elems<DspinSignals< rsp_width> >("signal_dspin_h_rsp_inc", CLUSTER_X-1, CLUSTER_Y, 2);433 DspinSignals< rsp_width>*** signal_dspin_h_rsp_dec =434 alloc_elems<DspinSignals< rsp_width> >("signal_dspin_h_rsp_dec", CLUSTER_X-1, CLUSTER_Y, 2);503 DspinSignals<dspin_cmd_width>*** signal_dspin_h_cmd_inc = 504 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", CLUSTER_X-1, CLUSTER_Y, 2); 505 DspinSignals<dspin_cmd_width>*** signal_dspin_h_cmd_dec = 506 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", CLUSTER_X-1, CLUSTER_Y, 2); 507 DspinSignals<dspin_rsp_width>*** signal_dspin_h_rsp_inc = 508 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", CLUSTER_X-1, CLUSTER_Y, 2); 509 DspinSignals<dspin_rsp_width>*** signal_dspin_h_rsp_dec = 510 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", CLUSTER_X-1, CLUSTER_Y, 2); 435 511 436 512 // Vertical inter-clusters DSPIN signals 437 DspinSignals< cmd_width>*** signal_dspin_v_cmd_inc =438 alloc_elems<DspinSignals< cmd_width> >("signal_dspin_v_cmd_inc", CLUSTER_X, CLUSTER_Y-1, 2);439 DspinSignals< cmd_width>*** signal_dspin_v_cmd_dec =440 alloc_elems<DspinSignals< cmd_width> >("signal_dspin_v_cmd_dec", CLUSTER_X, CLUSTER_Y-1, 2);441 DspinSignals< rsp_width>*** signal_dspin_v_rsp_inc =442 alloc_elems<DspinSignals< rsp_width> >("signal_dspin_v_rsp_inc", CLUSTER_X, CLUSTER_Y-1, 2);443 DspinSignals< rsp_width>*** signal_dspin_v_rsp_dec =444 alloc_elems<DspinSignals< rsp_width> >("signal_dspin_v_rsp_dec", CLUSTER_X, CLUSTER_Y-1, 2);513 DspinSignals<dspin_cmd_width>*** signal_dspin_v_cmd_inc = 514 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", CLUSTER_X, CLUSTER_Y-1, 2); 515 DspinSignals<dspin_cmd_width>*** signal_dspin_v_cmd_dec = 516 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", CLUSTER_X, CLUSTER_Y-1, 2); 517 DspinSignals<dspin_rsp_width>*** signal_dspin_v_rsp_inc = 518 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", CLUSTER_X, CLUSTER_Y-1, 2); 519 DspinSignals<dspin_rsp_width>*** signal_dspin_v_rsp_dec = 520 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", CLUSTER_X, CLUSTER_Y-1, 2); 445 521 446 522 // Mesh boundaries DSPIN signals 447 DspinSignals< cmd_width>**** signal_dspin_false_cmd_in =448 alloc_elems<DspinSignals< cmd_width> >("signal_dspin_false_cmd_in", CLUSTER_X, CLUSTER_Y, 2, 4);449 DspinSignals< cmd_width>**** signal_dspin_false_cmd_out =450 alloc_elems<DspinSignals< cmd_width> >("signal_dspin_false_cmd_out", CLUSTER_X, CLUSTER_Y, 2, 4);451 DspinSignals< rsp_width>**** signal_dspin_false_rsp_in =452 alloc_elems<DspinSignals< rsp_width> >("signal_dspin_false_rsp_in", CLUSTER_X, CLUSTER_Y, 2, 4);453 DspinSignals< rsp_width>**** signal_dspin_false_rsp_out =454 alloc_elems<DspinSignals< rsp_width> >("signal_dspin_false_rsp_out", CLUSTER_X, CLUSTER_Y, 2, 4);523 DspinSignals<dspin_cmd_width>**** signal_dspin_false_cmd_in = 524 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_in", CLUSTER_X, CLUSTER_Y, 2, 4); 525 DspinSignals<dspin_cmd_width>**** signal_dspin_false_cmd_out = 526 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_false_cmd_out", CLUSTER_X, CLUSTER_Y, 2, 4); 527 DspinSignals<dspin_rsp_width>**** signal_dspin_false_rsp_in = 528 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_in", CLUSTER_X, CLUSTER_Y, 2, 4); 529 DspinSignals<dspin_rsp_width>**** signal_dspin_false_rsp_out = 530 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_false_rsp_out", CLUSTER_X, CLUSTER_Y, 2, 4); 455 531 456 532 … … 474 550 //////////////////////////// 475 551 476 TsarXbarCluster< 477 proc_iss, cmd_width, rsp_width 478 > * clusters[CLUSTER_X][CLUSTER_Y]; 552 TsarXbarCluster<dspin_cmd_width, 553 dspin_rsp_width, 554 vci_param_int, 555 vci_param_ext>* clusters[CLUSTER_X][CLUSTER_Y]; 479 556 480 557 #if USE_OPENMP … … 496 573 std::ostringstream sc; 497 574 sc << "cluster_" << x << "_" << y; 498 clusters[x][y] = new TsarXbarCluster< 499 proc_iss, cmd_width, rsp_width 500 > 575 clusters[x][y] = new TsarXbarCluster<dspin_cmd_width, 576 dspin_rsp_width, 577 vci_param_int, 578 vci_param_ext> 501 579 ( 502 580 sc.str().c_str(), 503 NB_PROCS_MAX , NB_TTYS , NB_DMAS_MAX , // cluster params 504 x , y , cluster(x,y), // mesh coordinates 505 maptabd , maptabx , // mapping tables 506 x_width , y_width , srcid_width - x_width - y_width, // srcid width, 507 MEMC_TGTID , XICU_TGTID , CDMA_TGTID , // 508 FBUF_TGTID , MTTY_TGTID , BROM_TGTID , // targets ids 509 MNIC_TGTID , BDEV_TGTID, // 510 MEMC_WAYS , MEMC_SETS , // MC params 511 L1_IWAYS , L1_ISETS , L1_DWAYS , L1_DSETS, // L1 params 512 XRAM_LATENCY , // 513 is_io_cluster, // is IO cluster ? 514 FBUF_X_SIZE , FBUF_Y_SIZE , // FB params 515 disk_name , BDEV_SECTOR_SIZE, // IOC params 516 NB_NICS , nic_rx_name , nic_tx_name , NIC_TIMEOUT, // NIC params 517 loader , 581 <<<<<<< .mine 582 NB_PROCS_MAX, 583 NB_TTY_CHANNELS, 584 NB_DMA_CHANNELS, 585 x, 586 y, 587 cluster(x,y), 588 maptabd, 589 maptabx, 590 x_width, 591 y_width, 592 int_vci_srcid_width - x_width - y_width, // l_id width, 593 MEMC_TGTID, 594 XICU_TGTID, 595 MDMA_TGTID, 596 FBUF_TGTID, 597 MTTY_TGTID, 598 BROM_TGTID, 599 MNIC_TGTID, 600 BDEV_TGTID, 601 MEMC_WAYS, 602 MEMC_SETS, 603 L1_IWAYS, 604 L1_ISETS, 605 L1_DWAYS, 606 L1_DSETS, 607 XRAM_LATENCY, 608 (cluster(x,y) == cluster_io_id), 609 FBUF_X_SIZE, 610 FBUF_Y_SIZE, 611 disk_name, 612 BDEV_SECTOR_SIZE, 613 NB_NIC_CHANNELS, 614 nic_rx_name, 615 nic_tx_name, 616 NIC_TIMEOUT, 617 loader, 518 618 frozen_cycles, 519 619 debug_from , … … 617 717 } 618 718 } 719 std::cout << "North, South, West, East connections established" << std::endl; 720 std::cout << std::endl; 619 721 620 722 … … 650 752 for (size_t n = 1; n < ncycles; n++) 651 753 { 754 // Monitor a specific address for L1 & L2 caches 755 //clusters[0][0]->proc[0]->cache_monitor(0x800002c000ULL); 756 //clusters[1][0]->memc->copies_monitor(0x800002C000ULL); 757 652 758 if (debug_ok and (n > debug_from) and (n % debug_period == 0)) 653 759 { 654 760 std::cout << "****************** cycle " << std::dec << n ; 655 761 std::cout << " ************************************************" << std::endl; 656 /* 657 clusters[0][0]->proc[0]->print_trace(); 658 clusters[0][0]->signal_vci_ini_proc[0].print_trace("DIRECT proc_0_0_0 vci_ini"); 659 clusters[0][0]->signal_dspin_cmd_proc_i[0].print_trace("DIRECT cmd_out_proc_0_0_0"); 660 clusters[0][0]->signal_dspin_rsp_proc_i[0].print_trace("DIRECT rsp_in_proc_0_0_0"); 661 clusters[0][0]->signal_dspin_p2m_proc[0].print_trace("COHERENCE p2m_proc_0_0_0"); 662 clusters[0][0]->signal_dspin_m2p_proc[0].print_trace("COHERENCE m2p_proc_0_0_0"); 663 clusters[0][0]->memc->print_trace(); 664 clusters[0][0]->signal_vci_tgt_memc.print_trace("DIRECT memc_0_0_vci_tgt"); 665 clusters[0][0]->signal_dspin_cmd_memc_t.print_trace("DIRECT cmd_memc_0_0"); 666 clusters[0][0]->signal_dspin_rsp_memc_t.print_trace("DIRECT rsp_memc_0_0"); 667 clusters[0][0]->signal_dspin_p2m_memc.print_trace("COHERENCE p2m_memc_0_0"); 668 clusters[0][0]->signal_dspin_m2p_memc.print_trace("COHERENCE m2p_memc_0_0"); 669 clusters[0][0]->signal_vci_tgt_brom.print_trace("DIRECT brom vci_tgt_0_0"); 670 clusters[0][0]->signal_dspin_cmd_brom_t.print_trace("DIRECT cmd_in_brom_0_0"); 671 clusters[0][0]->signal_dspin_rsp_brom_t.print_trace("DIRECT rsp_out_brom_0_0"); 672 673 clusters[0][1]->proc[0]->print_trace(); 674 clusters[0][1]->signal_vci_ini_proc[0].print_trace("DIRECT proc_0_1_0 vci_ini"); 675 clusters[0][1]->signal_dspin_cmd_proc_i[0].print_trace("DIRECT cmd_out_proc_0_1_0"); 676 clusters[0][1]->signal_dspin_rsp_proc_i[0].print_trace("DIRECT rsp_in_proc_0_1_0"); 677 clusters[0][1]->signal_dspin_p2m_proc[0].print_trace("COHERENCE p2m_proc_0_1_0"); 678 clusters[0][1]->signal_dspin_m2p_proc[0].print_trace("COHERENCE m2p_proc_0_1_0"); 679 clusters[0][1]->memc->print_trace(); 680 clusters[0][1]->signal_vci_tgt_memc.print_trace("DIRECT memc_0_1_vci_tgt"); 681 clusters[0][1]->signal_dspin_cmd_memc_t.print_trace("DIRECT cmd_memc_0_1"); 682 clusters[0][1]->signal_dspin_rsp_memc_t.print_trace("DIRECT rsp_memc_0_1"); 683 clusters[0][1]->signal_dspin_p2m_memc.print_trace("COHERENCE p2m_memc_0_1"); 684 clusters[0][1]->signal_dspin_m2p_memc.print_trace("COHERENCE m2p_memc_0_1"); 685 clusters[0][1]->signal_vci_tgt_brom.print_trace("DIRECT brom vci_tgt_0_1"); 686 clusters[0][1]->signal_dspin_cmd_brom_t.print_trace("DIRECT cmd_in_brom_0_1"); 687 clusters[0][1]->signal_dspin_rsp_brom_t.print_trace("DIRECT rsp_out_brom_0_1"); 688 689 clusters[1][0]->proc[0]->print_trace(); 690 clusters[1][0]->signal_vci_ini_proc[0].print_trace("DIRECT proc_1_0_0 vci_ini"); 691 clusters[1][0]->signal_dspin_cmd_proc_i[0].print_trace("DIRECT cmd_out_proc_1_0_0"); 692 clusters[1][0]->signal_dspin_rsp_proc_i[0].print_trace("DIRECT rsp_in_proc_1_0_0"); 693 clusters[1][0]->signal_dspin_p2m_proc[0].print_trace("COHERENCE p2m_proc_1_0_0"); 694 clusters[1][0]->signal_dspin_m2p_proc[0].print_trace("COHERENCE m2p_proc_1_0_0"); 695 clusters[1][0]->memc->print_trace(); 696 clusters[1][0]->signal_vci_tgt_memc.print_trace("DIRECT memc_1_0_vci_tgt"); 697 clusters[1][0]->signal_dspin_cmd_memc_t.print_trace("DIRECT cmd_memc_1_0"); 698 clusters[1][0]->signal_dspin_rsp_memc_t.print_trace("DIRECT rsp_memc_1_0"); 699 clusters[1][0]->signal_dspin_p2m_memc.print_trace("COHERENCE p2m_memc_1_0"); 700 clusters[1][0]->signal_dspin_m2p_memc.print_trace("COHERENCE m2p_memc_1_0"); 701 clusters[1][0]->signal_vci_tgt_brom.print_trace("DIRECT brom vci_tgt_1_0"); 702 clusters[1][0]->signal_dspin_cmd_brom_t.print_trace("DIRECT cmd_in_brom_1_0"); 703 clusters[1][0]->signal_dspin_rsp_brom_t.print_trace("DIRECT rsp_out_brom_1_0"); 704 705 clusters[1][1]->proc[0]->print_trace(); 706 clusters[1][1]->signal_vci_ini_proc[0].print_trace("DIRECT proc_1_1_0 vci_ini"); 707 clusters[1][1]->signal_dspin_cmd_proc_i[0].print_trace("DIRECT cmd_out_proc_1_1_0"); 708 clusters[1][1]->signal_dspin_rsp_proc_i[0].print_trace("DIRECT rsp_in_proc_1_1_0"); 709 clusters[1][1]->signal_dspin_p2m_proc[0].print_trace("COHERENCE p2m_proc_1_1_0"); 710 clusters[1][1]->signal_dspin_m2p_proc[0].print_trace("COHERENCE m2p_proc_1_1_0"); 711 clusters[1][1]->memc->print_trace(); 712 clusters[1][1]->signal_vci_tgt_memc.print_trace("DIRECT memc_1_1_vci_tgt"); 713 clusters[1][1]->signal_dspin_cmd_memc_t.print_trace("DIRECT cmd_memc_1_1"); 714 clusters[1][1]->signal_dspin_rsp_memc_t.print_trace("DIRECT rsp_memc_1_1"); 715 clusters[1][1]->signal_dspin_p2m_memc.print_trace("COHERENCE p2m_memc_1_1"); 716 clusters[1][1]->signal_dspin_m2p_memc.print_trace("COHERENCE m2p_memc_1_1"); 717 clusters[1][1]->signal_vci_tgt_brom.print_trace("DIRECT brom vci_tgt_1_1"); 718 clusters[1][1]->signal_dspin_cmd_brom_t.print_trace("DIRECT cmd_in_brom_1_1"); 719 clusters[1][1]->signal_dspin_rsp_brom_t.print_trace("DIRECT rsp_out_brom_1_1"); 720 */ 762 721 763 // trace proc[debug_proc_id] 722 764 if ( debug_proc_id < (CLUSTER_X * CLUSTER_Y * NB_PROCS_MAX) ) 723 765 { 724 size_t l = debug_proc_id % (CLUSTER_X * CLUSTER_Y);766 size_t l = debug_proc_id % NB_PROCS_MAX ; 725 767 size_t y = (debug_proc_id / NB_PROCS_MAX) % CLUSTER_Y ; 726 768 size_t x = debug_proc_id / (CLUSTER_Y * NB_PROCS_MAX) ; 727 769 728 std::ostringstream signame; 729 signame << "VCI signal PROC_" << x << "_" << y << "_" << l; 770 std::ostringstream vci_signame; 771 vci_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; 772 std::ostringstream p2m_signame; 773 p2m_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " P2M" ; 774 std::ostringstream m2p_signame; 775 m2p_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " M2P" ; 730 776 731 777 clusters[x][y]->proc[l]->print_trace(); 732 clusters[x][y]->signal_vci_ini_proc[l].print_trace("signame"); 778 clusters[x][y]->signal_vci_ini_proc[l].print_trace(vci_signame.str()); 779 clusters[x][y]->signal_dspin_p2m_proc[l].print_trace(p2m_signame.str()); 780 clusters[x][y]->signal_dspin_m2p_proc[l].print_trace(m2p_signame.str()); 733 781 } 734 /*735 782 // trace memc[debug_memc_id] 736 783 if ( debug_memc_id < (CLUSTER_X * CLUSTER_Y) ) … … 739 786 size_t y = debug_memc_id % CLUSTER_Y; 740 787 741 std::ostringstream signame; 742 signame << "VCI signal MEMC_" << x << "_" << y; 743 744 clusters[memc_x][memc_y]->memc->print_trace(); 745 clusters[memc_x][memc_y]->signal_vci_tgt_memc.print_trace("signame"); 788 std::ostringstream smemc; 789 smemc << "[SIG]MEMC_" << x << "_" << y; 790 std::ostringstream sxram; 791 sxram << "[SIG]XRAM_" << x << "_" << y; 792 std::ostringstream sm2p; 793 sm2p << "[SIG]MEMC_" << x << "_" << y << " M2P" ; 794 std::ostringstream sp2m; 795 sp2m << "[SIG]MEMC_" << x << "_" << y << " P2M" ; 796 797 clusters[x][y]->memc->print_trace(); 798 clusters[x][y]->xram->print_trace(); 799 clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str()); 800 clusters[x][y]->signal_vci_xram.print_trace(sxram.str()); 801 clusters[x][y]->signal_dspin_p2m_memc.print_trace(sp2m.str()); 802 clusters[x][y]->signal_dspin_m2p_memc.print_trace(sm2p.str()); 746 803 } 747 */ 804 805 // trace replicated peripherals 806 clusters[1][1]->mdma->print_trace(); 807 clusters[1][1]->signal_vci_tgt_mdma.print_trace("[SIG]MDMA_TGT_1_1"); 808 clusters[1][1]->signal_vci_ini_mdma.print_trace("[SIG]MDMA_INI_1_1"); 809 810 748 811 // trace external peripherals 749 812 size_t io_x = cluster_io_id / CLUSTER_Y; 750 813 size_t io_y = cluster_io_id % CLUSTER_Y; 751 814 752 clusters[io_x][io_y]->signal_vci_tgt_mtty.print_trace("VCI signal TTY"); 753 /* 815 // clusters[io_x][io_y]->brom->print_trace(); 816 // clusters[io_x][io_y]->signal_vci_tgt_brom.print_trace("/SIG/BROM"); 817 // clusters[io_x][io_y]->signal_vci_tgt_mtty.print_trace("VCI signal TTY"); 818 754 819 clusters[io_x][io_y]->bdev->print_trace(); 755 clusters[io_x][io_y]->signal_vci_tgt_bdev.print_trace("VCI signal BDEV_TGT"); 756 clusters[io_x][io_y]->signal_vci_ini_bdev.print_trace("VCI signal BDEV_INI"); 757 */ 820 clusters[io_x][io_y]->signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT"); 821 clusters[io_x][io_y]->signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI"); 758 822 } 759 823
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